Home Explore Help
Register Sign In
RD_Software
/
linux-arkmicro
2
0
Fork 1
Files Issues 0 Pull Requests 0 Wiki
Tree: 31daef21e5
Branches Tags
linux-arkmicro
/
u-boot
/
arch
/
arm
/
include
/
asm
/
arch-am33xx
/
hardware.h

hardware.h 2.2 KB
History Raw

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889 
  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * hardware.h
    4. 

  4.  *
    5. 

  5.  * hardware specific header
    6. 

  6.  *
    7. 

  7.  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
    8. 

  8.  */
    9. 

  9. 

  10. #ifndef __AM33XX_HARDWARE_H
    11. 

  11. #define __AM33XX_HARDWARE_H
    12. 

  12. 

  13. #include <config.h>
    14. 

  14. #include <asm/arch/omap.h>
    15. 

  15. #ifdef CONFIG_AM33XX
    16. 

  16. #include <asm/arch/hardware_am33xx.h>
    17. 

  17. #elif defined(CONFIG_TI816X)
    18. 

  18. #include <asm/arch/hardware_ti816x.h>
    19. 

  19. #elif defined(CONFIG_TI814X)
    20. 

  20. #include <asm/arch/hardware_ti814x.h>
    21. 

  21. #elif defined(CONFIG_AM43XX)
    22. 

  22. #include <asm/arch/hardware_am43xx.h>
    23. 

  23. #endif
    24. 

  24. 

  25. /*
    26. 

  26.  * Common hardware definitions
    27. 

  27.  */
    28. 

  28. 

  29. /* DM Timer base addresses */
    30. 

  30. #define DM_TIMER0_BASE			0x4802C000
    31. 

  31. #define DM_TIMER1_BASE			0x4802E000
    32. 

  32. #define DM_TIMER2_BASE			0x48040000
    33. 

  33. #define DM_TIMER3_BASE			0x48042000
    34. 

  34. #define DM_TIMER4_BASE			0x48044000
    35. 

  35. #define DM_TIMER5_BASE			0x48046000
    36. 

  36. #define DM_TIMER6_BASE			0x48048000
    37. 

  37. #define DM_TIMER7_BASE			0x4804A000
    38. 

  38. 

  39. /* GPIO Base address */
    40. 

  40. #define GPIO0_BASE			0x48032000
    41. 

  41. #define GPIO1_BASE			0x4804C000
    42. 

  42. 

  43. /* BCH Error Location Module */
    44. 

  44. #define ELM_BASE			0x48080000
    45. 

  45. 

  46. /* EMIF Base address */
    47. 

  47. #define EMIF4_0_CFG_BASE		0x4C000000
    48. 

  48. #define EMIF4_1_CFG_BASE		0x4D000000
    49. 

  49. 

  50. /* DDR Base address */
    51. 

  51. #define DDR_CTRL_ADDR			0x44E10E04
    52. 

  52. #define DDR_CONTROL_BASE_ADDR		0x44E11404
    53. 

  53. 

  54. /* UART */
    55. 

  55. #if CONFIG_CONS_INDEX == 1
    56. 

  56. #	define DEFAULT_UART_BASE UART0_BASE
    57. 

  57. #elif CONFIG_CONS_INDEX == 2
    58. 

  58. #	define DEFAULT_UART_BASE UART1_BASE
    59. 

  59. #elif CONFIG_CONS_INDEX == 3
    60. 

  60. #	define DEFAULT_UART_BASE UART2_BASE
    61. 

  61. #elif CONFIG_CONS_INDEX == 4
    62. 

  62. #	define DEFAULT_UART_BASE UART3_BASE
    63. 

  63. #elif CONFIG_CONS_INDEX == 5
    64. 

  64. #	define DEFAULT_UART_BASE UART4_BASE
    65. 

  65. #elif CONFIG_CONS_INDEX == 6
    66. 

  66. #	define DEFAULT_UART_BASE UART5_BASE
    67. 

  67. #endif
    68. 

  68. 

  69. /* GPMC Base address */
    70. 

  70. #define GPMC_BASE			0x50000000
    71. 

  71. 

  72. /* CPSW Config space */
    73. 

  73. #define CPSW_BASE			0x4A100000
    74. 

  74. 

  75. /* Control status register */
    76. 

  76. #define CTRL_CRYSTAL_FREQ_SRC_MASK		(1 << 31)
    77. 

  77. #define CTRL_CRYSTAL_FREQ_SRC_SHIFT		31
    78. 

  78. #define CTRL_CRYSTAL_FREQ_SELECTION_MASK	(0x3 << 29)
    79. 

  79. #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT	29
    80. 

  80. #define CTRL_SYSBOOT_15_14_MASK			(0x3 << 22)
    81. 

  81. #define CTRL_SYSBOOT_15_14_SHIFT		22
    82. 

  82. 

  83. #define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT		0x0
    84. 

  84. #define CTRL_CRYSTAL_FREQ_SRC_EFUSE		0x1
    85. 

  85. 

  86. #define NUM_CRYSTAL_FREQ			0x4
    87. 

  87. 

  88. int clk_get(int clk);
    89. 

  89. #endif /* __AM33XX_HARDWARE_H */
    90.