regs-uart.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  4. */
  5. #ifndef __REGS_UART_H__
  6. #define __REGS_UART_H__
  7. #define FFUART_BASE 0x40100000
  8. #define BTUART_BASE 0x40200000
  9. #define STUART_BASE 0x40700000
  10. #define HWUART_BASE 0x41600000
  11. struct pxa_uart_regs {
  12. union {
  13. uint32_t thr;
  14. uint32_t rbr;
  15. uint32_t dll;
  16. };
  17. union {
  18. uint32_t ier;
  19. uint32_t dlh;
  20. };
  21. union {
  22. uint32_t fcr;
  23. uint32_t iir;
  24. };
  25. uint32_t lcr;
  26. uint32_t mcr;
  27. uint32_t lsr;
  28. uint32_t msr;
  29. uint32_t spr;
  30. uint32_t isr;
  31. };
  32. #define IER_DMAE (1 << 7)
  33. #define IER_UUE (1 << 6)
  34. #define IER_NRZE (1 << 5)
  35. #define IER_RTIOE (1 << 4)
  36. #define IER_MIE (1 << 3)
  37. #define IER_RLSE (1 << 2)
  38. #define IER_TIE (1 << 1)
  39. #define IER_RAVIE (1 << 0)
  40. #define IIR_FIFOES1 (1 << 7)
  41. #define IIR_FIFOES0 (1 << 6)
  42. #define IIR_TOD (1 << 3)
  43. #define IIR_IID2 (1 << 2)
  44. #define IIR_IID1 (1 << 1)
  45. #define IIR_IP (1 << 0)
  46. #define FCR_ITL2 (1 << 7)
  47. #define FCR_ITL1 (1 << 6)
  48. #define FCR_RESETTF (1 << 2)
  49. #define FCR_RESETRF (1 << 1)
  50. #define FCR_TRFIFOE (1 << 0)
  51. #define FCR_ITL_1 0
  52. #define FCR_ITL_8 (FCR_ITL1)
  53. #define FCR_ITL_16 (FCR_ITL2)
  54. #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
  55. #define LCR_DLAB (1 << 7)
  56. #define LCR_SB (1 << 6)
  57. #define LCR_STKYP (1 << 5)
  58. #define LCR_EPS (1 << 4)
  59. #define LCR_PEN (1 << 3)
  60. #define LCR_STB (1 << 2)
  61. #define LCR_WLS1 (1 << 1)
  62. #define LCR_WLS0 (1 << 0)
  63. #define LSR_FIFOE (1 << 7)
  64. #define LSR_TEMT (1 << 6)
  65. #define LSR_TDRQ (1 << 5)
  66. #define LSR_BI (1 << 4)
  67. #define LSR_FE (1 << 3)
  68. #define LSR_PE (1 << 2)
  69. #define LSR_OE (1 << 1)
  70. #define LSR_DR (1 << 0)
  71. #define MCR_LOOP (1 << 4)
  72. #define MCR_OUT2 (1 << 3)
  73. #define MCR_OUT1 (1 << 2)
  74. #define MCR_RTS (1 << 1)
  75. #define MCR_DTR (1 << 0)
  76. #define MSR_DCD (1 << 7)
  77. #define MSR_RI (1 << 6)
  78. #define MSR_DSR (1 << 5)
  79. #define MSR_CTS (1 << 4)
  80. #define MSR_DDCD (1 << 3)
  81. #define MSR_TERI (1 << 2)
  82. #define MSR_DDSR (1 << 1)
  83. #define MSR_DCTS (1 << 0)
  84. #endif /* __REGS_UART_H__ */