lpc32xx_dma.c 3.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008 by NXP Semiconductors
  4. * @Author: Kevin Wells
  5. * @Descr: LPC3250 DMA controller interface support functions
  6. *
  7. * Copyright (c) 2015 Tyco Fire Protection Products.
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <asm/arch/dma.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/io.h>
  16. /* DMA controller channel register structure */
  17. struct dmac_chan_reg {
  18. u32 src_addr;
  19. u32 dest_addr;
  20. u32 lli;
  21. u32 control;
  22. u32 config_ch;
  23. u32 reserved[3];
  24. };
  25. /* DMA controller register structures */
  26. struct dma_reg {
  27. u32 int_stat;
  28. u32 int_tc_stat;
  29. u32 int_tc_clear;
  30. u32 int_err_stat;
  31. u32 int_err_clear;
  32. u32 raw_tc_stat;
  33. u32 raw_err_stat;
  34. u32 chan_enable;
  35. u32 sw_burst_req;
  36. u32 sw_single_req;
  37. u32 sw_last_burst_req;
  38. u32 sw_last_single_req;
  39. u32 config;
  40. u32 sync;
  41. u32 reserved[50];
  42. struct dmac_chan_reg dma_chan[8];
  43. };
  44. #define DMA_NO_OF_CHANNELS 8
  45. /* config register definitions */
  46. #define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */
  47. static u32 alloc_ch;
  48. static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;
  49. int lpc32xx_dma_get_channel(void)
  50. {
  51. int i;
  52. if (!alloc_ch) { /* First time caller */
  53. /*
  54. * DMA clock are enable by "lpc32xx_dma_init()" and should
  55. * be call by board "board_early_init_f()" function.
  56. */
  57. /*
  58. * Make sure DMA controller and all channels are disabled.
  59. * Controller is in little-endian mode. Disable sync signals.
  60. */
  61. writel(0, &dma->config);
  62. writel(0, &dma->sync);
  63. /* Clear interrupt and error statuses */
  64. writel(0xFF, &dma->int_tc_clear);
  65. writel(0xFF, &dma->raw_tc_stat);
  66. writel(0xFF, &dma->int_err_clear);
  67. writel(0xFF, &dma->raw_err_stat);
  68. /* Enable DMA controller */
  69. writel(DMAC_CTRL_ENABLE, &dma->config);
  70. }
  71. i = ffz(alloc_ch);
  72. /* Check if all the available channels are busy */
  73. if (unlikely(i == DMA_NO_OF_CHANNELS))
  74. return -1;
  75. alloc_ch |= BIT_MASK(i);
  76. return i;
  77. }
  78. int lpc32xx_dma_start_xfer(unsigned int channel,
  79. const struct lpc32xx_dmac_ll *desc, u32 config)
  80. {
  81. if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) ||
  82. (channel >= DMA_NO_OF_CHANNELS))) {
  83. pr_err("Request for xfer on unallocated channel %d", channel);
  84. return -1;
  85. }
  86. writel(BIT_MASK(channel), &dma->int_tc_clear);
  87. writel(BIT_MASK(channel), &dma->int_err_clear);
  88. writel(desc->dma_src, &dma->dma_chan[channel].src_addr);
  89. writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr);
  90. writel(desc->next_lli, &dma->dma_chan[channel].lli);
  91. writel(desc->next_ctrl, &dma->dma_chan[channel].control);
  92. writel(config, &dma->dma_chan[channel].config_ch);
  93. return 0;
  94. }
  95. int lpc32xx_dma_wait_status(unsigned int channel)
  96. {
  97. unsigned long start;
  98. u32 reg;
  99. /* Check if given channel is valid */
  100. if (unlikely(channel >= DMA_NO_OF_CHANNELS)) {
  101. pr_err("Request for status on unallocated channel %d", channel);
  102. return -1;
  103. }
  104. start = get_timer(0);
  105. while (1) {
  106. reg = readl(&dma->raw_tc_stat);
  107. reg |= readl(dma->raw_err_stat);
  108. if (reg & BIT_MASK(channel))
  109. break;
  110. if (get_timer(start) > CONFIG_SYS_HZ) {
  111. pr_err("DMA status timeout channel %d\n", channel);
  112. return -ETIMEDOUT;
  113. }
  114. udelay(1);
  115. }
  116. if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) {
  117. setbits_le32(&dma->int_err_clear, BIT_MASK(channel));
  118. setbits_le32(&dma->raw_err_stat, BIT_MASK(channel));
  119. pr_err("DMA error on channel %d\n", channel);
  120. return -1;
  121. }
  122. setbits_le32(&dma->int_tc_clear, BIT_MASK(channel));
  123. setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel));
  124. return 0;
  125. }