Kconfig 13 KB

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  1. #
  2. # I2C subsystem configuration
  3. #
  4. menu "I2C support"
  5. config DM_I2C
  6. bool "Enable Driver Model for I2C drivers"
  7. depends on DM
  8. help
  9. Enable driver model for I2C. The I2C uclass interface: probe, read,
  10. write and speed, is implemented with the bus drivers operations,
  11. which provide methods for bus setting and data transfer. Each chip
  12. device (bus child) info is kept as parent platdata. The interface
  13. is defined in include/i2c.h. When i2c bus driver supports the i2c
  14. uclass, but the device drivers not, then DM_I2C_COMPAT config can
  15. be used as compatibility layer.
  16. config DM_I2C_COMPAT
  17. bool "Enable I2C compatibility layer"
  18. depends on DM
  19. help
  20. Enable old-style I2C functions for compatibility with existing code.
  21. This option can be enabled as a temporary measure to avoid needing
  22. to convert all code for a board in a single commit. It should not
  23. be enabled for any board in an official release.
  24. config I2C_CROS_EC_TUNNEL
  25. tristate "Chrome OS EC tunnel I2C bus"
  26. depends on CROS_EC
  27. help
  28. This provides an I2C bus that will tunnel i2c commands through to
  29. the other side of the Chrome OS EC to the I2C bus connected there.
  30. This will work whatever the interface used to talk to the EC (SPI,
  31. I2C or LPC). Some Chromebooks use this when the hardware design
  32. does not allow direct access to the main PMIC from the AP.
  33. config I2C_CROS_EC_LDO
  34. bool "Provide access to LDOs on the Chrome OS EC"
  35. depends on CROS_EC
  36. ---help---
  37. On many Chromebooks the main PMIC is inaccessible to the AP. This is
  38. often dealt with by using an I2C pass-through interface provided by
  39. the EC. On some unfortunate models (e.g. Spring) the pass-through
  40. is not available, and an LDO message is available instead. This
  41. option enables a driver which provides very basic access to those
  42. regulators, via the EC. We implement this as an I2C bus which
  43. emulates just the TPS65090 messages we know about. This is done to
  44. avoid duplicating the logic in the TPS65090 regulator driver for
  45. enabling/disabling an LDO.
  46. config I2C_SET_DEFAULT_BUS_NUM
  47. bool "Set default I2C bus number"
  48. depends on DM_I2C
  49. help
  50. Set default number of I2C bus to be accessed. This option provides
  51. behaviour similar to old (i.e. pre DM) I2C bus driver.
  52. config I2C_DEFAULT_BUS_NUMBER
  53. hex "I2C default bus number"
  54. depends on I2C_SET_DEFAULT_BUS_NUM
  55. default 0x0
  56. help
  57. Number of default I2C bus to use
  58. config DM_I2C_GPIO
  59. bool "Enable Driver Model for software emulated I2C bus driver"
  60. depends on DM_I2C && DM_GPIO
  61. help
  62. Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
  63. configuration is given by the device tree. Kernel-style device tree
  64. bindings are supported.
  65. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
  66. config SYS_I2C_AT91
  67. bool "Atmel I2C driver"
  68. depends on DM_I2C && ARCH_AT91
  69. help
  70. Add support for the Atmel I2C driver. A serious problem is that there
  71. is no documented way to issue repeated START conditions for more than
  72. two messages, as needed to support combined I2C messages. Use the
  73. i2c-gpio driver unless your system can cope with this limitation.
  74. Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
  75. config SYS_I2C_FSL
  76. bool "Freescale I2C bus driver"
  77. depends on DM_I2C
  78. help
  79. Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
  80. MPC85xx processors.
  81. config SYS_I2C_CADENCE
  82. tristate "Cadence I2C Controller"
  83. depends on DM_I2C && (ARCH_ZYNQ || ARM64)
  84. help
  85. Say yes here to select Cadence I2C Host Controller. This controller is
  86. e.g. used by Xilinx Zynq.
  87. config SYS_I2C_DW
  88. bool "Designware I2C Controller"
  89. default n
  90. help
  91. Say yes here to select the Designware I2C Host Controller. This
  92. controller is used in various SoCs, e.g. the ST SPEAr, Altera
  93. SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
  94. config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  95. bool "DW I2C Enable Status Register not supported"
  96. depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
  97. TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
  98. default y
  99. help
  100. Some versions of the Designware I2C controller do not support the
  101. enable status register. This config option can be enabled in such
  102. cases.
  103. config SYS_I2C_ASPEED
  104. bool "Aspeed I2C Controller"
  105. depends on DM_I2C && ARCH_ASPEED
  106. help
  107. Say yes here to select Aspeed I2C Host Controller. The driver
  108. supports AST2500 and AST2400 controllers, but is very limited.
  109. Only single master mode is supported and only byte-by-byte
  110. synchronous reads and writes are supported, no Pool Buffers or DMA.
  111. config SYS_I2C_INTEL
  112. bool "Intel I2C/SMBUS driver"
  113. depends on DM_I2C
  114. help
  115. Add support for the Intel SMBUS driver. So far this driver is just
  116. a stub which perhaps some basic init. There is no implementation of
  117. the I2C API meaning that any I2C operations will immediately fail
  118. for now.
  119. config SYS_I2C_IMX_LPI2C
  120. bool "NXP i.MX LPI2C driver"
  121. help
  122. Add support for the NXP i.MX LPI2C driver.
  123. config SYS_I2C_MESON
  124. bool "Amlogic Meson I2C driver"
  125. depends on DM_I2C && ARCH_MESON
  126. help
  127. Add support for the I2C controller available in Amlogic Meson
  128. SoCs. The controller supports programmable bus speed including
  129. standard (100kbits/s) and fast (400kbit/s) speed and allows the
  130. software to define a flexible format of the bit streams. It has an
  131. internal buffer holding up to 8 bytes for transfers and supports
  132. both 7-bit and 10-bit addresses.
  133. config SYS_I2C_MXC
  134. bool "NXP MXC I2C driver"
  135. help
  136. Add support for the NXP I2C driver. This supports upto for bus
  137. channels and operating on standard mode upto 100 kbits/s and fast
  138. mode upto 400 kbits/s.
  139. if SYS_I2C_MXC
  140. config SYS_I2C_MXC_I2C1
  141. bool "NXP MXC I2C1"
  142. help
  143. Add support for NXP MXC I2C Controller 1.
  144. Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
  145. config SYS_I2C_MXC_I2C2
  146. bool "NXP MXC I2C2"
  147. help
  148. Add support for NXP MXC I2C Controller 2.
  149. Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
  150. config SYS_I2C_MXC_I2C3
  151. bool "NXP MXC I2C3"
  152. help
  153. Add support for NXP MXC I2C Controller 3.
  154. Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
  155. config SYS_I2C_MXC_I2C4
  156. bool "NXP MXC I2C4"
  157. help
  158. Add support for NXP MXC I2C Controller 4.
  159. Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
  160. config SYS_I2C_MXC_I2C5
  161. bool "NXP MXC I2C5"
  162. help
  163. Add support for NXP MXC I2C Controller 5.
  164. Required for SoCs which have I2C MXC controller 5 eg LX2160A
  165. config SYS_I2C_MXC_I2C6
  166. bool "NXP MXC I2C6"
  167. help
  168. Add support for NXP MXC I2C Controller 6.
  169. Required for SoCs which have I2C MXC controller 6 eg LX2160A
  170. config SYS_I2C_MXC_I2C7
  171. bool "NXP MXC I2C7"
  172. help
  173. Add support for NXP MXC I2C Controller 7.
  174. Required for SoCs which have I2C MXC controller 7 eg LX2160A
  175. config SYS_I2C_MXC_I2C8
  176. bool "NXP MXC I2C8"
  177. help
  178. Add support for NXP MXC I2C Controller 8.
  179. Required for SoCs which have I2C MXC controller 8 eg LX2160A
  180. endif
  181. if SYS_I2C_MXC_I2C1
  182. config SYS_MXC_I2C1_SPEED
  183. int "I2C Channel 1 speed"
  184. default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
  185. default 100000
  186. help
  187. MXC I2C Channel 1 speed
  188. config SYS_MXC_I2C1_SLAVE
  189. int "I2C1 Slave"
  190. default 0
  191. help
  192. MXC I2C1 Slave
  193. endif
  194. if SYS_I2C_MXC_I2C2
  195. config SYS_MXC_I2C2_SPEED
  196. int "I2C Channel 2 speed"
  197. default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
  198. default 100000
  199. help
  200. MXC I2C Channel 2 speed
  201. config SYS_MXC_I2C2_SLAVE
  202. int "I2C2 Slave"
  203. default 0
  204. help
  205. MXC I2C2 Slave
  206. endif
  207. if SYS_I2C_MXC_I2C3
  208. config SYS_MXC_I2C3_SPEED
  209. int "I2C Channel 3 speed"
  210. default 100000
  211. help
  212. MXC I2C Channel 3 speed
  213. config SYS_MXC_I2C3_SLAVE
  214. int "I2C3 Slave"
  215. default 0
  216. help
  217. MXC I2C3 Slave
  218. endif
  219. if SYS_I2C_MXC_I2C4
  220. config SYS_MXC_I2C4_SPEED
  221. int "I2C Channel 4 speed"
  222. default 100000
  223. help
  224. MXC I2C Channel 4 speed
  225. config SYS_MXC_I2C4_SLAVE
  226. int "I2C4 Slave"
  227. default 0
  228. help
  229. MXC I2C4 Slave
  230. endif
  231. if SYS_I2C_MXC_I2C5
  232. config SYS_MXC_I2C5_SPEED
  233. int "I2C Channel 5 speed"
  234. default 100000
  235. help
  236. MXC I2C Channel 5 speed
  237. config SYS_MXC_I2C5_SLAVE
  238. int "I2C5 Slave"
  239. default 0
  240. help
  241. MXC I2C5 Slave
  242. endif
  243. if SYS_I2C_MXC_I2C6
  244. config SYS_MXC_I2C6_SPEED
  245. int "I2C Channel 6 speed"
  246. default 100000
  247. help
  248. MXC I2C Channel 6 speed
  249. config SYS_MXC_I2C6_SLAVE
  250. int "I2C6 Slave"
  251. default 0
  252. help
  253. MXC I2C6 Slave
  254. endif
  255. if SYS_I2C_MXC_I2C7
  256. config SYS_MXC_I2C7_SPEED
  257. int "I2C Channel 7 speed"
  258. default 100000
  259. help
  260. MXC I2C Channel 7 speed
  261. config SYS_MXC_I2C7_SLAVE
  262. int "I2C7 Slave"
  263. default 0
  264. help
  265. MXC I2C7 Slave
  266. endif
  267. if SYS_I2C_MXC_I2C8
  268. config SYS_MXC_I2C8_SPEED
  269. int "I2C Channel 8 speed"
  270. default 100000
  271. help
  272. MXC I2C Channel 8 speed
  273. config SYS_MXC_I2C8_SLAVE
  274. int "I2C8 Slave"
  275. default 0
  276. help
  277. MXC I2C8 Slave
  278. endif
  279. config SYS_I2C_OMAP24XX
  280. bool "TI OMAP2+ I2C driver"
  281. depends on ARCH_OMAP2PLUS
  282. help
  283. Add support for the OMAP2+ I2C driver.
  284. if SYS_I2C_OMAP24XX
  285. config SYS_OMAP24_I2C_SLAVE
  286. int "I2C Slave addr channel 0"
  287. default 1
  288. help
  289. OMAP24xx I2C Slave address channel 0
  290. config SYS_OMAP24_I2C_SPEED
  291. int "I2C Slave channel 0 speed"
  292. default 100000
  293. help
  294. OMAP24xx Slave speed channel 0
  295. endif
  296. config SYS_I2C_RCAR_I2C
  297. bool "Renesas RCar I2C driver"
  298. depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
  299. help
  300. Support for Renesas RCar I2C controller.
  301. config SYS_I2C_RCAR_IIC
  302. bool "Renesas RCar Gen3 IIC driver"
  303. depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
  304. help
  305. Support for Renesas RCar Gen3 IIC controller.
  306. config SYS_I2C_ROCKCHIP
  307. bool "Rockchip I2C driver"
  308. depends on DM_I2C
  309. help
  310. Add support for the Rockchip I2C driver. This is used with various
  311. Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
  312. have several I2C ports and all are provided, controled by the
  313. device tree.
  314. config SYS_I2C_SANDBOX
  315. bool "Sandbox I2C driver"
  316. depends on SANDBOX && DM_I2C
  317. help
  318. Enable I2C support for sandbox. This is an emulation of a real I2C
  319. bus. Devices can be attached to the bus using the device tree
  320. which specifies the driver to use. See sandbox.dts as an example.
  321. config SYS_I2C_S3C24X0
  322. bool "Samsung I2C driver"
  323. depends on ARCH_EXYNOS4 && DM_I2C
  324. help
  325. Support for Samsung I2C controller as Samsung SoCs.
  326. config SYS_I2C_STM32F7
  327. bool "STMicroelectronics STM32F7 I2C support"
  328. depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
  329. help
  330. Enable this option to add support for STM32 I2C controller
  331. introduced with STM32F7/H7 SoCs. This I2C controller supports :
  332. _ Slave and master modes
  333. _ Multimaster capability
  334. _ Standard-mode (up to 100 kHz)
  335. _ Fast-mode (up to 400 kHz)
  336. _ Fast-mode Plus (up to 1 MHz)
  337. _ 7-bit and 10-bit addressing mode
  338. _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
  339. _ All 7-bit addresses acknowledge mode
  340. _ General call
  341. _ Programmable setup and hold times
  342. _ Easy to use event management
  343. _ Optional clock stretching
  344. _ Software reset
  345. config SYS_I2C_UNIPHIER
  346. bool "UniPhier I2C driver"
  347. depends on ARCH_UNIPHIER && DM_I2C
  348. default y
  349. help
  350. Support for UniPhier I2C controller driver. This I2C controller
  351. is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
  352. config SYS_I2C_UNIPHIER_F
  353. bool "UniPhier FIFO-builtin I2C driver"
  354. depends on ARCH_UNIPHIER && DM_I2C
  355. default y
  356. help
  357. Support for UniPhier FIFO-builtin I2C controller driver.
  358. This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
  359. config SYS_I2C_MVTWSI
  360. bool "Marvell I2C driver"
  361. depends on DM_I2C
  362. help
  363. Support for Marvell I2C controllers as used on the orion5x and
  364. kirkwood SoC families.
  365. config TEGRA186_BPMP_I2C
  366. bool "Enable Tegra186 BPMP-based I2C driver"
  367. depends on TEGRA186_BPMP
  368. help
  369. Support for Tegra I2C controllers managed by the BPMP (Boot and
  370. Power Management Processor). On Tegra186, some I2C controllers are
  371. directly controlled by the main CPU, whereas others are controlled
  372. by the BPMP, and can only be accessed by the main CPU via IPC
  373. requests to the BPMP. This driver covers the latter case.
  374. config SYS_I2C_BUS_MAX
  375. int "Max I2C busses"
  376. depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
  377. default 2 if TI816X
  378. default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
  379. default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
  380. default 5 if OMAP54XX
  381. help
  382. Define the maximum number of available I2C buses.
  383. config SYS_I2C_ZYNQ
  384. bool "Xilinx I2C driver"
  385. depends on ARCH_ZYNQMP || ARCH_ZYNQ
  386. help
  387. Support for Xilinx I2C controller.
  388. config SYS_I2C_ZYNQ_SLAVE
  389. hex "Set slave addr"
  390. depends on SYS_I2C_ZYNQ
  391. default 0
  392. help
  393. Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr.
  394. config SYS_I2C_ZYNQ_SPEED
  395. int "Set I2C speed"
  396. depends on SYS_I2C_ZYNQ
  397. default 100000
  398. help
  399. Set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting.
  400. config ZYNQ_I2C0
  401. bool "Xilinx I2C0 controller"
  402. depends on SYS_I2C_ZYNQ
  403. help
  404. Enable Xilinx I2C0 controller.
  405. config ZYNQ_I2C1
  406. bool "Xilinx I2C1 controller"
  407. depends on SYS_I2C_ZYNQ
  408. help
  409. Enable Xilinx I2C1 controller.
  410. config SYS_I2C_IHS
  411. bool "gdsys IHS I2C driver"
  412. depends on DM_I2C
  413. help
  414. Support for gdsys IHS I2C driver on FPGA bus.
  415. source "drivers/i2c/muxes/Kconfig"
  416. endmenu