pmic_hi6553.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Linaro
  4. * Peter Griffin <peter.griffin@linaro.org>
  5. */
  6. #include <asm/io.h>
  7. #include <common.h>
  8. #include <power/pmic.h>
  9. #include <power/max8997_muic.h>
  10. #include <power/hi6553_pmic.h>
  11. #include <errno.h>
  12. u8 *pmussi_base;
  13. uint8_t hi6553_readb(u32 offset)
  14. {
  15. return readb(pmussi_base + (offset << 2));
  16. }
  17. void hi6553_writeb(u32 offset, uint8_t value)
  18. {
  19. writeb(value, pmussi_base + (offset << 2));
  20. }
  21. int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
  22. {
  23. if (check_reg(p, reg))
  24. return -EINVAL;
  25. hi6553_writeb(reg, (uint8_t)val);
  26. return 0;
  27. }
  28. int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
  29. {
  30. if (check_reg(p, reg))
  31. return -EINVAL;
  32. *val = (u32)hi6553_readb(reg);
  33. return 0;
  34. }
  35. static void hi6553_init(void)
  36. {
  37. int data;
  38. hi6553_writeb(HI6553_PERI_EN_MARK, 0x1e);
  39. hi6553_writeb(HI6553_NP_REG_ADJ1, 0);
  40. data = HI6553_DISABLE6_XO_CLK_CONN | HI6553_DISABLE6_XO_CLK_NFC |
  41. HI6553_DISABLE6_XO_CLK_RF1 | HI6553_DISABLE6_XO_CLK_RF2;
  42. hi6553_writeb(HI6553_DISABLE6_XO_CLK, data);
  43. /* configure BUCK0 & BUCK1 */
  44. hi6553_writeb(HI6553_BUCK01_CTRL2, 0x5e);
  45. hi6553_writeb(HI6553_BUCK0_CTRL7, 0x10);
  46. hi6553_writeb(HI6553_BUCK1_CTRL7, 0x10);
  47. hi6553_writeb(HI6553_BUCK0_CTRL5, 0x1e);
  48. hi6553_writeb(HI6553_BUCK1_CTRL5, 0x1e);
  49. hi6553_writeb(HI6553_BUCK0_CTRL1, 0xfc);
  50. hi6553_writeb(HI6553_BUCK1_CTRL1, 0xfc);
  51. /* configure BUCK2 */
  52. hi6553_writeb(HI6553_BUCK2_REG1, 0x4f);
  53. hi6553_writeb(HI6553_BUCK2_REG5, 0x99);
  54. hi6553_writeb(HI6553_BUCK2_REG6, 0x45);
  55. mdelay(1);
  56. hi6553_writeb(HI6553_VSET_BUCK2_ADJ, 0x22);
  57. mdelay(1);
  58. /* configure BUCK3 */
  59. hi6553_writeb(HI6553_BUCK3_REG3, 0x02);
  60. hi6553_writeb(HI6553_BUCK3_REG5, 0x99);
  61. hi6553_writeb(HI6553_BUCK3_REG6, 0x41);
  62. hi6553_writeb(HI6553_VSET_BUCK3_ADJ, 0x02);
  63. mdelay(1);
  64. /* configure BUCK4 */
  65. hi6553_writeb(HI6553_BUCK4_REG2, 0x9a);
  66. hi6553_writeb(HI6553_BUCK4_REG5, 0x99);
  67. hi6553_writeb(HI6553_BUCK4_REG6, 0x45);
  68. /* configure LDO20 */
  69. hi6553_writeb(HI6553_LDO20_REG_ADJ, 0x50);
  70. hi6553_writeb(HI6553_NP_REG_CHG, 0x0f);
  71. hi6553_writeb(HI6553_CLK_TOP0, 0x06);
  72. hi6553_writeb(HI6553_CLK_TOP3, 0xc0);
  73. hi6553_writeb(HI6553_CLK_TOP4, 0x00);
  74. /* configure LDO7 & LDO10 for SD slot */
  75. data = hi6553_readb(HI6553_LDO7_REG_ADJ);
  76. data = (data & 0xf8) | 0x2;
  77. hi6553_writeb(HI6553_LDO7_REG_ADJ, data);
  78. mdelay(5);
  79. /* enable LDO7 */
  80. hi6553_writeb(HI6553_ENABLE2_LDO1_8, 1 << 6);
  81. mdelay(5);
  82. data = hi6553_readb(HI6553_LDO10_REG_ADJ);
  83. data = (data & 0xf8) | 0x5;
  84. hi6553_writeb(HI6553_LDO10_REG_ADJ, data);
  85. mdelay(5);
  86. /* enable LDO10 */
  87. hi6553_writeb(HI6553_ENABLE3_LDO9_16, 1 << 1);
  88. mdelay(5);
  89. /* select 32.764KHz */
  90. hi6553_writeb(HI6553_CLK19M2_600_586_EN, 0x01);
  91. }
  92. int power_hi6553_init(u8 *base)
  93. {
  94. static const char name[] = "HI6553 PMIC";
  95. struct pmic *p = pmic_alloc();
  96. if (!p) {
  97. printf("%s: POWER allocation error!\n", __func__);
  98. return -ENOMEM;
  99. }
  100. p->name = name;
  101. p->interface = PMIC_NONE;
  102. p->number_of_regs = 44;
  103. pmussi_base = base;
  104. hi6553_init();
  105. puts("HI6553 PMIC init\n");
  106. return 0;
  107. }