README 3.5 KB

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  1. OpenRISC Linux
  2. ==============
  3. This is a port of Linux to the OpenRISC class of microprocessors; the initial
  4. target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k).
  5. For information about OpenRISC processors and ongoing development:
  6. website http://openrisc.io
  7. email openrisc@lists.librecores.org
  8. ---------------------------------------------------------------------
  9. Build instructions for OpenRISC toolchain and Linux
  10. ===================================================
  11. In order to build and run Linux for OpenRISC, you'll need at least a basic
  12. toolchain and, perhaps, the architectural simulator. Steps to get these bits
  13. in place are outlined here.
  14. 1) Toolchain
  15. Toolchain binaries can be obtained from openrisc.io or our github releases page.
  16. Instructions for building the different toolchains can be found on openrisc.io
  17. or Stafford's toolchain build and release scripts.
  18. binaries https://github.com/openrisc/or1k-gcc/releases
  19. toolchains https://openrisc.io/software
  20. building https://github.com/stffrdhrn/or1k-toolchain-build
  21. 2) Building
  22. Build the Linux kernel as usual
  23. make ARCH=openrisc defconfig
  24. make ARCH=openrisc
  25. 3) Running on FPGA (optional)
  26. The OpenRISC community typically uses FuseSoC to manage building and programming
  27. an SoC into an FPGA. The below is an example of programming a De0 Nano
  28. development board with the OpenRISC SoC. During the build FPGA RTL is code
  29. downloaded from the FuseSoC IP cores repository and built using the FPGA vendor
  30. tools. Binaries are loaded onto the board with openocd.
  31. git clone https://github.com/olofk/fusesoc
  32. cd fusesoc
  33. sudo pip install -e .
  34. fusesoc init
  35. fusesoc build de0_nano
  36. fusesoc pgm de0_nano
  37. openocd -f interface/altera-usb-blaster.cfg \
  38. -f board/or1k_generic.cfg
  39. telnet localhost 4444
  40. > init
  41. > halt; load_image vmlinux ; reset
  42. 4) Running on a Simulator (optional)
  43. QEMU is a processor emulator which we recommend for simulating the OpenRISC
  44. platform. Please follow the OpenRISC instructions on the QEMU website to get
  45. Linux running on QEMU. You can build QEMU yourself, but your Linux distribution
  46. likely provides binary packages to support OpenRISC.
  47. qemu openrisc https://wiki.qemu.org/Documentation/Platforms/OpenRISC
  48. ---------------------------------------------------------------------
  49. Terminology
  50. ===========
  51. In the code, the following particles are used on symbols to limit the scope
  52. to more or less specific processor implementations:
  53. openrisc: the OpenRISC class of processors
  54. or1k: the OpenRISC 1000 family of processors
  55. or1200: the OpenRISC 1200 processor
  56. ---------------------------------------------------------------------
  57. History
  58. ========
  59. 18. 11. 2003 Matjaz Breskvar (phoenix@bsemi.com)
  60. initial port of linux to OpenRISC/or32 architecture.
  61. all the core stuff is implemented and seams usable.
  62. 08. 12. 2003 Matjaz Breskvar (phoenix@bsemi.com)
  63. complete change of TLB miss handling.
  64. rewrite of exceptions handling.
  65. fully functional sash-3.6 in default initrd.
  66. a much improved version with changes all around.
  67. 10. 04. 2004 Matjaz Breskvar (phoenix@bsemi.com)
  68. alot of bugfixes all over.
  69. ethernet support, functional http and telnet servers.
  70. running many standard linux apps.
  71. 26. 06. 2004 Matjaz Breskvar (phoenix@bsemi.com)
  72. port to 2.6.x
  73. 30. 11. 2004 Matjaz Breskvar (phoenix@bsemi.com)
  74. lots of bugfixes and enhancments.
  75. added opencores framebuffer driver.
  76. 09. 10. 2010 Jonas Bonn (jonas@southpole.se)
  77. major rewrite to bring up to par with upstream Linux 2.6.36