ps3vram.c 22 KB

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  1. /*
  2. * ps3vram - Use extra PS3 video ram as block device.
  3. *
  4. * Copyright 2009 Sony Corporation
  5. *
  6. * Based on the MTD ps3vram driver, which is
  7. * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
  8. * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
  9. */
  10. #include <linux/blkdev.h>
  11. #include <linux/delay.h>
  12. #include <linux/module.h>
  13. #include <linux/proc_fs.h>
  14. #include <linux/seq_file.h>
  15. #include <linux/slab.h>
  16. #include <asm/cell-regs.h>
  17. #include <asm/firmware.h>
  18. #include <asm/lv1call.h>
  19. #include <asm/ps3.h>
  20. #include <asm/ps3gpu.h>
  21. #define DEVICE_NAME "ps3vram"
  22. #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  23. #define XDR_IOIF 0x0c000000
  24. #define FIFO_BASE XDR_IOIF
  25. #define FIFO_SIZE (64 * 1024)
  26. #define DMA_PAGE_SIZE (4 * 1024)
  27. #define CACHE_PAGE_SIZE (256 * 1024)
  28. #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  29. #define CACHE_OFFSET CACHE_PAGE_SIZE
  30. #define FIFO_OFFSET 0
  31. #define CTRL_PUT 0x10
  32. #define CTRL_GET 0x11
  33. #define CTRL_TOP 0x15
  34. #define UPLOAD_SUBCH 1
  35. #define DOWNLOAD_SUBCH 2
  36. #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
  37. #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
  38. #define CACHE_PAGE_PRESENT 1
  39. #define CACHE_PAGE_DIRTY 2
  40. struct ps3vram_tag {
  41. unsigned int address;
  42. unsigned int flags;
  43. };
  44. struct ps3vram_cache {
  45. unsigned int page_count;
  46. unsigned int page_size;
  47. struct ps3vram_tag *tags;
  48. unsigned int hit;
  49. unsigned int miss;
  50. };
  51. struct ps3vram_priv {
  52. struct request_queue *queue;
  53. struct gendisk *gendisk;
  54. u64 size;
  55. u64 memory_handle;
  56. u64 context_handle;
  57. u32 __iomem *ctrl;
  58. void __iomem *reports;
  59. u8 *xdr_buf;
  60. u32 *fifo_base;
  61. u32 *fifo_ptr;
  62. struct ps3vram_cache cache;
  63. spinlock_t lock; /* protecting list of bios */
  64. struct bio_list list;
  65. };
  66. static int ps3vram_major;
  67. static const struct block_device_operations ps3vram_fops = {
  68. .owner = THIS_MODULE,
  69. };
  70. #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  71. #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
  72. #define DMA_NOTIFIER_SIZE 0x40
  73. #define NOTIFIER 7 /* notifier used for completion report */
  74. static char *size = "256M";
  75. module_param(size, charp, 0);
  76. MODULE_PARM_DESC(size, "memory size");
  77. static u32 __iomem *ps3vram_get_notifier(void __iomem *reports, int notifier)
  78. {
  79. return reports + DMA_NOTIFIER_OFFSET_BASE +
  80. DMA_NOTIFIER_SIZE * notifier;
  81. }
  82. static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
  83. {
  84. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  85. u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  86. int i;
  87. for (i = 0; i < 4; i++)
  88. iowrite32be(0xffffffff, notify + i);
  89. }
  90. static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
  91. unsigned int timeout_ms)
  92. {
  93. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  94. u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  95. unsigned long timeout;
  96. for (timeout = 20; timeout; timeout--) {
  97. if (!ioread32be(notify + 3))
  98. return 0;
  99. udelay(10);
  100. }
  101. timeout = jiffies + msecs_to_jiffies(timeout_ms);
  102. do {
  103. if (!ioread32be(notify + 3))
  104. return 0;
  105. msleep(1);
  106. } while (time_before(jiffies, timeout));
  107. return -ETIMEDOUT;
  108. }
  109. static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
  110. {
  111. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  112. iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
  113. iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_GET);
  114. }
  115. static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
  116. unsigned int timeout_ms)
  117. {
  118. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  119. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  120. do {
  121. if (ioread32be(priv->ctrl + CTRL_PUT) == ioread32be(priv->ctrl + CTRL_GET))
  122. return 0;
  123. msleep(1);
  124. } while (time_before(jiffies, timeout));
  125. dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
  126. ioread32be(priv->ctrl + CTRL_PUT), ioread32be(priv->ctrl + CTRL_GET),
  127. ioread32be(priv->ctrl + CTRL_TOP));
  128. return -ETIMEDOUT;
  129. }
  130. static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
  131. {
  132. *(priv->fifo_ptr)++ = data;
  133. }
  134. static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
  135. u32 size)
  136. {
  137. ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
  138. }
  139. static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
  140. {
  141. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  142. int status;
  143. ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
  144. iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
  145. /* asking the HV for a blit will kick the FIFO */
  146. status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
  147. if (status)
  148. dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
  149. __func__, status);
  150. priv->fifo_ptr = priv->fifo_base;
  151. }
  152. static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
  153. {
  154. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  155. int status;
  156. mutex_lock(&ps3_gpu_mutex);
  157. iowrite32be(FIFO_BASE + FIFO_OFFSET + (priv->fifo_ptr - priv->fifo_base)
  158. * sizeof(u32), priv->ctrl + CTRL_PUT);
  159. /* asking the HV for a blit will kick the FIFO */
  160. status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
  161. if (status)
  162. dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
  163. __func__, status);
  164. if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
  165. FIFO_SIZE - 1024) {
  166. dev_dbg(&dev->core, "FIFO full, rewinding\n");
  167. ps3vram_wait_ring(dev, 200);
  168. ps3vram_rewind_ring(dev);
  169. }
  170. mutex_unlock(&ps3_gpu_mutex);
  171. }
  172. static void ps3vram_bind(struct ps3_system_bus_device *dev)
  173. {
  174. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  175. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
  176. ps3vram_out_ring(priv, 0x31337303);
  177. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
  178. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  179. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  180. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  181. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
  182. ps3vram_out_ring(priv, 0x3137c0de);
  183. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
  184. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  185. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  186. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  187. ps3vram_fire_ring(dev);
  188. }
  189. static int ps3vram_upload(struct ps3_system_bus_device *dev,
  190. unsigned int src_offset, unsigned int dst_offset,
  191. int len, int count)
  192. {
  193. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  194. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  195. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  196. ps3vram_out_ring(priv, XDR_IOIF + src_offset);
  197. ps3vram_out_ring(priv, dst_offset);
  198. ps3vram_out_ring(priv, len);
  199. ps3vram_out_ring(priv, len);
  200. ps3vram_out_ring(priv, len);
  201. ps3vram_out_ring(priv, count);
  202. ps3vram_out_ring(priv, (1 << 8) | 1);
  203. ps3vram_out_ring(priv, 0);
  204. ps3vram_notifier_reset(dev);
  205. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  206. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  207. ps3vram_out_ring(priv, 0);
  208. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
  209. ps3vram_out_ring(priv, 0);
  210. ps3vram_fire_ring(dev);
  211. if (ps3vram_notifier_wait(dev, 200) < 0) {
  212. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  213. return -1;
  214. }
  215. return 0;
  216. }
  217. static int ps3vram_download(struct ps3_system_bus_device *dev,
  218. unsigned int src_offset, unsigned int dst_offset,
  219. int len, int count)
  220. {
  221. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  222. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  223. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  224. ps3vram_out_ring(priv, src_offset);
  225. ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
  226. ps3vram_out_ring(priv, len);
  227. ps3vram_out_ring(priv, len);
  228. ps3vram_out_ring(priv, len);
  229. ps3vram_out_ring(priv, count);
  230. ps3vram_out_ring(priv, (1 << 8) | 1);
  231. ps3vram_out_ring(priv, 0);
  232. ps3vram_notifier_reset(dev);
  233. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  234. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  235. ps3vram_out_ring(priv, 0);
  236. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
  237. ps3vram_out_ring(priv, 0);
  238. ps3vram_fire_ring(dev);
  239. if (ps3vram_notifier_wait(dev, 200) < 0) {
  240. dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
  241. return -1;
  242. }
  243. return 0;
  244. }
  245. static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
  246. {
  247. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  248. struct ps3vram_cache *cache = &priv->cache;
  249. if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
  250. return;
  251. dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
  252. cache->tags[entry].address);
  253. if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
  254. cache->tags[entry].address, DMA_PAGE_SIZE,
  255. cache->page_size / DMA_PAGE_SIZE) < 0) {
  256. dev_err(&dev->core,
  257. "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
  258. entry * cache->page_size, cache->tags[entry].address,
  259. cache->page_size);
  260. }
  261. cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
  262. }
  263. static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
  264. unsigned int address)
  265. {
  266. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  267. struct ps3vram_cache *cache = &priv->cache;
  268. dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
  269. if (ps3vram_download(dev, address,
  270. CACHE_OFFSET + entry * cache->page_size,
  271. DMA_PAGE_SIZE,
  272. cache->page_size / DMA_PAGE_SIZE) < 0) {
  273. dev_err(&dev->core,
  274. "Failed to download from 0x%x to 0x%x size 0x%x\n",
  275. address, entry * cache->page_size, cache->page_size);
  276. }
  277. cache->tags[entry].address = address;
  278. cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
  279. }
  280. static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
  281. {
  282. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  283. struct ps3vram_cache *cache = &priv->cache;
  284. int i;
  285. dev_dbg(&dev->core, "FLUSH\n");
  286. for (i = 0; i < cache->page_count; i++) {
  287. ps3vram_cache_evict(dev, i);
  288. cache->tags[i].flags = 0;
  289. }
  290. }
  291. static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
  292. loff_t address)
  293. {
  294. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  295. struct ps3vram_cache *cache = &priv->cache;
  296. unsigned int base;
  297. unsigned int offset;
  298. int i;
  299. static int counter;
  300. offset = (unsigned int) (address & (cache->page_size - 1));
  301. base = (unsigned int) (address - offset);
  302. /* fully associative check */
  303. for (i = 0; i < cache->page_count; i++) {
  304. if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
  305. cache->tags[i].address == base) {
  306. cache->hit++;
  307. dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
  308. cache->tags[i].address);
  309. return i;
  310. }
  311. }
  312. /* choose a random entry */
  313. i = (jiffies + (counter++)) % cache->page_count;
  314. dev_dbg(&dev->core, "Using entry %d\n", i);
  315. ps3vram_cache_evict(dev, i);
  316. ps3vram_cache_load(dev, i, base);
  317. cache->miss++;
  318. return i;
  319. }
  320. static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
  321. {
  322. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  323. priv->cache.page_count = CACHE_PAGE_COUNT;
  324. priv->cache.page_size = CACHE_PAGE_SIZE;
  325. priv->cache.tags = kcalloc(CACHE_PAGE_COUNT,
  326. sizeof(struct ps3vram_tag),
  327. GFP_KERNEL);
  328. if (!priv->cache.tags)
  329. return -ENOMEM;
  330. dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
  331. CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
  332. return 0;
  333. }
  334. static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
  335. {
  336. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  337. ps3vram_cache_flush(dev);
  338. kfree(priv->cache.tags);
  339. }
  340. static blk_status_t ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
  341. size_t len, size_t *retlen, u_char *buf)
  342. {
  343. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  344. unsigned int cached, count;
  345. dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
  346. (unsigned int)from, len);
  347. if (from >= priv->size)
  348. return BLK_STS_IOERR;
  349. if (len > priv->size - from)
  350. len = priv->size - from;
  351. /* Copy from vram to buf */
  352. count = len;
  353. while (count) {
  354. unsigned int offset, avail;
  355. unsigned int entry;
  356. offset = (unsigned int) (from & (priv->cache.page_size - 1));
  357. avail = priv->cache.page_size - offset;
  358. entry = ps3vram_cache_match(dev, from);
  359. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  360. dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
  361. "avail=%08x count=%08x\n", __func__,
  362. (unsigned int)from, cached, offset, avail, count);
  363. if (avail > count)
  364. avail = count;
  365. memcpy(buf, priv->xdr_buf + cached, avail);
  366. buf += avail;
  367. count -= avail;
  368. from += avail;
  369. }
  370. *retlen = len;
  371. return 0;
  372. }
  373. static blk_status_t ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
  374. size_t len, size_t *retlen, const u_char *buf)
  375. {
  376. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  377. unsigned int cached, count;
  378. if (to >= priv->size)
  379. return BLK_STS_IOERR;
  380. if (len > priv->size - to)
  381. len = priv->size - to;
  382. /* Copy from buf to vram */
  383. count = len;
  384. while (count) {
  385. unsigned int offset, avail;
  386. unsigned int entry;
  387. offset = (unsigned int) (to & (priv->cache.page_size - 1));
  388. avail = priv->cache.page_size - offset;
  389. entry = ps3vram_cache_match(dev, to);
  390. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  391. dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
  392. "avail=%08x count=%08x\n", __func__, (unsigned int)to,
  393. cached, offset, avail, count);
  394. if (avail > count)
  395. avail = count;
  396. memcpy(priv->xdr_buf + cached, buf, avail);
  397. priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
  398. buf += avail;
  399. count -= avail;
  400. to += avail;
  401. }
  402. *retlen = len;
  403. return 0;
  404. }
  405. static int ps3vram_proc_show(struct seq_file *m, void *v)
  406. {
  407. struct ps3vram_priv *priv = m->private;
  408. seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
  409. return 0;
  410. }
  411. static void ps3vram_proc_init(struct ps3_system_bus_device *dev)
  412. {
  413. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  414. struct proc_dir_entry *pde;
  415. pde = proc_create_single_data(DEVICE_NAME, 0444, NULL,
  416. ps3vram_proc_show, priv);
  417. if (!pde)
  418. dev_warn(&dev->core, "failed to create /proc entry\n");
  419. }
  420. static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev,
  421. struct bio *bio)
  422. {
  423. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  424. int write = bio_data_dir(bio) == WRITE;
  425. const char *op = write ? "write" : "read";
  426. loff_t offset = bio->bi_iter.bi_sector << 9;
  427. blk_status_t error = 0;
  428. struct bio_vec bvec;
  429. struct bvec_iter iter;
  430. struct bio *next;
  431. bio_for_each_segment(bvec, bio, iter) {
  432. /* PS3 is ppc64, so we don't handle highmem */
  433. char *ptr = page_address(bvec.bv_page) + bvec.bv_offset;
  434. size_t len = bvec.bv_len, retlen;
  435. dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
  436. len, offset);
  437. if (write)
  438. error = ps3vram_write(dev, offset, len, &retlen, ptr);
  439. else
  440. error = ps3vram_read(dev, offset, len, &retlen, ptr);
  441. if (error) {
  442. dev_err(&dev->core, "%s failed\n", op);
  443. goto out;
  444. }
  445. if (retlen != len) {
  446. dev_err(&dev->core, "Short %s\n", op);
  447. error = BLK_STS_IOERR;
  448. goto out;
  449. }
  450. offset += len;
  451. }
  452. dev_dbg(&dev->core, "%s completed\n", op);
  453. out:
  454. spin_lock_irq(&priv->lock);
  455. bio_list_pop(&priv->list);
  456. next = bio_list_peek(&priv->list);
  457. spin_unlock_irq(&priv->lock);
  458. bio->bi_status = error;
  459. bio_endio(bio);
  460. return next;
  461. }
  462. static blk_qc_t ps3vram_make_request(struct request_queue *q, struct bio *bio)
  463. {
  464. struct ps3_system_bus_device *dev = q->queuedata;
  465. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  466. int busy;
  467. dev_dbg(&dev->core, "%s\n", __func__);
  468. blk_queue_split(q, &bio);
  469. spin_lock_irq(&priv->lock);
  470. busy = !bio_list_empty(&priv->list);
  471. bio_list_add(&priv->list, bio);
  472. spin_unlock_irq(&priv->lock);
  473. if (busy)
  474. return BLK_QC_T_NONE;
  475. do {
  476. bio = ps3vram_do_bio(dev, bio);
  477. } while (bio);
  478. return BLK_QC_T_NONE;
  479. }
  480. static int ps3vram_probe(struct ps3_system_bus_device *dev)
  481. {
  482. struct ps3vram_priv *priv;
  483. int error, status;
  484. struct request_queue *queue;
  485. struct gendisk *gendisk;
  486. u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar,
  487. reports_size, xdr_lpar;
  488. char *rest;
  489. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  490. if (!priv) {
  491. error = -ENOMEM;
  492. goto fail;
  493. }
  494. spin_lock_init(&priv->lock);
  495. bio_list_init(&priv->list);
  496. ps3_system_bus_set_drvdata(dev, priv);
  497. /* Allocate XDR buffer (1MiB aligned) */
  498. priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
  499. get_order(XDR_BUF_SIZE));
  500. if (priv->xdr_buf == NULL) {
  501. dev_err(&dev->core, "Could not allocate XDR buffer\n");
  502. error = -ENOMEM;
  503. goto fail_free_priv;
  504. }
  505. /* Put FIFO at begginning of XDR buffer */
  506. priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
  507. priv->fifo_ptr = priv->fifo_base;
  508. /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
  509. if (ps3_open_hv_device(dev)) {
  510. dev_err(&dev->core, "ps3_open_hv_device failed\n");
  511. error = -EAGAIN;
  512. goto out_free_xdr_buf;
  513. }
  514. /* Request memory */
  515. status = -1;
  516. ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
  517. if (!ddr_size) {
  518. dev_err(&dev->core, "Specified size is too small\n");
  519. error = -EINVAL;
  520. goto out_close_gpu;
  521. }
  522. while (ddr_size > 0) {
  523. status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
  524. &priv->memory_handle,
  525. &ddr_lpar);
  526. if (!status)
  527. break;
  528. ddr_size -= 1024*1024;
  529. }
  530. if (status) {
  531. dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
  532. status);
  533. error = -ENOMEM;
  534. goto out_close_gpu;
  535. }
  536. /* Request context */
  537. status = lv1_gpu_context_allocate(priv->memory_handle, 0,
  538. &priv->context_handle, &ctrl_lpar,
  539. &info_lpar, &reports_lpar,
  540. &reports_size);
  541. if (status) {
  542. dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
  543. status);
  544. error = -ENOMEM;
  545. goto out_free_memory;
  546. }
  547. /* Map XDR buffer to RSX */
  548. xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf));
  549. status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  550. xdr_lpar, XDR_BUF_SIZE,
  551. CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
  552. CBE_IOPTE_M);
  553. if (status) {
  554. dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
  555. status);
  556. error = -ENOMEM;
  557. goto out_free_context;
  558. }
  559. priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
  560. if (!priv->ctrl) {
  561. dev_err(&dev->core, "ioremap CTRL failed\n");
  562. error = -ENOMEM;
  563. goto out_unmap_context;
  564. }
  565. priv->reports = ioremap(reports_lpar, reports_size);
  566. if (!priv->reports) {
  567. dev_err(&dev->core, "ioremap REPORTS failed\n");
  568. error = -ENOMEM;
  569. goto out_unmap_ctrl;
  570. }
  571. mutex_lock(&ps3_gpu_mutex);
  572. ps3vram_init_ring(dev);
  573. mutex_unlock(&ps3_gpu_mutex);
  574. priv->size = ddr_size;
  575. ps3vram_bind(dev);
  576. mutex_lock(&ps3_gpu_mutex);
  577. error = ps3vram_wait_ring(dev, 100);
  578. mutex_unlock(&ps3_gpu_mutex);
  579. if (error < 0) {
  580. dev_err(&dev->core, "Failed to initialize channels\n");
  581. error = -ETIMEDOUT;
  582. goto out_unmap_reports;
  583. }
  584. error = ps3vram_cache_init(dev);
  585. if (error < 0) {
  586. goto out_unmap_reports;
  587. }
  588. ps3vram_proc_init(dev);
  589. queue = blk_alloc_queue(GFP_KERNEL);
  590. if (!queue) {
  591. dev_err(&dev->core, "blk_alloc_queue failed\n");
  592. error = -ENOMEM;
  593. goto out_cache_cleanup;
  594. }
  595. priv->queue = queue;
  596. queue->queuedata = dev;
  597. blk_queue_make_request(queue, ps3vram_make_request);
  598. blk_queue_max_segments(queue, BLK_MAX_SEGMENTS);
  599. blk_queue_max_segment_size(queue, BLK_MAX_SEGMENT_SIZE);
  600. blk_queue_max_hw_sectors(queue, BLK_SAFE_MAX_SECTORS);
  601. gendisk = alloc_disk(1);
  602. if (!gendisk) {
  603. dev_err(&dev->core, "alloc_disk failed\n");
  604. error = -ENOMEM;
  605. goto fail_cleanup_queue;
  606. }
  607. priv->gendisk = gendisk;
  608. gendisk->major = ps3vram_major;
  609. gendisk->first_minor = 0;
  610. gendisk->fops = &ps3vram_fops;
  611. gendisk->queue = queue;
  612. gendisk->private_data = dev;
  613. strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
  614. set_capacity(gendisk, priv->size >> 9);
  615. dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n",
  616. gendisk->disk_name, get_capacity(gendisk) >> 11);
  617. device_add_disk(&dev->core, gendisk, NULL);
  618. return 0;
  619. fail_cleanup_queue:
  620. blk_cleanup_queue(queue);
  621. out_cache_cleanup:
  622. remove_proc_entry(DEVICE_NAME, NULL);
  623. ps3vram_cache_cleanup(dev);
  624. out_unmap_reports:
  625. iounmap(priv->reports);
  626. out_unmap_ctrl:
  627. iounmap(priv->ctrl);
  628. out_unmap_context:
  629. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar,
  630. XDR_BUF_SIZE, CBE_IOPTE_M);
  631. out_free_context:
  632. lv1_gpu_context_free(priv->context_handle);
  633. out_free_memory:
  634. lv1_gpu_memory_free(priv->memory_handle);
  635. out_close_gpu:
  636. ps3_close_hv_device(dev);
  637. out_free_xdr_buf:
  638. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  639. fail_free_priv:
  640. kfree(priv);
  641. ps3_system_bus_set_drvdata(dev, NULL);
  642. fail:
  643. return error;
  644. }
  645. static int ps3vram_remove(struct ps3_system_bus_device *dev)
  646. {
  647. struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
  648. del_gendisk(priv->gendisk);
  649. put_disk(priv->gendisk);
  650. blk_cleanup_queue(priv->queue);
  651. remove_proc_entry(DEVICE_NAME, NULL);
  652. ps3vram_cache_cleanup(dev);
  653. iounmap(priv->reports);
  654. iounmap(priv->ctrl);
  655. lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  656. ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
  657. XDR_BUF_SIZE, CBE_IOPTE_M);
  658. lv1_gpu_context_free(priv->context_handle);
  659. lv1_gpu_memory_free(priv->memory_handle);
  660. ps3_close_hv_device(dev);
  661. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  662. kfree(priv);
  663. ps3_system_bus_set_drvdata(dev, NULL);
  664. return 0;
  665. }
  666. static struct ps3_system_bus_driver ps3vram = {
  667. .match_id = PS3_MATCH_ID_GPU,
  668. .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
  669. .core.name = DEVICE_NAME,
  670. .core.owner = THIS_MODULE,
  671. .probe = ps3vram_probe,
  672. .remove = ps3vram_remove,
  673. .shutdown = ps3vram_remove,
  674. };
  675. static int __init ps3vram_init(void)
  676. {
  677. int error;
  678. if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
  679. return -ENODEV;
  680. error = register_blkdev(0, DEVICE_NAME);
  681. if (error <= 0) {
  682. pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
  683. return error;
  684. }
  685. ps3vram_major = error;
  686. pr_info("%s: registered block device major %d\n", DEVICE_NAME,
  687. ps3vram_major);
  688. error = ps3_system_bus_driver_register(&ps3vram);
  689. if (error)
  690. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  691. return error;
  692. }
  693. static void __exit ps3vram_exit(void)
  694. {
  695. ps3_system_bus_driver_unregister(&ps3vram);
  696. unregister_blkdev(ps3vram_major, DEVICE_NAME);
  697. }
  698. module_init(ps3vram_init);
  699. module_exit(ps3vram_exit);
  700. MODULE_LICENSE("GPL");
  701. MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
  702. MODULE_AUTHOR("Sony Corporation");
  703. MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);