ccu-sun8i-a23.c 24 KB

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  1. /*
  2. * Copyright (c) 2016 Maxime Ripard. All rights reserved.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/clk-provider.h>
  14. #include <linux/of_address.h>
  15. #include "ccu_common.h"
  16. #include "ccu_reset.h"
  17. #include "ccu_div.h"
  18. #include "ccu_gate.h"
  19. #include "ccu_mp.h"
  20. #include "ccu_mult.h"
  21. #include "ccu_nk.h"
  22. #include "ccu_nkm.h"
  23. #include "ccu_nkmp.h"
  24. #include "ccu_nm.h"
  25. #include "ccu_phase.h"
  26. #include "ccu_sdm.h"
  27. #include "ccu-sun8i-a23-a33.h"
  28. static struct ccu_nkmp pll_cpux_clk = {
  29. .enable = BIT(31),
  30. .lock = BIT(28),
  31. .n = _SUNXI_CCU_MULT(8, 5),
  32. .k = _SUNXI_CCU_MULT(4, 2),
  33. .m = _SUNXI_CCU_DIV(0, 2),
  34. .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
  35. .common = {
  36. .reg = 0x000,
  37. .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
  38. &ccu_nkmp_ops,
  39. 0),
  40. },
  41. };
  42. /*
  43. * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
  44. * the base (2x, 4x and 8x), and one variable divider (the one true
  45. * pll audio).
  46. *
  47. * With sigma-delta modulation for fractional-N on the audio PLL,
  48. * we have to use specific dividers. This means the variable divider
  49. * can no longer be used, as the audio codec requests the exact clock
  50. * rates we support through this mechanism. So we now hard code the
  51. * variable divider to 1. This means the clock rates will no longer
  52. * match the clock names.
  53. */
  54. #define SUN8I_A23_PLL_AUDIO_REG 0x008
  55. static struct ccu_sdm_setting pll_audio_sdm_table[] = {
  56. { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
  57. { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
  58. };
  59. static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
  60. "osc24M", 0x008,
  61. 8, 7, /* N */
  62. 0, 5, /* M */
  63. pll_audio_sdm_table, BIT(24),
  64. 0x284, BIT(31),
  65. BIT(31), /* gate */
  66. BIT(28), /* lock */
  67. CLK_SET_RATE_UNGATE);
  68. static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
  69. "osc24M", 0x010,
  70. 8, 7, /* N */
  71. 0, 4, /* M */
  72. BIT(24), /* frac enable */
  73. BIT(25), /* frac select */
  74. 270000000, /* frac rate 0 */
  75. 297000000, /* frac rate 1 */
  76. BIT(31), /* gate */
  77. BIT(28), /* lock */
  78. CLK_SET_RATE_UNGATE);
  79. static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
  80. "osc24M", 0x018,
  81. 8, 7, /* N */
  82. 0, 4, /* M */
  83. BIT(24), /* frac enable */
  84. BIT(25), /* frac select */
  85. 270000000, /* frac rate 0 */
  86. 297000000, /* frac rate 1 */
  87. BIT(31), /* gate */
  88. BIT(28), /* lock */
  89. CLK_SET_RATE_UNGATE);
  90. static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
  91. "osc24M", 0x020,
  92. 8, 5, /* N */
  93. 4, 2, /* K */
  94. 0, 2, /* M */
  95. BIT(31), /* gate */
  96. BIT(28), /* lock */
  97. 0);
  98. static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
  99. "osc24M", 0x028,
  100. 8, 5, /* N */
  101. 4, 2, /* K */
  102. BIT(31), /* gate */
  103. BIT(28), /* lock */
  104. 2, /* post-div */
  105. CLK_SET_RATE_UNGATE);
  106. static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
  107. "osc24M", 0x038,
  108. 8, 7, /* N */
  109. 0, 4, /* M */
  110. BIT(24), /* frac enable */
  111. BIT(25), /* frac select */
  112. 270000000, /* frac rate 0 */
  113. 297000000, /* frac rate 1 */
  114. BIT(31), /* gate */
  115. BIT(28), /* lock */
  116. CLK_SET_RATE_UNGATE);
  117. /*
  118. * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
  119. *
  120. * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
  121. * integer / fractional clock with switchable multipliers and dividers.
  122. * This is not supported here. We hardcode the PLL to MIPI mode.
  123. */
  124. #define SUN8I_A23_PLL_MIPI_REG 0x040
  125. static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
  126. "pll-video", 0x040,
  127. 8, 4, /* N */
  128. 4, 2, /* K */
  129. 0, 4, /* M */
  130. BIT(31) | BIT(23) | BIT(22), /* gate */
  131. BIT(28), /* lock */
  132. CLK_SET_RATE_UNGATE);
  133. static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
  134. "osc24M", 0x044,
  135. 8, 7, /* N */
  136. 0, 4, /* M */
  137. BIT(24), /* frac enable */
  138. BIT(25), /* frac select */
  139. 270000000, /* frac rate 0 */
  140. 297000000, /* frac rate 1 */
  141. BIT(31), /* gate */
  142. BIT(28), /* lock */
  143. CLK_SET_RATE_UNGATE);
  144. static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
  145. "osc24M", 0x048,
  146. 8, 7, /* N */
  147. 0, 4, /* M */
  148. BIT(24), /* frac enable */
  149. BIT(25), /* frac select */
  150. 270000000, /* frac rate 0 */
  151. 297000000, /* frac rate 1 */
  152. BIT(31), /* gate */
  153. BIT(28), /* lock */
  154. CLK_SET_RATE_UNGATE);
  155. static const char * const cpux_parents[] = { "osc32k", "osc24M",
  156. "pll-cpux" , "pll-cpux" };
  157. static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
  158. 0x050, 16, 2, CLK_IS_CRITICAL);
  159. static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
  160. static const char * const ahb1_parents[] = { "osc32k", "osc24M",
  161. "axi" , "pll-periph" };
  162. static const struct ccu_mux_var_prediv ahb1_predivs[] = {
  163. { .index = 3, .shift = 6, .width = 2 },
  164. };
  165. static struct ccu_div ahb1_clk = {
  166. .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
  167. .mux = {
  168. .shift = 12,
  169. .width = 2,
  170. .var_predivs = ahb1_predivs,
  171. .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
  172. },
  173. .common = {
  174. .reg = 0x054,
  175. .features = CCU_FEATURE_VARIABLE_PREDIV,
  176. .hw.init = CLK_HW_INIT_PARENTS("ahb1",
  177. ahb1_parents,
  178. &ccu_div_ops,
  179. 0),
  180. },
  181. };
  182. static struct clk_div_table apb1_div_table[] = {
  183. { .val = 0, .div = 2 },
  184. { .val = 1, .div = 2 },
  185. { .val = 2, .div = 4 },
  186. { .val = 3, .div = 8 },
  187. { /* Sentinel */ },
  188. };
  189. static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
  190. 0x054, 8, 2, apb1_div_table, 0);
  191. static const char * const apb2_parents[] = { "osc32k", "osc24M",
  192. "pll-periph" , "pll-periph" };
  193. static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
  194. 0, 5, /* M */
  195. 16, 2, /* P */
  196. 24, 2, /* mux */
  197. 0);
  198. static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
  199. 0x060, BIT(1), 0);
  200. static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
  201. 0x060, BIT(6), 0);
  202. static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
  203. 0x060, BIT(8), 0);
  204. static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
  205. 0x060, BIT(9), 0);
  206. static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
  207. 0x060, BIT(10), 0);
  208. static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
  209. 0x060, BIT(13), 0);
  210. static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
  211. 0x060, BIT(14), 0);
  212. static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
  213. 0x060, BIT(19), 0);
  214. static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
  215. 0x060, BIT(20), 0);
  216. static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
  217. 0x060, BIT(21), 0);
  218. static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
  219. 0x060, BIT(24), 0);
  220. static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
  221. 0x060, BIT(26), 0);
  222. static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
  223. 0x060, BIT(29), 0);
  224. static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
  225. 0x064, BIT(0), 0);
  226. static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
  227. 0x064, BIT(4), 0);
  228. static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
  229. 0x064, BIT(8), 0);
  230. static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
  231. 0x064, BIT(12), 0);
  232. static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
  233. 0x064, BIT(14), 0);
  234. static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
  235. 0x064, BIT(20), 0);
  236. static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
  237. 0x064, BIT(21), 0);
  238. static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
  239. 0x064, BIT(22), 0);
  240. static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
  241. 0x064, BIT(25), 0);
  242. static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
  243. 0x068, BIT(0), 0);
  244. static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
  245. 0x068, BIT(5), 0);
  246. static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
  247. 0x068, BIT(12), 0);
  248. static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
  249. 0x068, BIT(13), 0);
  250. static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
  251. 0x06c, BIT(0), 0);
  252. static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
  253. 0x06c, BIT(1), 0);
  254. static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
  255. 0x06c, BIT(2), 0);
  256. static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
  257. 0x06c, BIT(16), 0);
  258. static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
  259. 0x06c, BIT(17), 0);
  260. static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
  261. 0x06c, BIT(18), 0);
  262. static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
  263. 0x06c, BIT(19), 0);
  264. static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
  265. 0x06c, BIT(20), 0);
  266. static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
  267. static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
  268. 0, 4, /* M */
  269. 16, 2, /* P */
  270. 24, 2, /* mux */
  271. BIT(31), /* gate */
  272. 0);
  273. static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
  274. 0, 4, /* M */
  275. 16, 2, /* P */
  276. 24, 2, /* mux */
  277. BIT(31), /* gate */
  278. 0);
  279. static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
  280. 0x088, 20, 3, 0);
  281. static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
  282. 0x088, 8, 3, 0);
  283. static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
  284. 0, 4, /* M */
  285. 16, 2, /* P */
  286. 24, 2, /* mux */
  287. BIT(31), /* gate */
  288. 0);
  289. static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
  290. 0x08c, 20, 3, 0);
  291. static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
  292. 0x08c, 8, 3, 0);
  293. static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
  294. 0, 4, /* M */
  295. 16, 2, /* P */
  296. 24, 2, /* mux */
  297. BIT(31), /* gate */
  298. 0);
  299. static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
  300. 0x090, 20, 3, 0);
  301. static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
  302. 0x090, 8, 3, 0);
  303. static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
  304. 0, 4, /* M */
  305. 16, 2, /* P */
  306. 24, 2, /* mux */
  307. BIT(31), /* gate */
  308. 0);
  309. static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
  310. 0, 4, /* M */
  311. 16, 2, /* P */
  312. 24, 2, /* mux */
  313. BIT(31), /* gate */
  314. 0);
  315. static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
  316. "pll-audio-2x", "pll-audio" };
  317. static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
  318. 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
  319. static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
  320. 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
  321. /* TODO: the parent for most of the USB clocks is not known */
  322. static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
  323. 0x0cc, BIT(8), 0);
  324. static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
  325. 0x0cc, BIT(9), 0);
  326. static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
  327. 0x0cc, BIT(10), 0);
  328. static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
  329. 0x0cc, BIT(11), 0);
  330. static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
  331. 0x0cc, BIT(16), 0);
  332. static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
  333. 0x100, BIT(0), 0);
  334. static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
  335. 0x100, BIT(1), 0);
  336. static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr",
  337. 0x100, BIT(16), 0);
  338. static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
  339. 0x100, BIT(24), 0);
  340. static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
  341. 0x100, BIT(26), 0);
  342. static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
  343. "pll-gpu", "pll-de" };
  344. static const u8 de_table[] = { 0, 2, 3, 5 };
  345. static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
  346. de_parents, de_table,
  347. 0x104, 0, 4, 24, 3, BIT(31), 0);
  348. static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
  349. de_parents, de_table,
  350. 0x10c, 0, 4, 24, 3, BIT(31), 0);
  351. static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
  352. "pll-mipi" };
  353. static const u8 lcd_ch0_table[] = { 0, 2, 4 };
  354. static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
  355. lcd_ch0_parents, lcd_ch0_table,
  356. 0x118, 24, 3, BIT(31),
  357. CLK_SET_RATE_PARENT);
  358. static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
  359. static const u8 lcd_ch1_table[] = { 0, 2 };
  360. static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
  361. lcd_ch1_parents, lcd_ch1_table,
  362. 0x12c, 0, 4, 24, 2, BIT(31), 0);
  363. static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
  364. "pll-mipi", "pll-ve" };
  365. static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
  366. static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
  367. csi_sclk_parents, csi_sclk_table,
  368. 0x134, 16, 4, 24, 3, BIT(31), 0);
  369. static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
  370. "osc24M" };
  371. static const u8 csi_mclk_table[] = { 0, 3, 5 };
  372. static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
  373. csi_mclk_parents, csi_mclk_table,
  374. 0x134, 0, 5, 8, 3, BIT(15), 0);
  375. static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
  376. 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
  377. static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
  378. 0x140, BIT(31), CLK_SET_RATE_PARENT);
  379. static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
  380. 0x144, BIT(31), 0);
  381. static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
  382. "pll-ddr" };
  383. static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
  384. 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
  385. static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
  386. static const u8 dsi_sclk_table[] = { 0, 2 };
  387. static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
  388. dsi_sclk_parents, dsi_sclk_table,
  389. 0x168, 16, 4, 24, 2, BIT(31), 0);
  390. static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
  391. static const u8 dsi_dphy_table[] = { 0, 2 };
  392. static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
  393. dsi_dphy_parents, dsi_dphy_table,
  394. 0x168, 0, 4, 8, 2, BIT(15), 0);
  395. static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
  396. de_parents, de_table,
  397. 0x180, 0, 4, 24, 3, BIT(31), 0);
  398. static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
  399. 0x1a0, 0, 3, BIT(31), 0);
  400. static const char * const ats_parents[] = { "osc24M", "pll-periph" };
  401. static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
  402. 0x1b0, 0, 3, 24, 2, BIT(31), 0);
  403. static struct ccu_common *sun8i_a23_ccu_clks[] = {
  404. &pll_cpux_clk.common,
  405. &pll_audio_base_clk.common,
  406. &pll_video_clk.common,
  407. &pll_ve_clk.common,
  408. &pll_ddr_clk.common,
  409. &pll_periph_clk.common,
  410. &pll_gpu_clk.common,
  411. &pll_mipi_clk.common,
  412. &pll_hsic_clk.common,
  413. &pll_de_clk.common,
  414. &cpux_clk.common,
  415. &axi_clk.common,
  416. &ahb1_clk.common,
  417. &apb1_clk.common,
  418. &apb2_clk.common,
  419. &bus_mipi_dsi_clk.common,
  420. &bus_dma_clk.common,
  421. &bus_mmc0_clk.common,
  422. &bus_mmc1_clk.common,
  423. &bus_mmc2_clk.common,
  424. &bus_nand_clk.common,
  425. &bus_dram_clk.common,
  426. &bus_hstimer_clk.common,
  427. &bus_spi0_clk.common,
  428. &bus_spi1_clk.common,
  429. &bus_otg_clk.common,
  430. &bus_ehci_clk.common,
  431. &bus_ohci_clk.common,
  432. &bus_ve_clk.common,
  433. &bus_lcd_clk.common,
  434. &bus_csi_clk.common,
  435. &bus_de_fe_clk.common,
  436. &bus_de_be_clk.common,
  437. &bus_gpu_clk.common,
  438. &bus_msgbox_clk.common,
  439. &bus_spinlock_clk.common,
  440. &bus_drc_clk.common,
  441. &bus_codec_clk.common,
  442. &bus_pio_clk.common,
  443. &bus_i2s0_clk.common,
  444. &bus_i2s1_clk.common,
  445. &bus_i2c0_clk.common,
  446. &bus_i2c1_clk.common,
  447. &bus_i2c2_clk.common,
  448. &bus_uart0_clk.common,
  449. &bus_uart1_clk.common,
  450. &bus_uart2_clk.common,
  451. &bus_uart3_clk.common,
  452. &bus_uart4_clk.common,
  453. &nand_clk.common,
  454. &mmc0_clk.common,
  455. &mmc0_sample_clk.common,
  456. &mmc0_output_clk.common,
  457. &mmc1_clk.common,
  458. &mmc1_sample_clk.common,
  459. &mmc1_output_clk.common,
  460. &mmc2_clk.common,
  461. &mmc2_sample_clk.common,
  462. &mmc2_output_clk.common,
  463. &spi0_clk.common,
  464. &spi1_clk.common,
  465. &i2s0_clk.common,
  466. &i2s1_clk.common,
  467. &usb_phy0_clk.common,
  468. &usb_phy1_clk.common,
  469. &usb_hsic_clk.common,
  470. &usb_hsic_12M_clk.common,
  471. &usb_ohci_clk.common,
  472. &dram_ve_clk.common,
  473. &dram_csi_clk.common,
  474. &dram_drc_clk.common,
  475. &dram_de_fe_clk.common,
  476. &dram_de_be_clk.common,
  477. &de_be_clk.common,
  478. &de_fe_clk.common,
  479. &lcd_ch0_clk.common,
  480. &lcd_ch1_clk.common,
  481. &csi_sclk_clk.common,
  482. &csi_mclk_clk.common,
  483. &ve_clk.common,
  484. &ac_dig_clk.common,
  485. &avs_clk.common,
  486. &mbus_clk.common,
  487. &dsi_sclk_clk.common,
  488. &dsi_dphy_clk.common,
  489. &drc_clk.common,
  490. &gpu_clk.common,
  491. &ats_clk.common,
  492. };
  493. /* We hardcode the divider to 1 for now */
  494. static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
  495. "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
  496. static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
  497. "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
  498. static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
  499. "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
  500. static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
  501. "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
  502. static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
  503. "pll-periph", 1, 2, 0);
  504. static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
  505. "pll-video", 1, 2, 0);
  506. static struct clk_hw_onecell_data sun8i_a23_hw_clks = {
  507. .hws = {
  508. [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
  509. [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
  510. [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
  511. [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
  512. [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
  513. [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
  514. [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
  515. [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
  516. [CLK_PLL_VE] = &pll_ve_clk.common.hw,
  517. [CLK_PLL_DDR0] = &pll_ddr_clk.common.hw,
  518. [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
  519. [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
  520. [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
  521. [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
  522. [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
  523. [CLK_PLL_DE] = &pll_de_clk.common.hw,
  524. [CLK_CPUX] = &cpux_clk.common.hw,
  525. [CLK_AXI] = &axi_clk.common.hw,
  526. [CLK_AHB1] = &ahb1_clk.common.hw,
  527. [CLK_APB1] = &apb1_clk.common.hw,
  528. [CLK_APB2] = &apb2_clk.common.hw,
  529. [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
  530. [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
  531. [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
  532. [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
  533. [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
  534. [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
  535. [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
  536. [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
  537. [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
  538. [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
  539. [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
  540. [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
  541. [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
  542. [CLK_BUS_VE] = &bus_ve_clk.common.hw,
  543. [CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
  544. [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
  545. [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
  546. [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
  547. [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
  548. [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
  549. [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
  550. [CLK_BUS_DRC] = &bus_drc_clk.common.hw,
  551. [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
  552. [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
  553. [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
  554. [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
  555. [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
  556. [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
  557. [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
  558. [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
  559. [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
  560. [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
  561. [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
  562. [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
  563. [CLK_NAND] = &nand_clk.common.hw,
  564. [CLK_MMC0] = &mmc0_clk.common.hw,
  565. [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
  566. [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
  567. [CLK_MMC1] = &mmc1_clk.common.hw,
  568. [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
  569. [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
  570. [CLK_MMC2] = &mmc2_clk.common.hw,
  571. [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
  572. [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
  573. [CLK_SPI0] = &spi0_clk.common.hw,
  574. [CLK_SPI1] = &spi1_clk.common.hw,
  575. [CLK_I2S0] = &i2s0_clk.common.hw,
  576. [CLK_I2S1] = &i2s1_clk.common.hw,
  577. [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
  578. [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
  579. [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
  580. [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw,
  581. [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
  582. [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
  583. [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
  584. [CLK_DRAM_DRC] = &dram_drc_clk.common.hw,
  585. [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
  586. [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
  587. [CLK_DE_BE] = &de_be_clk.common.hw,
  588. [CLK_DE_FE] = &de_fe_clk.common.hw,
  589. [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw,
  590. [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw,
  591. [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
  592. [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
  593. [CLK_VE] = &ve_clk.common.hw,
  594. [CLK_AC_DIG] = &ac_dig_clk.common.hw,
  595. [CLK_AVS] = &avs_clk.common.hw,
  596. [CLK_MBUS] = &mbus_clk.common.hw,
  597. [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw,
  598. [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
  599. [CLK_DRC] = &drc_clk.common.hw,
  600. [CLK_GPU] = &gpu_clk.common.hw,
  601. [CLK_ATS] = &ats_clk.common.hw,
  602. },
  603. .num = CLK_NUMBER,
  604. };
  605. static struct ccu_reset_map sun8i_a23_ccu_resets[] = {
  606. [RST_USB_PHY0] = { 0x0cc, BIT(0) },
  607. [RST_USB_PHY1] = { 0x0cc, BIT(1) },
  608. [RST_USB_HSIC] = { 0x0cc, BIT(2) },
  609. [RST_MBUS] = { 0x0fc, BIT(31) },
  610. [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
  611. [RST_BUS_DMA] = { 0x2c0, BIT(6) },
  612. [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
  613. [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
  614. [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
  615. [RST_BUS_NAND] = { 0x2c0, BIT(13) },
  616. [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
  617. [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
  618. [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
  619. [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
  620. [RST_BUS_OTG] = { 0x2c0, BIT(24) },
  621. [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
  622. [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
  623. [RST_BUS_VE] = { 0x2c4, BIT(0) },
  624. [RST_BUS_LCD] = { 0x2c4, BIT(4) },
  625. [RST_BUS_CSI] = { 0x2c4, BIT(8) },
  626. [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
  627. [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
  628. [RST_BUS_GPU] = { 0x2c4, BIT(20) },
  629. [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
  630. [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
  631. [RST_BUS_DRC] = { 0x2c4, BIT(25) },
  632. [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
  633. [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
  634. [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
  635. [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
  636. [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
  637. [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
  638. [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
  639. [RST_BUS_UART0] = { 0x2d8, BIT(16) },
  640. [RST_BUS_UART1] = { 0x2d8, BIT(17) },
  641. [RST_BUS_UART2] = { 0x2d8, BIT(18) },
  642. [RST_BUS_UART3] = { 0x2d8, BIT(19) },
  643. [RST_BUS_UART4] = { 0x2d8, BIT(20) },
  644. };
  645. static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = {
  646. .ccu_clks = sun8i_a23_ccu_clks,
  647. .num_ccu_clks = ARRAY_SIZE(sun8i_a23_ccu_clks),
  648. .hw_clks = &sun8i_a23_hw_clks,
  649. .resets = sun8i_a23_ccu_resets,
  650. .num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets),
  651. };
  652. static void __init sun8i_a23_ccu_setup(struct device_node *node)
  653. {
  654. void __iomem *reg;
  655. u32 val;
  656. reg = of_io_request_and_map(node, 0, of_node_full_name(node));
  657. if (IS_ERR(reg)) {
  658. pr_err("%pOF: Could not map the clock registers\n", node);
  659. return;
  660. }
  661. /* Force the PLL-Audio-1x divider to 1 */
  662. val = readl(reg + SUN8I_A23_PLL_AUDIO_REG);
  663. val &= ~GENMASK(19, 16);
  664. writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG);
  665. /* Force PLL-MIPI to MIPI mode */
  666. val = readl(reg + SUN8I_A23_PLL_MIPI_REG);
  667. val &= ~BIT(16);
  668. writel(val, reg + SUN8I_A23_PLL_MIPI_REG);
  669. sunxi_ccu_probe(node, reg, &sun8i_a23_ccu_desc);
  670. }
  671. CLK_OF_DECLARE(sun8i_a23_ccu, "allwinner,sun8i-a23-ccu",
  672. sun8i_a23_ccu_setup);