sdhci-xenon.h 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. /*
  2. * Copyright (C) 2016 Marvell, All Rights Reserved.
  3. *
  4. * Author: Hu Ziji <huziji@marvell.com>
  5. * Date: 2016-8-24
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. */
  11. #ifndef SDHCI_XENON_H_
  12. #define SDHCI_XENON_H_
  13. /* Register Offset of Xenon SDHC self-defined register */
  14. #define XENON_SYS_CFG_INFO 0x0104
  15. #define XENON_SLOT_TYPE_SDIO_SHIFT 24
  16. #define XENON_NR_SUPPORTED_SLOT_MASK 0x7
  17. #define XENON_SYS_OP_CTRL 0x0108
  18. #define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20)
  19. #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8
  20. #define XENON_SLOT_ENABLE_SHIFT 0
  21. #define XENON_SYS_EXT_OP_CTRL 0x010C
  22. #define XENON_MASK_CMD_CONFLICT_ERR BIT(8)
  23. #define XENON_SLOT_OP_STATUS_CTRL 0x0128
  24. #define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16
  25. #define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7
  26. #define XENON_TUN_CONSECUTIVE_TIMES 0x4
  27. #define XENON_TUNING_STEP_SHIFT 12
  28. #define XENON_TUNING_STEP_MASK 0xF
  29. #define XENON_TUNING_STEP_DIVIDER BIT(6)
  30. #define XENON_SLOT_EMMC_CTRL 0x0130
  31. #define XENON_ENABLE_RESP_STROBE BIT(25)
  32. #define XENON_ENABLE_DATA_STROBE BIT(24)
  33. #define XENON_SLOT_RETUNING_REQ_CTRL 0x0144
  34. /* retuning compatible */
  35. #define XENON_RETUNING_COMPATIBLE 0x1
  36. #define XENON_SLOT_EXT_PRESENT_STATE 0x014C
  37. #define XENON_DLL_LOCK_STATE 0x1
  38. #define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150
  39. /* Tuning Parameter */
  40. #define XENON_TMR_RETUN_NO_PRESENT 0xF
  41. #define XENON_DEF_TUNING_COUNT 0x9
  42. #define XENON_DEFAULT_SDCLK_FREQ 400000
  43. #define XENON_LOWEST_SDCLK_FREQ 100000
  44. /* Xenon specific Mode Select value */
  45. #define XENON_CTRL_HS200 0x5
  46. #define XENON_CTRL_HS400 0x6
  47. struct xenon_priv {
  48. unsigned char tuning_count;
  49. /* idx of SDHC */
  50. u8 sdhc_id;
  51. /*
  52. * eMMC/SD/SDIO require different register settings.
  53. * Xenon driver has to recognize card type
  54. * before mmc_host->card is not available.
  55. * This field records the card type during init.
  56. * It is updated in xenon_init_card().
  57. *
  58. * It is only valid during initialization after it is updated.
  59. * Do not access this variable in normal transfers after
  60. * initialization completes.
  61. */
  62. unsigned int init_card_type;
  63. /*
  64. * The bus_width, timing, and clock fields in below
  65. * record the current ios setting of Xenon SDHC.
  66. * Driver will adjust PHY setting if any change to
  67. * ios affects PHY timing.
  68. */
  69. unsigned char bus_width;
  70. unsigned char timing;
  71. unsigned int clock;
  72. struct clk *axi_clk;
  73. int phy_type;
  74. /*
  75. * Contains board-specific PHY parameters
  76. * passed from device tree.
  77. */
  78. void *phy_params;
  79. struct xenon_emmc_phy_regs *emmc_phy_regs;
  80. bool restore_needed;
  81. };
  82. int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
  83. int xenon_phy_parse_dt(struct device_node *np,
  84. struct sdhci_host *host);
  85. void xenon_soc_pad_ctrl(struct sdhci_host *host,
  86. unsigned char signal_voltage);
  87. #endif