pcie-designware-host.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Synopsys DesignWare PCIe host controller driver
  4. *
  5. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  6. * http://www.samsung.com
  7. *
  8. * Author: Jingoo Han <jg1.han@samsung.com>
  9. */
  10. #include <linux/irqchip/chained_irq.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_pci.h>
  14. #include <linux/pci_regs.h>
  15. #include <linux/platform_device.h>
  16. #include "../../pci.h"
  17. #include "pcie-designware.h"
  18. static struct pci_ops dw_pcie_ops;
  19. static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
  20. u32 *val)
  21. {
  22. struct dw_pcie *pci;
  23. if (pp->ops->rd_own_conf)
  24. return pp->ops->rd_own_conf(pp, where, size, val);
  25. pci = to_dw_pcie_from_pp(pp);
  26. return dw_pcie_read(pci->dbi_base + where, size, val);
  27. }
  28. static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
  29. u32 val)
  30. {
  31. struct dw_pcie *pci;
  32. if (pp->ops->wr_own_conf)
  33. return pp->ops->wr_own_conf(pp, where, size, val);
  34. pci = to_dw_pcie_from_pp(pp);
  35. return dw_pcie_write(pci->dbi_base + where, size, val);
  36. }
  37. static void dw_msi_ack_irq(struct irq_data *d)
  38. {
  39. irq_chip_ack_parent(d);
  40. }
  41. static void dw_msi_mask_irq(struct irq_data *d)
  42. {
  43. pci_msi_mask_irq(d);
  44. irq_chip_mask_parent(d);
  45. }
  46. static void dw_msi_unmask_irq(struct irq_data *d)
  47. {
  48. pci_msi_unmask_irq(d);
  49. irq_chip_unmask_parent(d);
  50. }
  51. static struct irq_chip dw_pcie_msi_irq_chip = {
  52. .name = "PCI-MSI",
  53. .irq_ack = dw_msi_ack_irq,
  54. .irq_mask = dw_msi_mask_irq,
  55. .irq_unmask = dw_msi_unmask_irq,
  56. };
  57. static struct msi_domain_info dw_pcie_msi_domain_info = {
  58. .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
  59. MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
  60. .chip = &dw_pcie_msi_irq_chip,
  61. };
  62. /* MSI int handler */
  63. irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
  64. {
  65. int i, pos, irq;
  66. unsigned long val;
  67. u32 status, num_ctrls;
  68. irqreturn_t ret = IRQ_NONE;
  69. num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
  70. for (i = 0; i < num_ctrls; i++) {
  71. dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +
  72. (i * MSI_REG_CTRL_BLOCK_SIZE),
  73. 4, &status);
  74. if (!status)
  75. continue;
  76. ret = IRQ_HANDLED;
  77. val = status;
  78. pos = 0;
  79. while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
  80. pos)) != MAX_MSI_IRQS_PER_CTRL) {
  81. irq = irq_find_mapping(pp->irq_domain,
  82. (i * MAX_MSI_IRQS_PER_CTRL) +
  83. pos);
  84. generic_handle_irq(irq);
  85. pos++;
  86. }
  87. }
  88. return ret;
  89. }
  90. /* Chained MSI interrupt service routine */
  91. static void dw_chained_msi_isr(struct irq_desc *desc)
  92. {
  93. struct irq_chip *chip = irq_desc_get_chip(desc);
  94. struct pcie_port *pp;
  95. chained_irq_enter(chip, desc);
  96. pp = irq_desc_get_handler_data(desc);
  97. dw_handle_msi_irq(pp);
  98. chained_irq_exit(chip, desc);
  99. }
  100. static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg)
  101. {
  102. struct pcie_port *pp = irq_data_get_irq_chip_data(data);
  103. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  104. u64 msi_target;
  105. if (pp->ops->get_msi_addr)
  106. msi_target = pp->ops->get_msi_addr(pp);
  107. else
  108. msi_target = (u64)pp->msi_data;
  109. msg->address_lo = lower_32_bits(msi_target);
  110. msg->address_hi = upper_32_bits(msi_target);
  111. if (pp->ops->get_msi_data)
  112. msg->data = pp->ops->get_msi_data(pp, data->hwirq);
  113. else
  114. msg->data = data->hwirq;
  115. dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
  116. (int)data->hwirq, msg->address_hi, msg->address_lo);
  117. }
  118. static int dw_pci_msi_set_affinity(struct irq_data *irq_data,
  119. const struct cpumask *mask, bool force)
  120. {
  121. return -EINVAL;
  122. }
  123. static void dw_pci_bottom_mask(struct irq_data *data)
  124. {
  125. struct pcie_port *pp = irq_data_get_irq_chip_data(data);
  126. unsigned int res, bit, ctrl;
  127. unsigned long flags;
  128. raw_spin_lock_irqsave(&pp->lock, flags);
  129. if (pp->ops->msi_clear_irq) {
  130. pp->ops->msi_clear_irq(pp, data->hwirq);
  131. } else {
  132. ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;
  133. res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
  134. bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
  135. pp->irq_status[ctrl] &= ~(1 << bit);
  136. dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
  137. ~pp->irq_status[ctrl]);
  138. }
  139. raw_spin_unlock_irqrestore(&pp->lock, flags);
  140. }
  141. static void dw_pci_bottom_unmask(struct irq_data *data)
  142. {
  143. struct pcie_port *pp = irq_data_get_irq_chip_data(data);
  144. unsigned int res, bit, ctrl;
  145. unsigned long flags;
  146. raw_spin_lock_irqsave(&pp->lock, flags);
  147. if (pp->ops->msi_set_irq) {
  148. pp->ops->msi_set_irq(pp, data->hwirq);
  149. } else {
  150. ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL;
  151. res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
  152. bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL;
  153. pp->irq_status[ctrl] |= 1 << bit;
  154. dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
  155. ~pp->irq_status[ctrl]);
  156. }
  157. raw_spin_unlock_irqrestore(&pp->lock, flags);
  158. }
  159. static void dw_pci_bottom_ack(struct irq_data *d)
  160. {
  161. struct pcie_port *pp = irq_data_get_irq_chip_data(d);
  162. unsigned int res, bit, ctrl;
  163. unsigned long flags;
  164. ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
  165. res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
  166. bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
  167. raw_spin_lock_irqsave(&pp->lock, flags);
  168. dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, 1 << bit);
  169. if (pp->ops->msi_irq_ack)
  170. pp->ops->msi_irq_ack(d->hwirq, pp);
  171. raw_spin_unlock_irqrestore(&pp->lock, flags);
  172. }
  173. static struct irq_chip dw_pci_msi_bottom_irq_chip = {
  174. .name = "DWPCI-MSI",
  175. .irq_ack = dw_pci_bottom_ack,
  176. .irq_compose_msi_msg = dw_pci_setup_msi_msg,
  177. .irq_set_affinity = dw_pci_msi_set_affinity,
  178. .irq_mask = dw_pci_bottom_mask,
  179. .irq_unmask = dw_pci_bottom_unmask,
  180. };
  181. static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
  182. unsigned int virq, unsigned int nr_irqs,
  183. void *args)
  184. {
  185. struct pcie_port *pp = domain->host_data;
  186. unsigned long flags;
  187. u32 i;
  188. int bit;
  189. raw_spin_lock_irqsave(&pp->lock, flags);
  190. bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
  191. order_base_2(nr_irqs));
  192. raw_spin_unlock_irqrestore(&pp->lock, flags);
  193. if (bit < 0)
  194. return -ENOSPC;
  195. for (i = 0; i < nr_irqs; i++)
  196. irq_domain_set_info(domain, virq + i, bit + i,
  197. &dw_pci_msi_bottom_irq_chip,
  198. pp, handle_edge_irq,
  199. NULL, NULL);
  200. return 0;
  201. }
  202. static void dw_pcie_irq_domain_free(struct irq_domain *domain,
  203. unsigned int virq, unsigned int nr_irqs)
  204. {
  205. struct irq_data *data = irq_domain_get_irq_data(domain, virq);
  206. struct pcie_port *pp = irq_data_get_irq_chip_data(data);
  207. unsigned long flags;
  208. raw_spin_lock_irqsave(&pp->lock, flags);
  209. bitmap_release_region(pp->msi_irq_in_use, data->hwirq,
  210. order_base_2(nr_irqs));
  211. raw_spin_unlock_irqrestore(&pp->lock, flags);
  212. }
  213. static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
  214. .alloc = dw_pcie_irq_domain_alloc,
  215. .free = dw_pcie_irq_domain_free,
  216. };
  217. int dw_pcie_allocate_domains(struct pcie_port *pp)
  218. {
  219. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  220. struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
  221. pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
  222. &dw_pcie_msi_domain_ops, pp);
  223. if (!pp->irq_domain) {
  224. dev_err(pci->dev, "Failed to create IRQ domain\n");
  225. return -ENOMEM;
  226. }
  227. irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
  228. pp->msi_domain = pci_msi_create_irq_domain(fwnode,
  229. &dw_pcie_msi_domain_info,
  230. pp->irq_domain);
  231. if (!pp->msi_domain) {
  232. dev_err(pci->dev, "Failed to create MSI domain\n");
  233. irq_domain_remove(pp->irq_domain);
  234. return -ENOMEM;
  235. }
  236. return 0;
  237. }
  238. void dw_pcie_free_msi(struct pcie_port *pp)
  239. {
  240. irq_set_chained_handler(pp->msi_irq, NULL);
  241. irq_set_handler_data(pp->msi_irq, NULL);
  242. irq_domain_remove(pp->msi_domain);
  243. irq_domain_remove(pp->irq_domain);
  244. if (pp->msi_page)
  245. __free_page(pp->msi_page);
  246. }
  247. void dw_pcie_msi_init(struct pcie_port *pp)
  248. {
  249. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  250. struct device *dev = pci->dev;
  251. u64 msi_target;
  252. pp->msi_page = alloc_page(GFP_KERNEL);
  253. pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE,
  254. DMA_FROM_DEVICE);
  255. if (dma_mapping_error(dev, pp->msi_data)) {
  256. dev_err(dev, "Failed to map MSI data\n");
  257. __free_page(pp->msi_page);
  258. pp->msi_page = NULL;
  259. return;
  260. }
  261. msi_target = (u64)pp->msi_data;
  262. /* Program the msi_data */
  263. dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
  264. lower_32_bits(msi_target));
  265. dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
  266. upper_32_bits(msi_target));
  267. }
  268. int dw_pcie_host_init(struct pcie_port *pp)
  269. {
  270. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  271. struct device *dev = pci->dev;
  272. struct device_node *np = dev->of_node;
  273. struct platform_device *pdev = to_platform_device(dev);
  274. struct resource_entry *win, *tmp;
  275. struct pci_bus *bus, *child;
  276. struct pci_host_bridge *bridge;
  277. struct resource *cfg_res;
  278. int ret;
  279. raw_spin_lock_init(&pci->pp.lock);
  280. cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
  281. if (cfg_res) {
  282. pp->cfg0_size = resource_size(cfg_res) >> 1;
  283. pp->cfg1_size = resource_size(cfg_res) >> 1;
  284. pp->cfg0_base = cfg_res->start;
  285. pp->cfg1_base = cfg_res->start + pp->cfg0_size;
  286. } else if (!pp->va_cfg0_base) {
  287. dev_err(dev, "Missing *config* reg space\n");
  288. }
  289. bridge = devm_pci_alloc_host_bridge(dev, 0);
  290. if (!bridge)
  291. return -ENOMEM;
  292. ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
  293. &bridge->windows, &pp->io_base);
  294. if (ret)
  295. return ret;
  296. ret = devm_request_pci_bus_resources(dev, &bridge->windows);
  297. if (ret)
  298. return ret;
  299. /* Get the I/O and memory ranges from DT */
  300. resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
  301. switch (resource_type(win->res)) {
  302. case IORESOURCE_IO:
  303. ret = devm_pci_remap_iospace(dev, win->res,
  304. pp->io_base);
  305. if (ret) {
  306. dev_warn(dev, "Error %d: failed to map resource %pR\n",
  307. ret, win->res);
  308. resource_list_destroy_entry(win);
  309. } else {
  310. pp->io = win->res;
  311. pp->io->name = "I/O";
  312. pp->io_size = resource_size(pp->io);
  313. pp->io_bus_addr = pp->io->start - win->offset;
  314. }
  315. break;
  316. case IORESOURCE_MEM:
  317. pp->mem = win->res;
  318. pp->mem->name = "MEM";
  319. pp->mem_size = resource_size(pp->mem);
  320. pp->mem_bus_addr = pp->mem->start - win->offset;
  321. break;
  322. case 0:
  323. pp->cfg = win->res;
  324. pp->cfg0_size = resource_size(pp->cfg) >> 1;
  325. pp->cfg1_size = resource_size(pp->cfg) >> 1;
  326. pp->cfg0_base = pp->cfg->start;
  327. pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
  328. break;
  329. case IORESOURCE_BUS:
  330. pp->busn = win->res;
  331. break;
  332. }
  333. }
  334. if (!pci->dbi_base) {
  335. pci->dbi_base = devm_pci_remap_cfgspace(dev,
  336. pp->cfg->start,
  337. resource_size(pp->cfg));
  338. if (!pci->dbi_base) {
  339. dev_err(dev, "Error with ioremap\n");
  340. return -ENOMEM;
  341. }
  342. }
  343. pp->mem_base = pp->mem->start;
  344. if (!pp->va_cfg0_base) {
  345. pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
  346. pp->cfg0_base, pp->cfg0_size);
  347. if (!pp->va_cfg0_base) {
  348. dev_err(dev, "Error with ioremap in function\n");
  349. return -ENOMEM;
  350. }
  351. }
  352. if (!pp->va_cfg1_base) {
  353. pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
  354. pp->cfg1_base,
  355. pp->cfg1_size);
  356. if (!pp->va_cfg1_base) {
  357. dev_err(dev, "Error with ioremap\n");
  358. return -ENOMEM;
  359. }
  360. }
  361. ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
  362. if (ret)
  363. pci->num_viewport = 2;
  364. if (pci_msi_enabled()) {
  365. /*
  366. * If a specific SoC driver needs to change the
  367. * default number of vectors, it needs to implement
  368. * the set_num_vectors callback.
  369. */
  370. if (!pp->ops->set_num_vectors) {
  371. pp->num_vectors = MSI_DEF_NUM_VECTORS;
  372. } else {
  373. pp->ops->set_num_vectors(pp);
  374. if (pp->num_vectors > MAX_MSI_IRQS ||
  375. pp->num_vectors == 0) {
  376. dev_err(dev,
  377. "Invalid number of vectors\n");
  378. return -EINVAL;
  379. }
  380. }
  381. if (!pp->ops->msi_host_init) {
  382. ret = dw_pcie_allocate_domains(pp);
  383. if (ret)
  384. return ret;
  385. if (pp->msi_irq)
  386. irq_set_chained_handler_and_data(pp->msi_irq,
  387. dw_chained_msi_isr,
  388. pp);
  389. } else {
  390. ret = pp->ops->msi_host_init(pp);
  391. if (ret < 0)
  392. return ret;
  393. }
  394. }
  395. if (pp->ops->host_init) {
  396. ret = pp->ops->host_init(pp);
  397. if (ret)
  398. goto err_free_msi;
  399. }
  400. pp->root_bus_nr = pp->busn->start;
  401. bridge->dev.parent = dev;
  402. bridge->sysdata = pp;
  403. bridge->busnr = pp->root_bus_nr;
  404. bridge->ops = &dw_pcie_ops;
  405. bridge->map_irq = of_irq_parse_and_map_pci;
  406. bridge->swizzle_irq = pci_common_swizzle;
  407. ret = pci_scan_root_bus_bridge(bridge);
  408. if (ret)
  409. goto err_free_msi;
  410. bus = bridge->bus;
  411. if (pp->ops->scan_bus)
  412. pp->ops->scan_bus(pp);
  413. pci_bus_size_bridges(bus);
  414. pci_bus_assign_resources(bus);
  415. list_for_each_entry(child, &bus->children, node)
  416. pcie_bus_configure_settings(child);
  417. pci_bus_add_devices(bus);
  418. return 0;
  419. err_free_msi:
  420. if (pci_msi_enabled() && !pp->ops->msi_host_init)
  421. dw_pcie_free_msi(pp);
  422. return ret;
  423. }
  424. static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
  425. u32 devfn, int where, int size, u32 *val)
  426. {
  427. int ret, type;
  428. u32 busdev, cfg_size;
  429. u64 cpu_addr;
  430. void __iomem *va_cfg_base;
  431. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  432. if (pp->ops->rd_other_conf)
  433. return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
  434. busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
  435. PCIE_ATU_FUNC(PCI_FUNC(devfn));
  436. if (bus->parent->number == pp->root_bus_nr) {
  437. type = PCIE_ATU_TYPE_CFG0;
  438. cpu_addr = pp->cfg0_base;
  439. cfg_size = pp->cfg0_size;
  440. va_cfg_base = pp->va_cfg0_base;
  441. } else {
  442. type = PCIE_ATU_TYPE_CFG1;
  443. cpu_addr = pp->cfg1_base;
  444. cfg_size = pp->cfg1_size;
  445. va_cfg_base = pp->va_cfg1_base;
  446. }
  447. dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
  448. type, cpu_addr,
  449. busdev, cfg_size);
  450. ret = dw_pcie_read(va_cfg_base + where, size, val);
  451. if (pci->num_viewport <= 2)
  452. dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
  453. PCIE_ATU_TYPE_IO, pp->io_base,
  454. pp->io_bus_addr, pp->io_size);
  455. return ret;
  456. }
  457. static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
  458. u32 devfn, int where, int size, u32 val)
  459. {
  460. int ret, type;
  461. u32 busdev, cfg_size;
  462. u64 cpu_addr;
  463. void __iomem *va_cfg_base;
  464. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  465. if (pp->ops->wr_other_conf)
  466. return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
  467. busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
  468. PCIE_ATU_FUNC(PCI_FUNC(devfn));
  469. if (bus->parent->number == pp->root_bus_nr) {
  470. type = PCIE_ATU_TYPE_CFG0;
  471. cpu_addr = pp->cfg0_base;
  472. cfg_size = pp->cfg0_size;
  473. va_cfg_base = pp->va_cfg0_base;
  474. } else {
  475. type = PCIE_ATU_TYPE_CFG1;
  476. cpu_addr = pp->cfg1_base;
  477. cfg_size = pp->cfg1_size;
  478. va_cfg_base = pp->va_cfg1_base;
  479. }
  480. dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
  481. type, cpu_addr,
  482. busdev, cfg_size);
  483. ret = dw_pcie_write(va_cfg_base + where, size, val);
  484. if (pci->num_viewport <= 2)
  485. dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
  486. PCIE_ATU_TYPE_IO, pp->io_base,
  487. pp->io_bus_addr, pp->io_size);
  488. return ret;
  489. }
  490. static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
  491. int dev)
  492. {
  493. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  494. /* If there is no link, then there is no device */
  495. if (bus->number != pp->root_bus_nr) {
  496. if (!dw_pcie_link_up(pci))
  497. return 0;
  498. }
  499. /* Access only one slot on each root port */
  500. if (bus->number == pp->root_bus_nr && dev > 0)
  501. return 0;
  502. return 1;
  503. }
  504. static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  505. int size, u32 *val)
  506. {
  507. struct pcie_port *pp = bus->sysdata;
  508. if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
  509. *val = 0xffffffff;
  510. return PCIBIOS_DEVICE_NOT_FOUND;
  511. }
  512. if (bus->number == pp->root_bus_nr)
  513. return dw_pcie_rd_own_conf(pp, where, size, val);
  514. return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
  515. }
  516. static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
  517. int where, int size, u32 val)
  518. {
  519. struct pcie_port *pp = bus->sysdata;
  520. if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
  521. return PCIBIOS_DEVICE_NOT_FOUND;
  522. if (bus->number == pp->root_bus_nr)
  523. return dw_pcie_wr_own_conf(pp, where, size, val);
  524. return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
  525. }
  526. static struct pci_ops dw_pcie_ops = {
  527. .read = dw_pcie_rd_conf,
  528. .write = dw_pcie_wr_conf,
  529. };
  530. static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
  531. {
  532. u32 val;
  533. val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
  534. if (val == 0xffffffff)
  535. return 1;
  536. return 0;
  537. }
  538. void dw_pcie_setup_rc(struct pcie_port *pp)
  539. {
  540. u32 val, ctrl, num_ctrls;
  541. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  542. dw_pcie_setup(pci);
  543. num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
  544. /* Initialize IRQ Status array */
  545. for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
  546. dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
  547. (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
  548. 4, ~0);
  549. dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
  550. (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
  551. 4, ~0);
  552. pp->irq_status[ctrl] = 0;
  553. }
  554. /* Setup RC BARs */
  555. dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
  556. dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
  557. /* Setup interrupt pins */
  558. dw_pcie_dbi_ro_wr_en(pci);
  559. val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
  560. val &= 0xffff00ff;
  561. val |= 0x00000100;
  562. dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
  563. dw_pcie_dbi_ro_wr_dis(pci);
  564. /* Setup bus numbers */
  565. val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
  566. val &= 0xff000000;
  567. val |= 0x00ff0100;
  568. dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
  569. /* Setup command register */
  570. val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
  571. val &= 0xffff0000;
  572. val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  573. PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
  574. dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
  575. /*
  576. * If the platform provides ->rd_other_conf, it means the platform
  577. * uses its own address translation component rather than ATU, so
  578. * we should not program the ATU here.
  579. */
  580. if (!pp->ops->rd_other_conf) {
  581. /* Get iATU unroll support */
  582. pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
  583. dev_dbg(pci->dev, "iATU unroll: %s\n",
  584. pci->iatu_unroll_enabled ? "enabled" : "disabled");
  585. dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
  586. PCIE_ATU_TYPE_MEM, pp->mem_base,
  587. pp->mem_bus_addr, pp->mem_size);
  588. if (pci->num_viewport > 2)
  589. dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
  590. PCIE_ATU_TYPE_IO, pp->io_base,
  591. pp->io_bus_addr, pp->io_size);
  592. }
  593. dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
  594. /* Enable write permission for the DBI read-only register */
  595. dw_pcie_dbi_ro_wr_en(pci);
  596. /* Program correct class for RC */
  597. dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
  598. /* Better disable write permission right after the update */
  599. dw_pcie_dbi_ro_wr_dis(pci);
  600. dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
  601. val |= PORT_LOGIC_SPEED_CHANGE;
  602. dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
  603. }