pinctrl-at91-pio4.c 32 KB

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  1. /*
  2. * Driver for the Atmel PIO4 controller
  3. *
  4. * Copyright (C) 2015 Atmel,
  5. * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
  6. *
  7. * This software is licensed under the terms of the GNU General Public
  8. * License version 2, as published by the Free Software Foundation, and
  9. * may be copied, distributed, and modified under those terms.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <dt-bindings/pinctrl/at91.h>
  17. #include <linux/clk.h>
  18. #include <linux/gpio/driver.h>
  19. /* FIXME: needed for gpio_to_irq(), get rid of this */
  20. #include <linux/gpio.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/io.h>
  23. #include <linux/init.h>
  24. #include <linux/of.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/pinctrl/pinconf.h>
  27. #include <linux/pinctrl/pinconf-generic.h>
  28. #include <linux/pinctrl/pinctrl.h>
  29. #include <linux/pinctrl/pinmux.h>
  30. #include <linux/slab.h>
  31. #include "core.h"
  32. #include "pinconf.h"
  33. #include "pinctrl-utils.h"
  34. /*
  35. * Warning:
  36. * In order to not introduce confusion between Atmel PIO groups and pinctrl
  37. * framework groups, Atmel PIO groups will be called banks, line is kept to
  38. * designed the pin id into this bank.
  39. */
  40. #define ATMEL_PIO_MSKR 0x0000
  41. #define ATMEL_PIO_CFGR 0x0004
  42. #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
  43. #define ATMEL_PIO_DIR_MASK BIT(8)
  44. #define ATMEL_PIO_PUEN_MASK BIT(9)
  45. #define ATMEL_PIO_PDEN_MASK BIT(10)
  46. #define ATMEL_PIO_IFEN_MASK BIT(12)
  47. #define ATMEL_PIO_IFSCEN_MASK BIT(13)
  48. #define ATMEL_PIO_OPD_MASK BIT(14)
  49. #define ATMEL_PIO_SCHMITT_MASK BIT(15)
  50. #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
  51. #define ATMEL_PIO_DRVSTR_OFFSET 16
  52. #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
  53. #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
  54. #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
  55. #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
  56. #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
  57. #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
  58. #define ATMEL_PIO_PDSR 0x0008
  59. #define ATMEL_PIO_LOCKSR 0x000C
  60. #define ATMEL_PIO_SODR 0x0010
  61. #define ATMEL_PIO_CODR 0x0014
  62. #define ATMEL_PIO_ODSR 0x0018
  63. #define ATMEL_PIO_IER 0x0020
  64. #define ATMEL_PIO_IDR 0x0024
  65. #define ATMEL_PIO_IMR 0x0028
  66. #define ATMEL_PIO_ISR 0x002C
  67. #define ATMEL_PIO_IOFR 0x003C
  68. #define ATMEL_PIO_NPINS_PER_BANK 32
  69. #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
  70. #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
  71. #define ATMEL_PIO_BANK_OFFSET 0x40
  72. #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
  73. #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
  74. #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
  75. /* Custom pinconf parameters */
  76. #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
  77. struct atmel_pioctrl_data {
  78. unsigned nbanks;
  79. };
  80. struct atmel_group {
  81. const char *name;
  82. u32 pin;
  83. };
  84. struct atmel_pin {
  85. unsigned pin_id;
  86. unsigned mux;
  87. unsigned ioset;
  88. unsigned bank;
  89. unsigned line;
  90. const char *device;
  91. };
  92. /**
  93. * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
  94. * @reg_base: base address of the controller.
  95. * @clk: clock of the controller.
  96. * @nbanks: number of PIO groups, it can vary depending on the SoC.
  97. * @pinctrl_dev: pinctrl device registered.
  98. * @groups: groups table to provide group name and pin in the group to pinctrl.
  99. * @group_names: group names table to provide all the group/pin names to
  100. * pinctrl or gpio.
  101. * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
  102. * fields are set at probe time. Other ones are set when parsing dt
  103. * pinctrl.
  104. * @npins: number of pins.
  105. * @gpio_chip: gpio chip registered.
  106. * @irq_domain: irq domain for the gpio controller.
  107. * @irqs: table containing the hw irq number of the bank. The index of the
  108. * table is the bank id.
  109. * @dev: device entry for the Atmel PIO controller.
  110. * @node: node of the Atmel PIO controller.
  111. */
  112. struct atmel_pioctrl {
  113. void __iomem *reg_base;
  114. struct clk *clk;
  115. unsigned nbanks;
  116. struct pinctrl_dev *pinctrl_dev;
  117. struct atmel_group *groups;
  118. const char * const *group_names;
  119. struct atmel_pin **pins;
  120. unsigned npins;
  121. struct gpio_chip *gpio_chip;
  122. struct irq_domain *irq_domain;
  123. int *irqs;
  124. unsigned *pm_wakeup_sources;
  125. struct {
  126. u32 imr;
  127. u32 odsr;
  128. u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
  129. } *pm_suspend_backup;
  130. struct device *dev;
  131. struct device_node *node;
  132. };
  133. static const char * const atmel_functions[] = {
  134. "GPIO", "A", "B", "C", "D", "E", "F", "G"
  135. };
  136. static const struct pinconf_generic_params atmel_custom_bindings[] = {
  137. {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
  138. };
  139. /* --- GPIO --- */
  140. static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
  141. unsigned int bank, unsigned int reg)
  142. {
  143. return readl_relaxed(atmel_pioctrl->reg_base
  144. + ATMEL_PIO_BANK_OFFSET * bank + reg);
  145. }
  146. static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
  147. unsigned int bank, unsigned int reg,
  148. unsigned int val)
  149. {
  150. writel_relaxed(val, atmel_pioctrl->reg_base
  151. + ATMEL_PIO_BANK_OFFSET * bank + reg);
  152. }
  153. static void atmel_gpio_irq_ack(struct irq_data *d)
  154. {
  155. /*
  156. * Nothing to do, interrupt is cleared when reading the status
  157. * register.
  158. */
  159. }
  160. static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
  161. {
  162. struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
  163. struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
  164. unsigned reg;
  165. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
  166. BIT(pin->line));
  167. reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
  168. reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
  169. switch (type) {
  170. case IRQ_TYPE_EDGE_RISING:
  171. irq_set_handler_locked(d, handle_edge_irq);
  172. reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
  173. break;
  174. case IRQ_TYPE_EDGE_FALLING:
  175. irq_set_handler_locked(d, handle_edge_irq);
  176. reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
  177. break;
  178. case IRQ_TYPE_EDGE_BOTH:
  179. irq_set_handler_locked(d, handle_edge_irq);
  180. reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
  181. break;
  182. case IRQ_TYPE_LEVEL_LOW:
  183. irq_set_handler_locked(d, handle_level_irq);
  184. reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
  185. break;
  186. case IRQ_TYPE_LEVEL_HIGH:
  187. irq_set_handler_locked(d, handle_level_irq);
  188. reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
  189. break;
  190. case IRQ_TYPE_NONE:
  191. default:
  192. return -EINVAL;
  193. }
  194. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
  195. return 0;
  196. }
  197. static void atmel_gpio_irq_mask(struct irq_data *d)
  198. {
  199. struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
  200. struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
  201. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
  202. BIT(pin->line));
  203. }
  204. static void atmel_gpio_irq_unmask(struct irq_data *d)
  205. {
  206. struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
  207. struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
  208. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
  209. BIT(pin->line));
  210. }
  211. #ifdef CONFIG_PM_SLEEP
  212. static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
  213. {
  214. struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
  215. int bank = ATMEL_PIO_BANK(d->hwirq);
  216. int line = ATMEL_PIO_LINE(d->hwirq);
  217. /* The gpio controller has one interrupt line per bank. */
  218. irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
  219. if (on)
  220. atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
  221. else
  222. atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
  223. return 0;
  224. }
  225. #else
  226. #define atmel_gpio_irq_set_wake NULL
  227. #endif /* CONFIG_PM_SLEEP */
  228. static struct irq_chip atmel_gpio_irq_chip = {
  229. .name = "GPIO",
  230. .irq_ack = atmel_gpio_irq_ack,
  231. .irq_mask = atmel_gpio_irq_mask,
  232. .irq_unmask = atmel_gpio_irq_unmask,
  233. .irq_set_type = atmel_gpio_irq_set_type,
  234. .irq_set_wake = atmel_gpio_irq_set_wake,
  235. };
  236. static void atmel_gpio_irq_handler(struct irq_desc *desc)
  237. {
  238. unsigned int irq = irq_desc_get_irq(desc);
  239. struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
  240. struct irq_chip *chip = irq_desc_get_chip(desc);
  241. unsigned long isr;
  242. int n, bank = -1;
  243. /* Find from which bank is the irq received. */
  244. for (n = 0; n < atmel_pioctrl->nbanks; n++) {
  245. if (atmel_pioctrl->irqs[n] == irq) {
  246. bank = n;
  247. break;
  248. }
  249. }
  250. if (bank < 0) {
  251. dev_err(atmel_pioctrl->dev,
  252. "no bank associated to irq %u\n", irq);
  253. return;
  254. }
  255. chained_irq_enter(chip, desc);
  256. for (;;) {
  257. isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
  258. ATMEL_PIO_ISR);
  259. isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
  260. ATMEL_PIO_IMR);
  261. if (!isr)
  262. break;
  263. for_each_set_bit(n, &isr, BITS_PER_LONG)
  264. generic_handle_irq(gpio_to_irq(bank *
  265. ATMEL_PIO_NPINS_PER_BANK + n));
  266. }
  267. chained_irq_exit(chip, desc);
  268. }
  269. static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  270. {
  271. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  272. struct atmel_pin *pin = atmel_pioctrl->pins[offset];
  273. unsigned reg;
  274. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
  275. BIT(pin->line));
  276. reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
  277. reg &= ~ATMEL_PIO_DIR_MASK;
  278. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
  279. return 0;
  280. }
  281. static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
  282. {
  283. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  284. struct atmel_pin *pin = atmel_pioctrl->pins[offset];
  285. unsigned reg;
  286. reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
  287. return !!(reg & BIT(pin->line));
  288. }
  289. static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  290. int value)
  291. {
  292. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  293. struct atmel_pin *pin = atmel_pioctrl->pins[offset];
  294. unsigned reg;
  295. atmel_gpio_write(atmel_pioctrl, pin->bank,
  296. value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
  297. BIT(pin->line));
  298. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
  299. BIT(pin->line));
  300. reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
  301. reg |= ATMEL_PIO_DIR_MASK;
  302. atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
  303. return 0;
  304. }
  305. static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  306. {
  307. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  308. struct atmel_pin *pin = atmel_pioctrl->pins[offset];
  309. atmel_gpio_write(atmel_pioctrl, pin->bank,
  310. val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
  311. BIT(pin->line));
  312. }
  313. static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  314. {
  315. struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
  316. return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
  317. }
  318. static struct gpio_chip atmel_gpio_chip = {
  319. .direction_input = atmel_gpio_direction_input,
  320. .get = atmel_gpio_get,
  321. .direction_output = atmel_gpio_direction_output,
  322. .set = atmel_gpio_set,
  323. .to_irq = atmel_gpio_to_irq,
  324. .base = 0,
  325. };
  326. /* --- PINCTRL --- */
  327. static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
  328. unsigned pin_id)
  329. {
  330. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  331. unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
  332. unsigned line = atmel_pioctrl->pins[pin_id]->line;
  333. void __iomem *addr = atmel_pioctrl->reg_base
  334. + bank * ATMEL_PIO_BANK_OFFSET;
  335. writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
  336. /* Have to set MSKR first, to access the right pin CFGR. */
  337. wmb();
  338. return readl_relaxed(addr + ATMEL_PIO_CFGR);
  339. }
  340. static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
  341. unsigned pin_id, u32 conf)
  342. {
  343. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  344. unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
  345. unsigned line = atmel_pioctrl->pins[pin_id]->line;
  346. void __iomem *addr = atmel_pioctrl->reg_base
  347. + bank * ATMEL_PIO_BANK_OFFSET;
  348. writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
  349. /* Have to set MSKR first, to access the right pin CFGR. */
  350. wmb();
  351. writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
  352. }
  353. static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
  354. {
  355. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  356. return atmel_pioctrl->npins;
  357. }
  358. static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
  359. unsigned selector)
  360. {
  361. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  362. return atmel_pioctrl->groups[selector].name;
  363. }
  364. static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
  365. unsigned selector, const unsigned **pins,
  366. unsigned *num_pins)
  367. {
  368. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  369. *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
  370. *num_pins = 1;
  371. return 0;
  372. }
  373. static struct atmel_group *
  374. atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
  375. {
  376. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  377. int i;
  378. for (i = 0; i < atmel_pioctrl->npins; i++) {
  379. struct atmel_group *grp = atmel_pioctrl->groups + i;
  380. if (grp->pin == pin)
  381. return grp;
  382. }
  383. return NULL;
  384. }
  385. static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
  386. struct device_node *np,
  387. u32 pinfunc, const char **grp_name,
  388. const char **func_name)
  389. {
  390. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  391. unsigned pin_id, func_id;
  392. struct atmel_group *grp;
  393. pin_id = ATMEL_GET_PIN_NO(pinfunc);
  394. func_id = ATMEL_GET_PIN_FUNC(pinfunc);
  395. if (func_id >= ARRAY_SIZE(atmel_functions))
  396. return -EINVAL;
  397. *func_name = atmel_functions[func_id];
  398. grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
  399. if (!grp)
  400. return -EINVAL;
  401. *grp_name = grp->name;
  402. atmel_pioctrl->pins[pin_id]->mux = func_id;
  403. atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
  404. /* Want the device name not the group one. */
  405. if (np->parent == atmel_pioctrl->node)
  406. atmel_pioctrl->pins[pin_id]->device = np->name;
  407. else
  408. atmel_pioctrl->pins[pin_id]->device = np->parent->name;
  409. return 0;
  410. }
  411. static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
  412. struct device_node *np,
  413. struct pinctrl_map **map,
  414. unsigned *reserved_maps,
  415. unsigned *num_maps)
  416. {
  417. unsigned num_pins, num_configs, reserve;
  418. unsigned long *configs;
  419. struct property *pins;
  420. u32 pinfunc;
  421. int ret, i;
  422. pins = of_find_property(np, "pinmux", NULL);
  423. if (!pins)
  424. return -EINVAL;
  425. ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
  426. &num_configs);
  427. if (ret < 0) {
  428. dev_err(pctldev->dev, "%pOF: could not parse node property\n",
  429. np);
  430. return ret;
  431. }
  432. num_pins = pins->length / sizeof(u32);
  433. if (!num_pins) {
  434. dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
  435. ret = -EINVAL;
  436. goto exit;
  437. }
  438. /*
  439. * Reserve maps, at least there is a mux map and an optional conf
  440. * map for each pin.
  441. */
  442. reserve = 1;
  443. if (num_configs)
  444. reserve++;
  445. reserve *= num_pins;
  446. ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
  447. reserve);
  448. if (ret < 0)
  449. goto exit;
  450. for (i = 0; i < num_pins; i++) {
  451. const char *group, *func;
  452. ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
  453. if (ret)
  454. goto exit;
  455. ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
  456. &func);
  457. if (ret)
  458. goto exit;
  459. pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
  460. group, func);
  461. if (num_configs) {
  462. ret = pinctrl_utils_add_map_configs(pctldev, map,
  463. reserved_maps, num_maps, group,
  464. configs, num_configs,
  465. PIN_MAP_TYPE_CONFIGS_GROUP);
  466. if (ret < 0)
  467. goto exit;
  468. }
  469. }
  470. exit:
  471. kfree(configs);
  472. return ret;
  473. }
  474. static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
  475. struct device_node *np_config,
  476. struct pinctrl_map **map,
  477. unsigned *num_maps)
  478. {
  479. struct device_node *np;
  480. unsigned reserved_maps;
  481. int ret;
  482. *map = NULL;
  483. *num_maps = 0;
  484. reserved_maps = 0;
  485. /*
  486. * If all the pins of a device have the same configuration (or no one),
  487. * it is useless to add a subnode, so directly parse node referenced by
  488. * phandle.
  489. */
  490. ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
  491. &reserved_maps, num_maps);
  492. if (ret) {
  493. for_each_child_of_node(np_config, np) {
  494. ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
  495. &reserved_maps, num_maps);
  496. if (ret < 0) {
  497. of_node_put(np);
  498. break;
  499. }
  500. }
  501. }
  502. if (ret < 0) {
  503. pinctrl_utils_free_map(pctldev, *map, *num_maps);
  504. dev_err(pctldev->dev, "can't create maps for node %pOF\n",
  505. np_config);
  506. }
  507. return ret;
  508. }
  509. static const struct pinctrl_ops atmel_pctlops = {
  510. .get_groups_count = atmel_pctl_get_groups_count,
  511. .get_group_name = atmel_pctl_get_group_name,
  512. .get_group_pins = atmel_pctl_get_group_pins,
  513. .dt_node_to_map = atmel_pctl_dt_node_to_map,
  514. .dt_free_map = pinctrl_utils_free_map,
  515. };
  516. static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
  517. {
  518. return ARRAY_SIZE(atmel_functions);
  519. }
  520. static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
  521. unsigned selector)
  522. {
  523. return atmel_functions[selector];
  524. }
  525. static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
  526. unsigned selector,
  527. const char * const **groups,
  528. unsigned * const num_groups)
  529. {
  530. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  531. *groups = atmel_pioctrl->group_names;
  532. *num_groups = atmel_pioctrl->npins;
  533. return 0;
  534. }
  535. static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
  536. unsigned function,
  537. unsigned group)
  538. {
  539. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  540. unsigned pin;
  541. u32 conf;
  542. dev_dbg(pctldev->dev, "enable function %s group %s\n",
  543. atmel_functions[function], atmel_pioctrl->groups[group].name);
  544. pin = atmel_pioctrl->groups[group].pin;
  545. conf = atmel_pin_config_read(pctldev, pin);
  546. conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
  547. conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
  548. dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
  549. atmel_pin_config_write(pctldev, pin, conf);
  550. return 0;
  551. }
  552. static const struct pinmux_ops atmel_pmxops = {
  553. .get_functions_count = atmel_pmx_get_functions_count,
  554. .get_function_name = atmel_pmx_get_function_name,
  555. .get_function_groups = atmel_pmx_get_function_groups,
  556. .set_mux = atmel_pmx_set_mux,
  557. };
  558. static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
  559. unsigned group,
  560. unsigned long *config)
  561. {
  562. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  563. unsigned param = pinconf_to_config_param(*config), arg = 0;
  564. struct atmel_group *grp = atmel_pioctrl->groups + group;
  565. unsigned pin_id = grp->pin;
  566. u32 res;
  567. res = atmel_pin_config_read(pctldev, pin_id);
  568. switch (param) {
  569. case PIN_CONFIG_BIAS_PULL_UP:
  570. if (!(res & ATMEL_PIO_PUEN_MASK))
  571. return -EINVAL;
  572. arg = 1;
  573. break;
  574. case PIN_CONFIG_BIAS_PULL_DOWN:
  575. if ((res & ATMEL_PIO_PUEN_MASK) ||
  576. (!(res & ATMEL_PIO_PDEN_MASK)))
  577. return -EINVAL;
  578. arg = 1;
  579. break;
  580. case PIN_CONFIG_BIAS_DISABLE:
  581. if ((res & ATMEL_PIO_PUEN_MASK) ||
  582. ((res & ATMEL_PIO_PDEN_MASK)))
  583. return -EINVAL;
  584. arg = 1;
  585. break;
  586. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  587. if (!(res & ATMEL_PIO_OPD_MASK))
  588. return -EINVAL;
  589. arg = 1;
  590. break;
  591. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  592. if (!(res & ATMEL_PIO_SCHMITT_MASK))
  593. return -EINVAL;
  594. arg = 1;
  595. break;
  596. case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
  597. if (!(res & ATMEL_PIO_DRVSTR_MASK))
  598. return -EINVAL;
  599. arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
  600. break;
  601. default:
  602. return -ENOTSUPP;
  603. }
  604. *config = pinconf_to_config_packed(param, arg);
  605. return 0;
  606. }
  607. static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
  608. unsigned group,
  609. unsigned long *configs,
  610. unsigned num_configs)
  611. {
  612. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  613. struct atmel_group *grp = atmel_pioctrl->groups + group;
  614. unsigned bank, pin, pin_id = grp->pin;
  615. u32 mask, conf = 0;
  616. int i;
  617. conf = atmel_pin_config_read(pctldev, pin_id);
  618. for (i = 0; i < num_configs; i++) {
  619. unsigned param = pinconf_to_config_param(configs[i]);
  620. unsigned arg = pinconf_to_config_argument(configs[i]);
  621. dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
  622. __func__, pin_id, configs[i]);
  623. switch (param) {
  624. case PIN_CONFIG_BIAS_DISABLE:
  625. conf &= (~ATMEL_PIO_PUEN_MASK);
  626. conf &= (~ATMEL_PIO_PDEN_MASK);
  627. break;
  628. case PIN_CONFIG_BIAS_PULL_UP:
  629. conf |= ATMEL_PIO_PUEN_MASK;
  630. conf &= (~ATMEL_PIO_PDEN_MASK);
  631. break;
  632. case PIN_CONFIG_BIAS_PULL_DOWN:
  633. conf |= ATMEL_PIO_PDEN_MASK;
  634. conf &= (~ATMEL_PIO_PUEN_MASK);
  635. break;
  636. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  637. if (arg == 0)
  638. conf &= (~ATMEL_PIO_OPD_MASK);
  639. else
  640. conf |= ATMEL_PIO_OPD_MASK;
  641. break;
  642. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  643. if (arg == 0)
  644. conf |= ATMEL_PIO_SCHMITT_MASK;
  645. else
  646. conf &= (~ATMEL_PIO_SCHMITT_MASK);
  647. break;
  648. case PIN_CONFIG_INPUT_DEBOUNCE:
  649. if (arg == 0) {
  650. conf &= (~ATMEL_PIO_IFEN_MASK);
  651. conf &= (~ATMEL_PIO_IFSCEN_MASK);
  652. } else {
  653. /*
  654. * We don't care about the debounce value for several reasons:
  655. * - can't have different debounce periods inside a same group,
  656. * - the register to configure this period is a secure register.
  657. * The debouncing filter can filter a pulse with a duration of less
  658. * than 1/2 slow clock period.
  659. */
  660. conf |= ATMEL_PIO_IFEN_MASK;
  661. conf |= ATMEL_PIO_IFSCEN_MASK;
  662. }
  663. break;
  664. case PIN_CONFIG_OUTPUT:
  665. conf |= ATMEL_PIO_DIR_MASK;
  666. bank = ATMEL_PIO_BANK(pin_id);
  667. pin = ATMEL_PIO_LINE(pin_id);
  668. mask = 1 << pin;
  669. if (arg == 0) {
  670. writel_relaxed(mask, atmel_pioctrl->reg_base +
  671. bank * ATMEL_PIO_BANK_OFFSET +
  672. ATMEL_PIO_CODR);
  673. } else {
  674. writel_relaxed(mask, atmel_pioctrl->reg_base +
  675. bank * ATMEL_PIO_BANK_OFFSET +
  676. ATMEL_PIO_SODR);
  677. }
  678. break;
  679. case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
  680. switch (arg) {
  681. case ATMEL_PIO_DRVSTR_LO:
  682. case ATMEL_PIO_DRVSTR_ME:
  683. case ATMEL_PIO_DRVSTR_HI:
  684. conf &= (~ATMEL_PIO_DRVSTR_MASK);
  685. conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
  686. break;
  687. default:
  688. dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
  689. }
  690. break;
  691. default:
  692. dev_warn(pctldev->dev,
  693. "unsupported configuration parameter: %u\n",
  694. param);
  695. continue;
  696. }
  697. }
  698. dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
  699. atmel_pin_config_write(pctldev, pin_id, conf);
  700. return 0;
  701. }
  702. static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
  703. struct seq_file *s, unsigned pin_id)
  704. {
  705. struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
  706. u32 conf;
  707. if (!atmel_pioctrl->pins[pin_id]->device)
  708. return;
  709. if (atmel_pioctrl->pins[pin_id])
  710. seq_printf(s, " (%s, ioset %u) ",
  711. atmel_pioctrl->pins[pin_id]->device,
  712. atmel_pioctrl->pins[pin_id]->ioset);
  713. conf = atmel_pin_config_read(pctldev, pin_id);
  714. if (conf & ATMEL_PIO_PUEN_MASK)
  715. seq_printf(s, "%s ", "pull-up");
  716. if (conf & ATMEL_PIO_PDEN_MASK)
  717. seq_printf(s, "%s ", "pull-down");
  718. if (conf & ATMEL_PIO_IFEN_MASK)
  719. seq_printf(s, "%s ", "debounce");
  720. if (conf & ATMEL_PIO_OPD_MASK)
  721. seq_printf(s, "%s ", "open-drain");
  722. if (conf & ATMEL_PIO_SCHMITT_MASK)
  723. seq_printf(s, "%s ", "schmitt");
  724. if (conf & ATMEL_PIO_DRVSTR_MASK) {
  725. switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
  726. case ATMEL_PIO_DRVSTR_ME:
  727. seq_printf(s, "%s ", "medium-drive");
  728. break;
  729. case ATMEL_PIO_DRVSTR_HI:
  730. seq_printf(s, "%s ", "high-drive");
  731. break;
  732. /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
  733. default:
  734. seq_printf(s, "%s ", "low-drive");
  735. }
  736. }
  737. }
  738. static const struct pinconf_ops atmel_confops = {
  739. .pin_config_group_get = atmel_conf_pin_config_group_get,
  740. .pin_config_group_set = atmel_conf_pin_config_group_set,
  741. .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
  742. };
  743. static struct pinctrl_desc atmel_pinctrl_desc = {
  744. .name = "atmel_pinctrl",
  745. .confops = &atmel_confops,
  746. .pctlops = &atmel_pctlops,
  747. .pmxops = &atmel_pmxops,
  748. };
  749. static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
  750. {
  751. struct platform_device *pdev = to_platform_device(dev);
  752. struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
  753. int i, j;
  754. /*
  755. * For each bank, save IMR to restore it later and disable all GPIO
  756. * interrupts excepting the ones marked as wakeup sources.
  757. */
  758. for (i = 0; i < atmel_pioctrl->nbanks; i++) {
  759. atmel_pioctrl->pm_suspend_backup[i].imr =
  760. atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
  761. atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
  762. ~atmel_pioctrl->pm_wakeup_sources[i]);
  763. atmel_pioctrl->pm_suspend_backup[i].odsr =
  764. atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
  765. for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
  766. atmel_gpio_write(atmel_pioctrl, i,
  767. ATMEL_PIO_MSKR, BIT(j));
  768. atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
  769. atmel_gpio_read(atmel_pioctrl, i,
  770. ATMEL_PIO_CFGR);
  771. }
  772. }
  773. return 0;
  774. }
  775. static int __maybe_unused atmel_pctrl_resume(struct device *dev)
  776. {
  777. struct platform_device *pdev = to_platform_device(dev);
  778. struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
  779. int i, j;
  780. for (i = 0; i < atmel_pioctrl->nbanks; i++) {
  781. atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
  782. atmel_pioctrl->pm_suspend_backup[i].imr);
  783. atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
  784. atmel_pioctrl->pm_suspend_backup[i].odsr);
  785. for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
  786. atmel_gpio_write(atmel_pioctrl, i,
  787. ATMEL_PIO_MSKR, BIT(j));
  788. atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
  789. atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
  790. }
  791. }
  792. return 0;
  793. }
  794. static const struct dev_pm_ops atmel_pctrl_pm_ops = {
  795. SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
  796. };
  797. /*
  798. * The number of banks can be different from a SoC to another one.
  799. * We can have up to 16 banks.
  800. */
  801. static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
  802. .nbanks = 4,
  803. };
  804. static const struct of_device_id atmel_pctrl_of_match[] = {
  805. {
  806. .compatible = "atmel,sama5d2-pinctrl",
  807. .data = &atmel_sama5d2_pioctrl_data,
  808. }, {
  809. /* sentinel */
  810. }
  811. };
  812. static int atmel_pinctrl_probe(struct platform_device *pdev)
  813. {
  814. struct device *dev = &pdev->dev;
  815. struct pinctrl_pin_desc *pin_desc;
  816. const char **group_names;
  817. const struct of_device_id *match;
  818. int i, ret;
  819. struct resource *res;
  820. struct atmel_pioctrl *atmel_pioctrl;
  821. const struct atmel_pioctrl_data *atmel_pioctrl_data;
  822. atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
  823. if (!atmel_pioctrl)
  824. return -ENOMEM;
  825. atmel_pioctrl->dev = dev;
  826. atmel_pioctrl->node = dev->of_node;
  827. platform_set_drvdata(pdev, atmel_pioctrl);
  828. match = of_match_node(atmel_pctrl_of_match, dev->of_node);
  829. if (!match) {
  830. dev_err(dev, "unknown compatible string\n");
  831. return -ENODEV;
  832. }
  833. atmel_pioctrl_data = match->data;
  834. atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
  835. atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
  836. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  837. atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
  838. if (IS_ERR(atmel_pioctrl->reg_base))
  839. return -EINVAL;
  840. atmel_pioctrl->clk = devm_clk_get(dev, NULL);
  841. if (IS_ERR(atmel_pioctrl->clk)) {
  842. dev_err(dev, "failed to get clock\n");
  843. return PTR_ERR(atmel_pioctrl->clk);
  844. }
  845. atmel_pioctrl->pins = devm_kcalloc(dev,
  846. atmel_pioctrl->npins,
  847. sizeof(*atmel_pioctrl->pins),
  848. GFP_KERNEL);
  849. if (!atmel_pioctrl->pins)
  850. return -ENOMEM;
  851. pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
  852. GFP_KERNEL);
  853. if (!pin_desc)
  854. return -ENOMEM;
  855. atmel_pinctrl_desc.pins = pin_desc;
  856. atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
  857. atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
  858. atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
  859. /* One pin is one group since a pin can achieve all functions. */
  860. group_names = devm_kcalloc(dev,
  861. atmel_pioctrl->npins, sizeof(*group_names),
  862. GFP_KERNEL);
  863. if (!group_names)
  864. return -ENOMEM;
  865. atmel_pioctrl->group_names = group_names;
  866. atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
  867. atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
  868. GFP_KERNEL);
  869. if (!atmel_pioctrl->groups)
  870. return -ENOMEM;
  871. for (i = 0 ; i < atmel_pioctrl->npins; i++) {
  872. struct atmel_group *group = atmel_pioctrl->groups + i;
  873. unsigned bank = ATMEL_PIO_BANK(i);
  874. unsigned line = ATMEL_PIO_LINE(i);
  875. atmel_pioctrl->pins[i] = devm_kzalloc(dev,
  876. sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
  877. if (!atmel_pioctrl->pins[i])
  878. return -ENOMEM;
  879. atmel_pioctrl->pins[i]->pin_id = i;
  880. atmel_pioctrl->pins[i]->bank = bank;
  881. atmel_pioctrl->pins[i]->line = line;
  882. pin_desc[i].number = i;
  883. /* Pin naming convention: P(bank_name)(bank_pin_number). */
  884. pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
  885. bank + 'A', line);
  886. group->name = group_names[i] = pin_desc[i].name;
  887. group->pin = pin_desc[i].number;
  888. dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
  889. }
  890. atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
  891. atmel_pioctrl->gpio_chip->of_node = dev->of_node;
  892. atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
  893. atmel_pioctrl->gpio_chip->label = dev_name(dev);
  894. atmel_pioctrl->gpio_chip->parent = dev;
  895. atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
  896. atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
  897. atmel_pioctrl->nbanks,
  898. sizeof(*atmel_pioctrl->pm_wakeup_sources),
  899. GFP_KERNEL);
  900. if (!atmel_pioctrl->pm_wakeup_sources)
  901. return -ENOMEM;
  902. atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
  903. atmel_pioctrl->nbanks,
  904. sizeof(*atmel_pioctrl->pm_suspend_backup),
  905. GFP_KERNEL);
  906. if (!atmel_pioctrl->pm_suspend_backup)
  907. return -ENOMEM;
  908. atmel_pioctrl->irqs = devm_kcalloc(dev,
  909. atmel_pioctrl->nbanks,
  910. sizeof(*atmel_pioctrl->irqs),
  911. GFP_KERNEL);
  912. if (!atmel_pioctrl->irqs)
  913. return -ENOMEM;
  914. /* There is one controller but each bank has its own irq line. */
  915. for (i = 0; i < atmel_pioctrl->nbanks; i++) {
  916. res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
  917. if (!res) {
  918. dev_err(dev, "missing irq resource for group %c\n",
  919. 'A' + i);
  920. return -EINVAL;
  921. }
  922. atmel_pioctrl->irqs[i] = res->start;
  923. irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
  924. irq_set_handler_data(res->start, atmel_pioctrl);
  925. dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
  926. }
  927. atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
  928. atmel_pioctrl->gpio_chip->ngpio,
  929. &irq_domain_simple_ops, NULL);
  930. if (!atmel_pioctrl->irq_domain) {
  931. dev_err(dev, "can't add the irq domain\n");
  932. return -ENODEV;
  933. }
  934. atmel_pioctrl->irq_domain->name = "atmel gpio";
  935. for (i = 0; i < atmel_pioctrl->npins; i++) {
  936. int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
  937. irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
  938. handle_simple_irq);
  939. irq_set_chip_data(irq, atmel_pioctrl);
  940. dev_dbg(dev,
  941. "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
  942. i, irq);
  943. }
  944. ret = clk_prepare_enable(atmel_pioctrl->clk);
  945. if (ret) {
  946. dev_err(dev, "failed to prepare and enable clock\n");
  947. goto clk_prepare_enable_error;
  948. }
  949. atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
  950. &atmel_pinctrl_desc,
  951. atmel_pioctrl);
  952. if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
  953. ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
  954. dev_err(dev, "pinctrl registration failed\n");
  955. goto clk_unprep;
  956. }
  957. ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
  958. if (ret) {
  959. dev_err(dev, "failed to add gpiochip\n");
  960. goto clk_unprep;
  961. }
  962. ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
  963. 0, 0, atmel_pioctrl->gpio_chip->ngpio);
  964. if (ret) {
  965. dev_err(dev, "failed to add gpio pin range\n");
  966. goto gpiochip_add_pin_range_error;
  967. }
  968. dev_info(&pdev->dev, "atmel pinctrl initialized\n");
  969. return 0;
  970. gpiochip_add_pin_range_error:
  971. gpiochip_remove(atmel_pioctrl->gpio_chip);
  972. clk_unprep:
  973. clk_disable_unprepare(atmel_pioctrl->clk);
  974. clk_prepare_enable_error:
  975. irq_domain_remove(atmel_pioctrl->irq_domain);
  976. return ret;
  977. }
  978. static struct platform_driver atmel_pinctrl_driver = {
  979. .driver = {
  980. .name = "pinctrl-at91-pio4",
  981. .of_match_table = atmel_pctrl_of_match,
  982. .pm = &atmel_pctrl_pm_ops,
  983. .suppress_bind_attrs = true,
  984. },
  985. .probe = atmel_pinctrl_probe,
  986. };
  987. builtin_platform_driver(atmel_pinctrl_driver);