pinctrl-spmi-mpp.c 24 KB

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  1. /*
  2. * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/gpio.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/pinctrl/pinconf-generic.h>
  18. #include <linux/pinctrl/pinconf.h>
  19. #include <linux/pinctrl/pinmux.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/regmap.h>
  22. #include <linux/slab.h>
  23. #include <linux/types.h>
  24. #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
  25. #include "../core.h"
  26. #include "../pinctrl-utils.h"
  27. #define PMIC_MPP_ADDRESS_RANGE 0x100
  28. /*
  29. * Pull Up Values - it indicates whether a pull-up should be
  30. * applied for bidirectional mode only. The hardware ignores the
  31. * configuration when operating in other modes.
  32. */
  33. #define PMIC_MPP_PULL_UP_0P6KOHM 0
  34. #define PMIC_MPP_PULL_UP_10KOHM 1
  35. #define PMIC_MPP_PULL_UP_30KOHM 2
  36. #define PMIC_MPP_PULL_UP_OPEN 3
  37. /* type registers base address bases */
  38. #define PMIC_MPP_REG_TYPE 0x4
  39. #define PMIC_MPP_REG_SUBTYPE 0x5
  40. /* mpp peripheral type and subtype values */
  41. #define PMIC_MPP_TYPE 0x11
  42. #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3
  43. #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4
  44. #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5
  45. #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6
  46. #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7
  47. #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf
  48. #define PMIC_MPP_REG_RT_STS 0x10
  49. #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
  50. /* control register base address bases */
  51. #define PMIC_MPP_REG_MODE_CTL 0x40
  52. #define PMIC_MPP_REG_DIG_VIN_CTL 0x41
  53. #define PMIC_MPP_REG_DIG_PULL_CTL 0x42
  54. #define PMIC_MPP_REG_DIG_IN_CTL 0x43
  55. #define PMIC_MPP_REG_EN_CTL 0x46
  56. #define PMIC_MPP_REG_AOUT_CTL 0x48
  57. #define PMIC_MPP_REG_AIN_CTL 0x4a
  58. #define PMIC_MPP_REG_SINK_CTL 0x4c
  59. /* PMIC_MPP_REG_MODE_CTL */
  60. #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1
  61. #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1
  62. #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7
  63. #define PMIC_MPP_REG_MODE_DIR_SHIFT 4
  64. #define PMIC_MPP_REG_MODE_DIR_MASK 0x7
  65. /* PMIC_MPP_REG_DIG_VIN_CTL */
  66. #define PMIC_MPP_REG_VIN_SHIFT 0
  67. #define PMIC_MPP_REG_VIN_MASK 0x7
  68. /* PMIC_MPP_REG_DIG_PULL_CTL */
  69. #define PMIC_MPP_REG_PULL_SHIFT 0
  70. #define PMIC_MPP_REG_PULL_MASK 0x7
  71. /* PMIC_MPP_REG_EN_CTL */
  72. #define PMIC_MPP_REG_MASTER_EN_SHIFT 7
  73. /* PMIC_MPP_REG_AIN_CTL */
  74. #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0
  75. #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7
  76. #define PMIC_MPP_MODE_DIGITAL_INPUT 0
  77. #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1
  78. #define PMIC_MPP_MODE_DIGITAL_BIDIR 2
  79. #define PMIC_MPP_MODE_ANALOG_BIDIR 3
  80. #define PMIC_MPP_MODE_ANALOG_INPUT 4
  81. #define PMIC_MPP_MODE_ANALOG_OUTPUT 5
  82. #define PMIC_MPP_MODE_CURRENT_SINK 6
  83. #define PMIC_MPP_SELECTOR_NORMAL 0
  84. #define PMIC_MPP_SELECTOR_PAIRED 1
  85. #define PMIC_MPP_SELECTOR_DTEST_FIRST 4
  86. #define PMIC_MPP_PHYSICAL_OFFSET 1
  87. /* Qualcomm specific pin configurations */
  88. #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1)
  89. #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2)
  90. #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3)
  91. #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4)
  92. /**
  93. * struct pmic_mpp_pad - keep current MPP settings
  94. * @base: Address base in SPMI device.
  95. * @irq: IRQ number which this MPP generate.
  96. * @is_enabled: Set to false when MPP should be put in high Z state.
  97. * @out_value: Cached pin output value.
  98. * @output_enabled: Set to true if MPP output logic is enabled.
  99. * @input_enabled: Set to true if MPP input buffer logic is enabled.
  100. * @paired: Pin operates in paired mode
  101. * @has_pullup: Pin has support to configure pullup
  102. * @num_sources: Number of power-sources supported by this MPP.
  103. * @power_source: Current power-source used.
  104. * @amux_input: Set the source for analog input.
  105. * @aout_level: Analog output level
  106. * @pullup: Pullup resistor value. Valid in Bidirectional mode only.
  107. * @function: See pmic_mpp_functions[].
  108. * @drive_strength: Amount of current in sink mode
  109. * @dtest: DTEST route selector
  110. */
  111. struct pmic_mpp_pad {
  112. u16 base;
  113. int irq;
  114. bool is_enabled;
  115. bool out_value;
  116. bool output_enabled;
  117. bool input_enabled;
  118. bool paired;
  119. bool has_pullup;
  120. unsigned int num_sources;
  121. unsigned int power_source;
  122. unsigned int amux_input;
  123. unsigned int aout_level;
  124. unsigned int pullup;
  125. unsigned int function;
  126. unsigned int drive_strength;
  127. unsigned int dtest;
  128. };
  129. struct pmic_mpp_state {
  130. struct device *dev;
  131. struct regmap *map;
  132. struct pinctrl_dev *ctrl;
  133. struct gpio_chip chip;
  134. };
  135. static const struct pinconf_generic_params pmic_mpp_bindings[] = {
  136. {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0},
  137. {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0},
  138. {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0},
  139. {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0},
  140. };
  141. #ifdef CONFIG_DEBUG_FS
  142. static const struct pin_config_item pmic_conf_items[] = {
  143. PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true),
  144. PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true),
  145. PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true),
  146. PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false),
  147. };
  148. #endif
  149. static const char *const pmic_mpp_groups[] = {
  150. "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
  151. };
  152. #define PMIC_MPP_DIGITAL 0
  153. #define PMIC_MPP_ANALOG 1
  154. #define PMIC_MPP_SINK 2
  155. static const char *const pmic_mpp_functions[] = {
  156. "digital", "analog", "sink"
  157. };
  158. static int pmic_mpp_read(struct pmic_mpp_state *state,
  159. struct pmic_mpp_pad *pad, unsigned int addr)
  160. {
  161. unsigned int val;
  162. int ret;
  163. ret = regmap_read(state->map, pad->base + addr, &val);
  164. if (ret < 0)
  165. dev_err(state->dev, "read 0x%x failed\n", addr);
  166. else
  167. ret = val;
  168. return ret;
  169. }
  170. static int pmic_mpp_write(struct pmic_mpp_state *state,
  171. struct pmic_mpp_pad *pad, unsigned int addr,
  172. unsigned int val)
  173. {
  174. int ret;
  175. ret = regmap_write(state->map, pad->base + addr, val);
  176. if (ret < 0)
  177. dev_err(state->dev, "write 0x%x failed\n", addr);
  178. return ret;
  179. }
  180. static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev)
  181. {
  182. /* Every PIN is a group */
  183. return pctldev->desc->npins;
  184. }
  185. static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev,
  186. unsigned pin)
  187. {
  188. return pctldev->desc->pins[pin].name;
  189. }
  190. static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev,
  191. unsigned pin,
  192. const unsigned **pins, unsigned *num_pins)
  193. {
  194. *pins = &pctldev->desc->pins[pin].number;
  195. *num_pins = 1;
  196. return 0;
  197. }
  198. static const struct pinctrl_ops pmic_mpp_pinctrl_ops = {
  199. .get_groups_count = pmic_mpp_get_groups_count,
  200. .get_group_name = pmic_mpp_get_group_name,
  201. .get_group_pins = pmic_mpp_get_group_pins,
  202. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  203. .dt_free_map = pinctrl_utils_free_map,
  204. };
  205. static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev)
  206. {
  207. return ARRAY_SIZE(pmic_mpp_functions);
  208. }
  209. static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev,
  210. unsigned function)
  211. {
  212. return pmic_mpp_functions[function];
  213. }
  214. static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev,
  215. unsigned function,
  216. const char *const **groups,
  217. unsigned *const num_qgroups)
  218. {
  219. *groups = pmic_mpp_groups;
  220. *num_qgroups = pctldev->desc->npins;
  221. return 0;
  222. }
  223. static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state,
  224. struct pmic_mpp_pad *pad)
  225. {
  226. unsigned int mode;
  227. unsigned int sel;
  228. unsigned int val;
  229. unsigned int en;
  230. switch (pad->function) {
  231. case PMIC_MPP_ANALOG:
  232. if (pad->input_enabled && pad->output_enabled)
  233. mode = PMIC_MPP_MODE_ANALOG_BIDIR;
  234. else if (pad->input_enabled)
  235. mode = PMIC_MPP_MODE_ANALOG_INPUT;
  236. else
  237. mode = PMIC_MPP_MODE_ANALOG_OUTPUT;
  238. break;
  239. case PMIC_MPP_DIGITAL:
  240. if (pad->input_enabled && pad->output_enabled)
  241. mode = PMIC_MPP_MODE_DIGITAL_BIDIR;
  242. else if (pad->input_enabled)
  243. mode = PMIC_MPP_MODE_DIGITAL_INPUT;
  244. else
  245. mode = PMIC_MPP_MODE_DIGITAL_OUTPUT;
  246. break;
  247. case PMIC_MPP_SINK:
  248. default:
  249. mode = PMIC_MPP_MODE_CURRENT_SINK;
  250. break;
  251. }
  252. if (pad->dtest)
  253. sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1;
  254. else if (pad->paired)
  255. sel = PMIC_MPP_SELECTOR_PAIRED;
  256. else
  257. sel = PMIC_MPP_SELECTOR_NORMAL;
  258. en = !!pad->out_value;
  259. val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT |
  260. sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT |
  261. en;
  262. return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
  263. }
  264. static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
  265. unsigned pin)
  266. {
  267. struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
  268. struct pmic_mpp_pad *pad;
  269. unsigned int val;
  270. int ret;
  271. pad = pctldev->desc->pins[pin].drv_data;
  272. pad->function = function;
  273. ret = pmic_mpp_write_mode_ctl(state, pad);
  274. if (ret < 0)
  275. return ret;
  276. val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
  277. return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
  278. }
  279. static const struct pinmux_ops pmic_mpp_pinmux_ops = {
  280. .get_functions_count = pmic_mpp_get_functions_count,
  281. .get_function_name = pmic_mpp_get_function_name,
  282. .get_function_groups = pmic_mpp_get_function_groups,
  283. .set_mux = pmic_mpp_set_mux,
  284. };
  285. static int pmic_mpp_config_get(struct pinctrl_dev *pctldev,
  286. unsigned int pin, unsigned long *config)
  287. {
  288. unsigned param = pinconf_to_config_param(*config);
  289. struct pmic_mpp_pad *pad;
  290. unsigned arg = 0;
  291. pad = pctldev->desc->pins[pin].drv_data;
  292. switch (param) {
  293. case PIN_CONFIG_BIAS_DISABLE:
  294. if (pad->pullup != PMIC_MPP_PULL_UP_OPEN)
  295. return -EINVAL;
  296. arg = 1;
  297. break;
  298. case PIN_CONFIG_BIAS_PULL_UP:
  299. switch (pad->pullup) {
  300. case PMIC_MPP_PULL_UP_0P6KOHM:
  301. arg = 600;
  302. break;
  303. case PMIC_MPP_PULL_UP_10KOHM:
  304. arg = 10000;
  305. break;
  306. case PMIC_MPP_PULL_UP_30KOHM:
  307. arg = 30000;
  308. break;
  309. default:
  310. return -EINVAL;
  311. }
  312. break;
  313. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  314. if (pad->is_enabled)
  315. return -EINVAL;
  316. arg = 1;
  317. break;
  318. case PIN_CONFIG_POWER_SOURCE:
  319. arg = pad->power_source;
  320. break;
  321. case PIN_CONFIG_INPUT_ENABLE:
  322. if (!pad->input_enabled)
  323. return -EINVAL;
  324. arg = 1;
  325. break;
  326. case PIN_CONFIG_OUTPUT:
  327. arg = pad->out_value;
  328. break;
  329. case PMIC_MPP_CONF_DTEST_SELECTOR:
  330. arg = pad->dtest;
  331. break;
  332. case PMIC_MPP_CONF_AMUX_ROUTE:
  333. arg = pad->amux_input;
  334. break;
  335. case PMIC_MPP_CONF_PAIRED:
  336. if (!pad->paired)
  337. return -EINVAL;
  338. arg = 1;
  339. break;
  340. case PIN_CONFIG_DRIVE_STRENGTH:
  341. arg = pad->drive_strength;
  342. break;
  343. case PMIC_MPP_CONF_ANALOG_LEVEL:
  344. arg = pad->aout_level;
  345. break;
  346. default:
  347. return -EINVAL;
  348. }
  349. /* Convert register value to pinconf value */
  350. *config = pinconf_to_config_packed(param, arg);
  351. return 0;
  352. }
  353. static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
  354. unsigned long *configs, unsigned nconfs)
  355. {
  356. struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
  357. struct pmic_mpp_pad *pad;
  358. unsigned param, arg;
  359. unsigned int val;
  360. int i, ret;
  361. pad = pctldev->desc->pins[pin].drv_data;
  362. /* Make it possible to enable the pin, by not setting high impedance */
  363. pad->is_enabled = true;
  364. for (i = 0; i < nconfs; i++) {
  365. param = pinconf_to_config_param(configs[i]);
  366. arg = pinconf_to_config_argument(configs[i]);
  367. switch (param) {
  368. case PIN_CONFIG_BIAS_DISABLE:
  369. pad->pullup = PMIC_MPP_PULL_UP_OPEN;
  370. break;
  371. case PIN_CONFIG_BIAS_PULL_UP:
  372. switch (arg) {
  373. case 600:
  374. pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM;
  375. break;
  376. case 10000:
  377. pad->pullup = PMIC_MPP_PULL_UP_10KOHM;
  378. break;
  379. case 30000:
  380. pad->pullup = PMIC_MPP_PULL_UP_30KOHM;
  381. break;
  382. default:
  383. return -EINVAL;
  384. }
  385. break;
  386. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  387. pad->is_enabled = false;
  388. break;
  389. case PIN_CONFIG_POWER_SOURCE:
  390. if (arg >= pad->num_sources)
  391. return -EINVAL;
  392. pad->power_source = arg;
  393. break;
  394. case PIN_CONFIG_INPUT_ENABLE:
  395. pad->input_enabled = arg ? true : false;
  396. break;
  397. case PIN_CONFIG_OUTPUT:
  398. pad->output_enabled = true;
  399. pad->out_value = arg;
  400. break;
  401. case PMIC_MPP_CONF_DTEST_SELECTOR:
  402. pad->dtest = arg;
  403. break;
  404. case PIN_CONFIG_DRIVE_STRENGTH:
  405. pad->drive_strength = arg;
  406. break;
  407. case PMIC_MPP_CONF_AMUX_ROUTE:
  408. if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4)
  409. return -EINVAL;
  410. pad->amux_input = arg;
  411. break;
  412. case PMIC_MPP_CONF_ANALOG_LEVEL:
  413. pad->aout_level = arg;
  414. break;
  415. case PMIC_MPP_CONF_PAIRED:
  416. pad->paired = !!arg;
  417. break;
  418. default:
  419. return -EINVAL;
  420. }
  421. }
  422. val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT;
  423. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val);
  424. if (ret < 0)
  425. return ret;
  426. if (pad->has_pullup) {
  427. val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
  428. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL,
  429. val);
  430. if (ret < 0)
  431. return ret;
  432. }
  433. val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK;
  434. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val);
  435. if (ret < 0)
  436. return ret;
  437. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level);
  438. if (ret < 0)
  439. return ret;
  440. ret = pmic_mpp_write_mode_ctl(state, pad);
  441. if (ret < 0)
  442. return ret;
  443. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_SINK_CTL, pad->drive_strength);
  444. if (ret < 0)
  445. return ret;
  446. val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
  447. return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
  448. }
  449. static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
  450. struct seq_file *s, unsigned pin)
  451. {
  452. struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
  453. struct pmic_mpp_pad *pad;
  454. int ret;
  455. static const char *const biases[] = {
  456. "0.6kOhm", "10kOhm", "30kOhm", "Disabled"
  457. };
  458. pad = pctldev->desc->pins[pin].drv_data;
  459. seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET);
  460. if (!pad->is_enabled) {
  461. seq_puts(s, " ---");
  462. } else {
  463. if (pad->input_enabled) {
  464. ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
  465. if (ret < 0)
  466. return;
  467. ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
  468. pad->out_value = ret;
  469. }
  470. seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
  471. seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
  472. seq_printf(s, " vin-%d", pad->power_source);
  473. seq_printf(s, " %d", pad->aout_level);
  474. if (pad->has_pullup)
  475. seq_printf(s, " %-8s", biases[pad->pullup]);
  476. seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
  477. if (pad->dtest)
  478. seq_printf(s, " dtest%d", pad->dtest);
  479. if (pad->paired)
  480. seq_puts(s, " paired");
  481. }
  482. }
  483. static const struct pinconf_ops pmic_mpp_pinconf_ops = {
  484. .is_generic = true,
  485. .pin_config_group_get = pmic_mpp_config_get,
  486. .pin_config_group_set = pmic_mpp_config_set,
  487. .pin_config_group_dbg_show = pmic_mpp_config_dbg_show,
  488. };
  489. static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin)
  490. {
  491. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  492. unsigned long config;
  493. config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
  494. return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
  495. }
  496. static int pmic_mpp_direction_output(struct gpio_chip *chip,
  497. unsigned pin, int val)
  498. {
  499. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  500. unsigned long config;
  501. config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
  502. return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
  503. }
  504. static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin)
  505. {
  506. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  507. struct pmic_mpp_pad *pad;
  508. int ret;
  509. pad = state->ctrl->desc->pins[pin].drv_data;
  510. if (pad->input_enabled) {
  511. ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
  512. if (ret < 0)
  513. return ret;
  514. pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
  515. }
  516. return !!pad->out_value;
  517. }
  518. static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value)
  519. {
  520. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  521. unsigned long config;
  522. config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
  523. pmic_mpp_config_set(state->ctrl, pin, &config, 1);
  524. }
  525. static int pmic_mpp_of_xlate(struct gpio_chip *chip,
  526. const struct of_phandle_args *gpio_desc,
  527. u32 *flags)
  528. {
  529. if (chip->of_gpio_n_cells < 2)
  530. return -EINVAL;
  531. if (flags)
  532. *flags = gpio_desc->args[1];
  533. return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET;
  534. }
  535. static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin)
  536. {
  537. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  538. struct pmic_mpp_pad *pad;
  539. pad = state->ctrl->desc->pins[pin].drv_data;
  540. return pad->irq;
  541. }
  542. static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  543. {
  544. struct pmic_mpp_state *state = gpiochip_get_data(chip);
  545. unsigned i;
  546. for (i = 0; i < chip->ngpio; i++) {
  547. pmic_mpp_config_dbg_show(state->ctrl, s, i);
  548. seq_puts(s, "\n");
  549. }
  550. }
  551. static const struct gpio_chip pmic_mpp_gpio_template = {
  552. .direction_input = pmic_mpp_direction_input,
  553. .direction_output = pmic_mpp_direction_output,
  554. .get = pmic_mpp_get,
  555. .set = pmic_mpp_set,
  556. .request = gpiochip_generic_request,
  557. .free = gpiochip_generic_free,
  558. .of_xlate = pmic_mpp_of_xlate,
  559. .to_irq = pmic_mpp_to_irq,
  560. .dbg_show = pmic_mpp_dbg_show,
  561. };
  562. static int pmic_mpp_populate(struct pmic_mpp_state *state,
  563. struct pmic_mpp_pad *pad)
  564. {
  565. int type, subtype, val, dir;
  566. unsigned int sel;
  567. type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE);
  568. if (type < 0)
  569. return type;
  570. if (type != PMIC_MPP_TYPE) {
  571. dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
  572. type, pad->base);
  573. return -ENODEV;
  574. }
  575. subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE);
  576. if (subtype < 0)
  577. return subtype;
  578. switch (subtype) {
  579. case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT:
  580. case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT:
  581. case PMIC_MPP_SUBTYPE_4CH_NO_SINK:
  582. case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK:
  583. case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC:
  584. pad->num_sources = 4;
  585. break;
  586. case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC:
  587. pad->num_sources = 8;
  588. break;
  589. default:
  590. dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n",
  591. subtype, pad->base);
  592. return -ENODEV;
  593. }
  594. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL);
  595. if (val < 0)
  596. return val;
  597. pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK;
  598. dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT;
  599. dir &= PMIC_MPP_REG_MODE_DIR_MASK;
  600. switch (dir) {
  601. case PMIC_MPP_MODE_DIGITAL_INPUT:
  602. pad->input_enabled = true;
  603. pad->output_enabled = false;
  604. pad->function = PMIC_MPP_DIGITAL;
  605. break;
  606. case PMIC_MPP_MODE_DIGITAL_OUTPUT:
  607. pad->input_enabled = false;
  608. pad->output_enabled = true;
  609. pad->function = PMIC_MPP_DIGITAL;
  610. break;
  611. case PMIC_MPP_MODE_DIGITAL_BIDIR:
  612. pad->input_enabled = true;
  613. pad->output_enabled = true;
  614. pad->function = PMIC_MPP_DIGITAL;
  615. break;
  616. case PMIC_MPP_MODE_ANALOG_BIDIR:
  617. pad->input_enabled = true;
  618. pad->output_enabled = true;
  619. pad->function = PMIC_MPP_ANALOG;
  620. break;
  621. case PMIC_MPP_MODE_ANALOG_INPUT:
  622. pad->input_enabled = true;
  623. pad->output_enabled = false;
  624. pad->function = PMIC_MPP_ANALOG;
  625. break;
  626. case PMIC_MPP_MODE_ANALOG_OUTPUT:
  627. pad->input_enabled = false;
  628. pad->output_enabled = true;
  629. pad->function = PMIC_MPP_ANALOG;
  630. break;
  631. case PMIC_MPP_MODE_CURRENT_SINK:
  632. pad->input_enabled = false;
  633. pad->output_enabled = true;
  634. pad->function = PMIC_MPP_SINK;
  635. break;
  636. default:
  637. dev_err(state->dev, "unknown MPP direction\n");
  638. return -ENODEV;
  639. }
  640. sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
  641. sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK;
  642. if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST)
  643. pad->dtest = sel + 1;
  644. else if (sel == PMIC_MPP_SELECTOR_PAIRED)
  645. pad->paired = true;
  646. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL);
  647. if (val < 0)
  648. return val;
  649. pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT;
  650. pad->power_source &= PMIC_MPP_REG_VIN_MASK;
  651. if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT &&
  652. subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) {
  653. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
  654. if (val < 0)
  655. return val;
  656. pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
  657. pad->pullup &= PMIC_MPP_REG_PULL_MASK;
  658. pad->has_pullup = true;
  659. }
  660. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
  661. if (val < 0)
  662. return val;
  663. pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT;
  664. pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK;
  665. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL);
  666. if (val < 0)
  667. return val;
  668. pad->drive_strength = val;
  669. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL);
  670. if (val < 0)
  671. return val;
  672. pad->aout_level = val;
  673. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
  674. if (val < 0)
  675. return val;
  676. pad->is_enabled = !!val;
  677. return 0;
  678. }
  679. static int pmic_mpp_probe(struct platform_device *pdev)
  680. {
  681. struct device *dev = &pdev->dev;
  682. struct pinctrl_pin_desc *pindesc;
  683. struct pinctrl_desc *pctrldesc;
  684. struct pmic_mpp_pad *pad, *pads;
  685. struct pmic_mpp_state *state;
  686. int ret, npins, i;
  687. u32 reg;
  688. ret = of_property_read_u32(dev->of_node, "reg", &reg);
  689. if (ret < 0) {
  690. dev_err(dev, "missing base address");
  691. return ret;
  692. }
  693. npins = platform_irq_count(pdev);
  694. if (!npins)
  695. return -EINVAL;
  696. if (npins < 0)
  697. return npins;
  698. BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups));
  699. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  700. if (!state)
  701. return -ENOMEM;
  702. platform_set_drvdata(pdev, state);
  703. state->dev = &pdev->dev;
  704. state->map = dev_get_regmap(dev->parent, NULL);
  705. pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
  706. if (!pindesc)
  707. return -ENOMEM;
  708. pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
  709. if (!pads)
  710. return -ENOMEM;
  711. pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
  712. if (!pctrldesc)
  713. return -ENOMEM;
  714. pctrldesc->pctlops = &pmic_mpp_pinctrl_ops;
  715. pctrldesc->pmxops = &pmic_mpp_pinmux_ops;
  716. pctrldesc->confops = &pmic_mpp_pinconf_ops;
  717. pctrldesc->owner = THIS_MODULE;
  718. pctrldesc->name = dev_name(dev);
  719. pctrldesc->pins = pindesc;
  720. pctrldesc->npins = npins;
  721. pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings);
  722. pctrldesc->custom_params = pmic_mpp_bindings;
  723. #ifdef CONFIG_DEBUG_FS
  724. pctrldesc->custom_conf_items = pmic_conf_items;
  725. #endif
  726. for (i = 0; i < npins; i++, pindesc++) {
  727. pad = &pads[i];
  728. pindesc->drv_data = pad;
  729. pindesc->number = i;
  730. pindesc->name = pmic_mpp_groups[i];
  731. pad->irq = platform_get_irq(pdev, i);
  732. if (pad->irq < 0)
  733. return pad->irq;
  734. pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE;
  735. ret = pmic_mpp_populate(state, pad);
  736. if (ret < 0)
  737. return ret;
  738. }
  739. state->chip = pmic_mpp_gpio_template;
  740. state->chip.parent = dev;
  741. state->chip.base = -1;
  742. state->chip.ngpio = npins;
  743. state->chip.label = dev_name(dev);
  744. state->chip.of_gpio_n_cells = 2;
  745. state->chip.can_sleep = false;
  746. state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
  747. if (IS_ERR(state->ctrl))
  748. return PTR_ERR(state->ctrl);
  749. ret = gpiochip_add_data(&state->chip, state);
  750. if (ret) {
  751. dev_err(state->dev, "can't add gpio chip\n");
  752. return ret;
  753. }
  754. ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
  755. if (ret) {
  756. dev_err(dev, "failed to add pin range\n");
  757. goto err_range;
  758. }
  759. return 0;
  760. err_range:
  761. gpiochip_remove(&state->chip);
  762. return ret;
  763. }
  764. static int pmic_mpp_remove(struct platform_device *pdev)
  765. {
  766. struct pmic_mpp_state *state = platform_get_drvdata(pdev);
  767. gpiochip_remove(&state->chip);
  768. return 0;
  769. }
  770. static const struct of_device_id pmic_mpp_of_match[] = {
  771. { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
  772. { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
  773. { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */
  774. { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */
  775. { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */
  776. { .compatible = "qcom,spmi-mpp" }, /* Generic */
  777. { },
  778. };
  779. MODULE_DEVICE_TABLE(of, pmic_mpp_of_match);
  780. static struct platform_driver pmic_mpp_driver = {
  781. .driver = {
  782. .name = "qcom-spmi-mpp",
  783. .of_match_table = pmic_mpp_of_match,
  784. },
  785. .probe = pmic_mpp_probe,
  786. .remove = pmic_mpp_remove,
  787. };
  788. module_platform_driver(pmic_mpp_driver);
  789. MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
  790. MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver");
  791. MODULE_ALIAS("platform:qcom-spmi-mpp");
  792. MODULE_LICENSE("GPL v2");