qla_isr.c 98 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691
  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/cpu.h>
  12. #include <linux/t10-pi.h>
  13. #include <scsi/scsi_tcq.h>
  14. #include <scsi/scsi_bsg_fc.h>
  15. #include <scsi/scsi_eh.h>
  16. #include <scsi/fc/fc_fs.h>
  17. #include <linux/nvme-fc-driver.h>
  18. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  19. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  20. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  21. static int qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  22. sts_entry_t *);
  23. /**
  24. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  25. * @irq:
  26. * @dev_id: SCSI driver HA context
  27. *
  28. * Called by system whenever the host adapter generates an interrupt.
  29. *
  30. * Returns handled flag.
  31. */
  32. irqreturn_t
  33. qla2100_intr_handler(int irq, void *dev_id)
  34. {
  35. scsi_qla_host_t *vha;
  36. struct qla_hw_data *ha;
  37. struct device_reg_2xxx __iomem *reg;
  38. int status;
  39. unsigned long iter;
  40. uint16_t hccr;
  41. uint16_t mb[4];
  42. struct rsp_que *rsp;
  43. unsigned long flags;
  44. rsp = (struct rsp_que *) dev_id;
  45. if (!rsp) {
  46. ql_log(ql_log_info, NULL, 0x505d,
  47. "%s: NULL response queue pointer.\n", __func__);
  48. return (IRQ_NONE);
  49. }
  50. ha = rsp->hw;
  51. reg = &ha->iobase->isp;
  52. status = 0;
  53. spin_lock_irqsave(&ha->hardware_lock, flags);
  54. vha = pci_get_drvdata(ha->pdev);
  55. for (iter = 50; iter--; ) {
  56. hccr = RD_REG_WORD(&reg->hccr);
  57. if (qla2x00_check_reg16_for_disconnect(vha, hccr))
  58. break;
  59. if (hccr & HCCR_RISC_PAUSE) {
  60. if (pci_channel_offline(ha->pdev))
  61. break;
  62. /*
  63. * Issue a "HARD" reset in order for the RISC interrupt
  64. * bit to be cleared. Schedule a big hammer to get
  65. * out of the RISC PAUSED state.
  66. */
  67. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  68. RD_REG_WORD(&reg->hccr);
  69. ha->isp_ops->fw_dump(vha, 1);
  70. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  71. break;
  72. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  73. break;
  74. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  75. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  76. RD_REG_WORD(&reg->hccr);
  77. /* Get mailbox data. */
  78. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  79. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  80. qla2x00_mbx_completion(vha, mb[0]);
  81. status |= MBX_INTERRUPT;
  82. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  83. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  84. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  85. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  86. qla2x00_async_event(vha, rsp, mb);
  87. } else {
  88. /*EMPTY*/
  89. ql_dbg(ql_dbg_async, vha, 0x5025,
  90. "Unrecognized interrupt type (%d).\n",
  91. mb[0]);
  92. }
  93. /* Release mailbox registers. */
  94. WRT_REG_WORD(&reg->semaphore, 0);
  95. RD_REG_WORD(&reg->semaphore);
  96. } else {
  97. qla2x00_process_response_queue(rsp);
  98. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  99. RD_REG_WORD(&reg->hccr);
  100. }
  101. }
  102. qla2x00_handle_mbx_completion(ha, status);
  103. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  104. return (IRQ_HANDLED);
  105. }
  106. bool
  107. qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *vha, uint32_t reg)
  108. {
  109. /* Check for PCI disconnection */
  110. if (reg == 0xffffffff && !pci_channel_offline(vha->hw->pdev)) {
  111. if (!test_and_set_bit(PFLG_DISCONNECTED, &vha->pci_flags) &&
  112. !test_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags) &&
  113. !test_bit(PFLG_DRIVER_PROBING, &vha->pci_flags)) {
  114. /*
  115. * Schedule this (only once) on the default system
  116. * workqueue so that all the adapter workqueues and the
  117. * DPC thread can be shutdown cleanly.
  118. */
  119. schedule_work(&vha->hw->board_disable);
  120. }
  121. return true;
  122. } else
  123. return false;
  124. }
  125. bool
  126. qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *vha, uint16_t reg)
  127. {
  128. return qla2x00_check_reg32_for_disconnect(vha, 0xffff0000 | reg);
  129. }
  130. /**
  131. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  132. * @irq:
  133. * @dev_id: SCSI driver HA context
  134. *
  135. * Called by system whenever the host adapter generates an interrupt.
  136. *
  137. * Returns handled flag.
  138. */
  139. irqreturn_t
  140. qla2300_intr_handler(int irq, void *dev_id)
  141. {
  142. scsi_qla_host_t *vha;
  143. struct device_reg_2xxx __iomem *reg;
  144. int status;
  145. unsigned long iter;
  146. uint32_t stat;
  147. uint16_t hccr;
  148. uint16_t mb[4];
  149. struct rsp_que *rsp;
  150. struct qla_hw_data *ha;
  151. unsigned long flags;
  152. rsp = (struct rsp_que *) dev_id;
  153. if (!rsp) {
  154. ql_log(ql_log_info, NULL, 0x5058,
  155. "%s: NULL response queue pointer.\n", __func__);
  156. return (IRQ_NONE);
  157. }
  158. ha = rsp->hw;
  159. reg = &ha->iobase->isp;
  160. status = 0;
  161. spin_lock_irqsave(&ha->hardware_lock, flags);
  162. vha = pci_get_drvdata(ha->pdev);
  163. for (iter = 50; iter--; ) {
  164. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  165. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  166. break;
  167. if (stat & HSR_RISC_PAUSED) {
  168. if (unlikely(pci_channel_offline(ha->pdev)))
  169. break;
  170. hccr = RD_REG_WORD(&reg->hccr);
  171. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  172. ql_log(ql_log_warn, vha, 0x5026,
  173. "Parity error -- HCCR=%x, Dumping "
  174. "firmware.\n", hccr);
  175. else
  176. ql_log(ql_log_warn, vha, 0x5027,
  177. "RISC paused -- HCCR=%x, Dumping "
  178. "firmware.\n", hccr);
  179. /*
  180. * Issue a "HARD" reset in order for the RISC
  181. * interrupt bit to be cleared. Schedule a big
  182. * hammer to get out of the RISC PAUSED state.
  183. */
  184. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  185. RD_REG_WORD(&reg->hccr);
  186. ha->isp_ops->fw_dump(vha, 1);
  187. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  188. break;
  189. } else if ((stat & HSR_RISC_INT) == 0)
  190. break;
  191. switch (stat & 0xff) {
  192. case 0x1:
  193. case 0x2:
  194. case 0x10:
  195. case 0x11:
  196. qla2x00_mbx_completion(vha, MSW(stat));
  197. status |= MBX_INTERRUPT;
  198. /* Release mailbox registers. */
  199. WRT_REG_WORD(&reg->semaphore, 0);
  200. break;
  201. case 0x12:
  202. mb[0] = MSW(stat);
  203. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  204. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  205. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  206. qla2x00_async_event(vha, rsp, mb);
  207. break;
  208. case 0x13:
  209. qla2x00_process_response_queue(rsp);
  210. break;
  211. case 0x15:
  212. mb[0] = MBA_CMPLT_1_16BIT;
  213. mb[1] = MSW(stat);
  214. qla2x00_async_event(vha, rsp, mb);
  215. break;
  216. case 0x16:
  217. mb[0] = MBA_SCSI_COMPLETION;
  218. mb[1] = MSW(stat);
  219. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  220. qla2x00_async_event(vha, rsp, mb);
  221. break;
  222. default:
  223. ql_dbg(ql_dbg_async, vha, 0x5028,
  224. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  225. break;
  226. }
  227. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  228. RD_REG_WORD_RELAXED(&reg->hccr);
  229. }
  230. qla2x00_handle_mbx_completion(ha, status);
  231. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  232. return (IRQ_HANDLED);
  233. }
  234. /**
  235. * qla2x00_mbx_completion() - Process mailbox command completions.
  236. * @vha: SCSI driver HA context
  237. * @mb0: Mailbox0 register
  238. */
  239. static void
  240. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  241. {
  242. uint16_t cnt;
  243. uint32_t mboxes;
  244. uint16_t __iomem *wptr;
  245. struct qla_hw_data *ha = vha->hw;
  246. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  247. /* Read all mbox registers? */
  248. WARN_ON_ONCE(ha->mbx_count > 32);
  249. mboxes = (1ULL << ha->mbx_count) - 1;
  250. if (!ha->mcp)
  251. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  252. else
  253. mboxes = ha->mcp->in_mb;
  254. /* Load return mailbox registers. */
  255. ha->flags.mbox_int = 1;
  256. ha->mailbox_out[0] = mb0;
  257. mboxes >>= 1;
  258. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  259. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  260. if (IS_QLA2200(ha) && cnt == 8)
  261. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  262. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  263. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  264. else if (mboxes & BIT_0)
  265. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  266. wptr++;
  267. mboxes >>= 1;
  268. }
  269. }
  270. static void
  271. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  272. {
  273. static char *event[] =
  274. { "Complete", "Request Notification", "Time Extension" };
  275. int rval;
  276. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  277. struct device_reg_82xx __iomem *reg82 = &vha->hw->iobase->isp82;
  278. uint16_t __iomem *wptr;
  279. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  280. /* Seed data -- mailbox1 -> mailbox7. */
  281. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  282. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  283. else if (IS_QLA8044(vha->hw))
  284. wptr = (uint16_t __iomem *)&reg82->mailbox_out[1];
  285. else
  286. return;
  287. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  288. mb[cnt] = RD_REG_WORD(wptr);
  289. ql_dbg(ql_dbg_async, vha, 0x5021,
  290. "Inter-Driver Communication %s -- "
  291. "%04x %04x %04x %04x %04x %04x %04x.\n",
  292. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  293. mb[4], mb[5], mb[6]);
  294. switch (aen) {
  295. /* Handle IDC Error completion case. */
  296. case MBA_IDC_COMPLETE:
  297. if (mb[1] >> 15) {
  298. vha->hw->flags.idc_compl_status = 1;
  299. if (vha->hw->notify_dcbx_comp && !vha->vp_idx)
  300. complete(&vha->hw->dcbx_comp);
  301. }
  302. break;
  303. case MBA_IDC_NOTIFY:
  304. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  305. timeout = (descr >> 8) & 0xf;
  306. ql_dbg(ql_dbg_async, vha, 0x5022,
  307. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  308. vha->host_no, event[aen & 0xff], timeout);
  309. if (!timeout)
  310. return;
  311. rval = qla2x00_post_idc_ack_work(vha, mb);
  312. if (rval != QLA_SUCCESS)
  313. ql_log(ql_log_warn, vha, 0x5023,
  314. "IDC failed to post ACK.\n");
  315. break;
  316. case MBA_IDC_TIME_EXT:
  317. vha->hw->idc_extend_tmo = descr;
  318. ql_dbg(ql_dbg_async, vha, 0x5087,
  319. "%lu Inter-Driver Communication %s -- "
  320. "Extend timeout by=%d.\n",
  321. vha->host_no, event[aen & 0xff], vha->hw->idc_extend_tmo);
  322. break;
  323. }
  324. }
  325. #define LS_UNKNOWN 2
  326. const char *
  327. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  328. {
  329. static const char *const link_speeds[] = {
  330. "1", "2", "?", "4", "8", "16", "32", "10"
  331. };
  332. #define QLA_LAST_SPEED 7
  333. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  334. return link_speeds[0];
  335. else if (speed == 0x13)
  336. return link_speeds[QLA_LAST_SPEED];
  337. else if (speed < QLA_LAST_SPEED)
  338. return link_speeds[speed];
  339. else
  340. return link_speeds[LS_UNKNOWN];
  341. }
  342. static void
  343. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  344. {
  345. struct qla_hw_data *ha = vha->hw;
  346. /*
  347. * 8200 AEN Interpretation:
  348. * mb[0] = AEN code
  349. * mb[1] = AEN Reason code
  350. * mb[2] = LSW of Peg-Halt Status-1 Register
  351. * mb[6] = MSW of Peg-Halt Status-1 Register
  352. * mb[3] = LSW of Peg-Halt Status-2 register
  353. * mb[7] = MSW of Peg-Halt Status-2 register
  354. * mb[4] = IDC Device-State Register value
  355. * mb[5] = IDC Driver-Presence Register value
  356. */
  357. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  358. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  359. mb[0], mb[1], mb[2], mb[6]);
  360. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  361. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  362. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  363. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  364. IDC_HEARTBEAT_FAILURE)) {
  365. ha->flags.nic_core_hung = 1;
  366. ql_log(ql_log_warn, vha, 0x5060,
  367. "83XX: F/W Error Reported: Check if reset required.\n");
  368. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  369. uint32_t protocol_engine_id, fw_err_code, err_level;
  370. /*
  371. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  372. * - PEG-Halt Status-1 Register:
  373. * (LSW = mb[2], MSW = mb[6])
  374. * Bits 0-7 = protocol-engine ID
  375. * Bits 8-28 = f/w error code
  376. * Bits 29-31 = Error-level
  377. * Error-level 0x1 = Non-Fatal error
  378. * Error-level 0x2 = Recoverable Fatal error
  379. * Error-level 0x4 = UnRecoverable Fatal error
  380. * - PEG-Halt Status-2 Register:
  381. * (LSW = mb[3], MSW = mb[7])
  382. */
  383. protocol_engine_id = (mb[2] & 0xff);
  384. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  385. ((mb[6] & 0x1fff) << 8));
  386. err_level = ((mb[6] & 0xe000) >> 13);
  387. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  388. "Register: protocol_engine_id=0x%x "
  389. "fw_err_code=0x%x err_level=0x%x.\n",
  390. protocol_engine_id, fw_err_code, err_level);
  391. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  392. "Register: 0x%x%x.\n", mb[7], mb[3]);
  393. if (err_level == ERR_LEVEL_NON_FATAL) {
  394. ql_log(ql_log_warn, vha, 0x5063,
  395. "Not a fatal error, f/w has recovered itself.\n");
  396. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  397. ql_log(ql_log_fatal, vha, 0x5064,
  398. "Recoverable Fatal error: Chip reset "
  399. "required.\n");
  400. qla83xx_schedule_work(vha,
  401. QLA83XX_NIC_CORE_RESET);
  402. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  403. ql_log(ql_log_fatal, vha, 0x5065,
  404. "Unrecoverable Fatal error: Set FAILED "
  405. "state, reboot required.\n");
  406. qla83xx_schedule_work(vha,
  407. QLA83XX_NIC_CORE_UNRECOVERABLE);
  408. }
  409. }
  410. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  411. uint16_t peg_fw_state, nw_interface_link_up;
  412. uint16_t nw_interface_signal_detect, sfp_status;
  413. uint16_t htbt_counter, htbt_monitor_enable;
  414. uint16_t sfp_additional_info, sfp_multirate;
  415. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  416. /*
  417. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  418. * - PEG-to-FC Status Register:
  419. * (LSW = mb[2], MSW = mb[6])
  420. * Bits 0-7 = Peg-Firmware state
  421. * Bit 8 = N/W Interface Link-up
  422. * Bit 9 = N/W Interface signal detected
  423. * Bits 10-11 = SFP Status
  424. * SFP Status 0x0 = SFP+ transceiver not expected
  425. * SFP Status 0x1 = SFP+ transceiver not present
  426. * SFP Status 0x2 = SFP+ transceiver invalid
  427. * SFP Status 0x3 = SFP+ transceiver present and
  428. * valid
  429. * Bits 12-14 = Heartbeat Counter
  430. * Bit 15 = Heartbeat Monitor Enable
  431. * Bits 16-17 = SFP Additional Info
  432. * SFP info 0x0 = Unregocnized transceiver for
  433. * Ethernet
  434. * SFP info 0x1 = SFP+ brand validation failed
  435. * SFP info 0x2 = SFP+ speed validation failed
  436. * SFP info 0x3 = SFP+ access error
  437. * Bit 18 = SFP Multirate
  438. * Bit 19 = SFP Tx Fault
  439. * Bits 20-22 = Link Speed
  440. * Bits 23-27 = Reserved
  441. * Bits 28-30 = DCBX Status
  442. * DCBX Status 0x0 = DCBX Disabled
  443. * DCBX Status 0x1 = DCBX Enabled
  444. * DCBX Status 0x2 = DCBX Exchange error
  445. * Bit 31 = Reserved
  446. */
  447. peg_fw_state = (mb[2] & 0x00ff);
  448. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  449. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  450. sfp_status = ((mb[2] & 0x0c00) >> 10);
  451. htbt_counter = ((mb[2] & 0x7000) >> 12);
  452. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  453. sfp_additional_info = (mb[6] & 0x0003);
  454. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  455. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  456. link_speed = ((mb[6] & 0x0070) >> 4);
  457. dcbx_status = ((mb[6] & 0x7000) >> 12);
  458. ql_log(ql_log_warn, vha, 0x5066,
  459. "Peg-to-Fc Status Register:\n"
  460. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  461. "nw_interface_signal_detect=0x%x"
  462. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  463. nw_interface_link_up, nw_interface_signal_detect,
  464. sfp_status);
  465. ql_log(ql_log_warn, vha, 0x5067,
  466. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  467. "sfp_additional_info=0x%x, sfp_multirate=0x%x.\n ",
  468. htbt_counter, htbt_monitor_enable,
  469. sfp_additional_info, sfp_multirate);
  470. ql_log(ql_log_warn, vha, 0x5068,
  471. "sfp_tx_fault=0x%x, link_state=0x%x, "
  472. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  473. dcbx_status);
  474. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  475. }
  476. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  477. ql_log(ql_log_warn, vha, 0x5069,
  478. "Heartbeat Failure encountered, chip reset "
  479. "required.\n");
  480. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  481. }
  482. }
  483. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  484. ql_log(ql_log_info, vha, 0x506a,
  485. "IDC Device-State changed = 0x%x.\n", mb[4]);
  486. if (ha->flags.nic_core_reset_owner)
  487. return;
  488. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  489. }
  490. }
  491. int
  492. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  493. {
  494. struct qla_hw_data *ha = vha->hw;
  495. scsi_qla_host_t *vp;
  496. uint32_t vp_did;
  497. unsigned long flags;
  498. int ret = 0;
  499. if (!ha->num_vhosts)
  500. return ret;
  501. spin_lock_irqsave(&ha->vport_slock, flags);
  502. list_for_each_entry(vp, &ha->vp_list, list) {
  503. vp_did = vp->d_id.b24;
  504. if (vp_did == rscn_entry) {
  505. ret = 1;
  506. break;
  507. }
  508. }
  509. spin_unlock_irqrestore(&ha->vport_slock, flags);
  510. return ret;
  511. }
  512. fc_port_t *
  513. qla2x00_find_fcport_by_loopid(scsi_qla_host_t *vha, uint16_t loop_id)
  514. {
  515. fc_port_t *f, *tf;
  516. f = tf = NULL;
  517. list_for_each_entry_safe(f, tf, &vha->vp_fcports, list)
  518. if (f->loop_id == loop_id)
  519. return f;
  520. return NULL;
  521. }
  522. fc_port_t *
  523. qla2x00_find_fcport_by_wwpn(scsi_qla_host_t *vha, u8 *wwpn, u8 incl_deleted)
  524. {
  525. fc_port_t *f, *tf;
  526. f = tf = NULL;
  527. list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) {
  528. if (memcmp(f->port_name, wwpn, WWN_SIZE) == 0) {
  529. if (incl_deleted)
  530. return f;
  531. else if (f->deleted == 0)
  532. return f;
  533. }
  534. }
  535. return NULL;
  536. }
  537. fc_port_t *
  538. qla2x00_find_fcport_by_nportid(scsi_qla_host_t *vha, port_id_t *id,
  539. u8 incl_deleted)
  540. {
  541. fc_port_t *f, *tf;
  542. f = tf = NULL;
  543. list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) {
  544. if (f->d_id.b24 == id->b24) {
  545. if (incl_deleted)
  546. return f;
  547. else if (f->deleted == 0)
  548. return f;
  549. }
  550. }
  551. return NULL;
  552. }
  553. /**
  554. * qla2x00_async_event() - Process aynchronous events.
  555. * @vha: SCSI driver HA context
  556. * @rsp: response queue
  557. * @mb: Mailbox registers (0 - 3)
  558. */
  559. void
  560. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  561. {
  562. uint16_t handle_cnt;
  563. uint16_t cnt, mbx;
  564. uint32_t handles[5];
  565. struct qla_hw_data *ha = vha->hw;
  566. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  567. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  568. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  569. uint32_t rscn_entry, host_pid;
  570. unsigned long flags;
  571. fc_port_t *fcport = NULL;
  572. if (!vha->hw->flags.fw_started)
  573. return;
  574. /* Setup to process RIO completion. */
  575. handle_cnt = 0;
  576. if (IS_CNA_CAPABLE(ha))
  577. goto skip_rio;
  578. switch (mb[0]) {
  579. case MBA_SCSI_COMPLETION:
  580. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  581. handle_cnt = 1;
  582. break;
  583. case MBA_CMPLT_1_16BIT:
  584. handles[0] = mb[1];
  585. handle_cnt = 1;
  586. mb[0] = MBA_SCSI_COMPLETION;
  587. break;
  588. case MBA_CMPLT_2_16BIT:
  589. handles[0] = mb[1];
  590. handles[1] = mb[2];
  591. handle_cnt = 2;
  592. mb[0] = MBA_SCSI_COMPLETION;
  593. break;
  594. case MBA_CMPLT_3_16BIT:
  595. handles[0] = mb[1];
  596. handles[1] = mb[2];
  597. handles[2] = mb[3];
  598. handle_cnt = 3;
  599. mb[0] = MBA_SCSI_COMPLETION;
  600. break;
  601. case MBA_CMPLT_4_16BIT:
  602. handles[0] = mb[1];
  603. handles[1] = mb[2];
  604. handles[2] = mb[3];
  605. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  606. handle_cnt = 4;
  607. mb[0] = MBA_SCSI_COMPLETION;
  608. break;
  609. case MBA_CMPLT_5_16BIT:
  610. handles[0] = mb[1];
  611. handles[1] = mb[2];
  612. handles[2] = mb[3];
  613. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  614. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  615. handle_cnt = 5;
  616. mb[0] = MBA_SCSI_COMPLETION;
  617. break;
  618. case MBA_CMPLT_2_32BIT:
  619. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  620. handles[1] = le32_to_cpu(
  621. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  622. RD_MAILBOX_REG(ha, reg, 6));
  623. handle_cnt = 2;
  624. mb[0] = MBA_SCSI_COMPLETION;
  625. break;
  626. default:
  627. break;
  628. }
  629. skip_rio:
  630. switch (mb[0]) {
  631. case MBA_SCSI_COMPLETION: /* Fast Post */
  632. if (!vha->flags.online)
  633. break;
  634. for (cnt = 0; cnt < handle_cnt; cnt++)
  635. qla2x00_process_completed_request(vha, rsp->req,
  636. handles[cnt]);
  637. break;
  638. case MBA_RESET: /* Reset */
  639. ql_dbg(ql_dbg_async, vha, 0x5002,
  640. "Asynchronous RESET.\n");
  641. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  642. break;
  643. case MBA_SYSTEM_ERR: /* System Error */
  644. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ?
  645. RD_REG_WORD(&reg24->mailbox7) : 0;
  646. ql_log(ql_log_warn, vha, 0x5003,
  647. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  648. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  649. ha->isp_ops->fw_dump(vha, 1);
  650. ha->flags.fw_init_done = 0;
  651. QLA_FW_STOPPED(ha);
  652. if (IS_FWI2_CAPABLE(ha)) {
  653. if (mb[1] == 0 && mb[2] == 0) {
  654. ql_log(ql_log_fatal, vha, 0x5004,
  655. "Unrecoverable Hardware Error: adapter "
  656. "marked OFFLINE!\n");
  657. vha->flags.online = 0;
  658. vha->device_flags |= DFLG_DEV_FAILED;
  659. } else {
  660. /* Check to see if MPI timeout occurred */
  661. if ((mbx & MBX_3) && (ha->port_no == 0))
  662. set_bit(MPI_RESET_NEEDED,
  663. &vha->dpc_flags);
  664. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  665. }
  666. } else if (mb[1] == 0) {
  667. ql_log(ql_log_fatal, vha, 0x5005,
  668. "Unrecoverable Hardware Error: adapter marked "
  669. "OFFLINE!\n");
  670. vha->flags.online = 0;
  671. vha->device_flags |= DFLG_DEV_FAILED;
  672. } else
  673. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  674. break;
  675. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  676. ql_log(ql_log_warn, vha, 0x5006,
  677. "ISP Request Transfer Error (%x).\n", mb[1]);
  678. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  679. break;
  680. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  681. ql_log(ql_log_warn, vha, 0x5007,
  682. "ISP Response Transfer Error (%x).\n", mb[1]);
  683. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  684. break;
  685. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  686. ql_dbg(ql_dbg_async, vha, 0x5008,
  687. "Asynchronous WAKEUP_THRES (%x).\n", mb[1]);
  688. break;
  689. case MBA_LOOP_INIT_ERR:
  690. ql_log(ql_log_warn, vha, 0x5090,
  691. "LOOP INIT ERROR (%x).\n", mb[1]);
  692. ha->isp_ops->fw_dump(vha, 1);
  693. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  694. break;
  695. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  696. ha->flags.lip_ae = 1;
  697. ql_dbg(ql_dbg_async, vha, 0x5009,
  698. "LIP occurred (%x).\n", mb[1]);
  699. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  700. atomic_set(&vha->loop_state, LOOP_DOWN);
  701. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  702. qla2x00_mark_all_devices_lost(vha, 1);
  703. }
  704. if (vha->vp_idx) {
  705. atomic_set(&vha->vp_state, VP_FAILED);
  706. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  707. }
  708. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  709. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  710. vha->flags.management_server_logged_in = 0;
  711. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  712. break;
  713. case MBA_LOOP_UP: /* Loop Up Event */
  714. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  715. ha->link_data_rate = PORT_SPEED_1GB;
  716. else
  717. ha->link_data_rate = mb[1];
  718. ql_log(ql_log_info, vha, 0x500a,
  719. "LOOP UP detected (%s Gbps).\n",
  720. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  721. vha->flags.management_server_logged_in = 0;
  722. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  723. if (AUTO_DETECT_SFP_SUPPORT(vha)) {
  724. set_bit(DETECT_SFP_CHANGE, &vha->dpc_flags);
  725. qla2xxx_wake_dpc(vha);
  726. }
  727. break;
  728. case MBA_LOOP_DOWN: /* Loop Down Event */
  729. SAVE_TOPO(ha);
  730. ha->flags.lip_ae = 0;
  731. ha->current_topology = 0;
  732. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  733. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  734. mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(&reg82->mailbox_out[4])
  735. : mbx;
  736. ql_log(ql_log_info, vha, 0x500b,
  737. "LOOP DOWN detected (%x %x %x %x).\n",
  738. mb[1], mb[2], mb[3], mbx);
  739. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  740. atomic_set(&vha->loop_state, LOOP_DOWN);
  741. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  742. /*
  743. * In case of loop down, restore WWPN from
  744. * NVRAM in case of FA-WWPN capable ISP
  745. * Restore for Physical Port only
  746. */
  747. if (!vha->vp_idx) {
  748. if (ha->flags.fawwpn_enabled) {
  749. void *wwpn = ha->init_cb->port_name;
  750. memcpy(vha->port_name, wwpn, WWN_SIZE);
  751. fc_host_port_name(vha->host) =
  752. wwn_to_u64(vha->port_name);
  753. ql_dbg(ql_dbg_init + ql_dbg_verbose,
  754. vha, 0x00d8, "LOOP DOWN detected,"
  755. "restore WWPN %016llx\n",
  756. wwn_to_u64(vha->port_name));
  757. }
  758. clear_bit(VP_CONFIG_OK, &vha->vp_flags);
  759. }
  760. vha->device_flags |= DFLG_NO_CABLE;
  761. qla2x00_mark_all_devices_lost(vha, 1);
  762. }
  763. if (vha->vp_idx) {
  764. atomic_set(&vha->vp_state, VP_FAILED);
  765. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  766. }
  767. vha->flags.management_server_logged_in = 0;
  768. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  769. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  770. break;
  771. case MBA_LIP_RESET: /* LIP reset occurred */
  772. ql_dbg(ql_dbg_async, vha, 0x500c,
  773. "LIP reset occurred (%x).\n", mb[1]);
  774. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  775. atomic_set(&vha->loop_state, LOOP_DOWN);
  776. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  777. qla2x00_mark_all_devices_lost(vha, 1);
  778. }
  779. if (vha->vp_idx) {
  780. atomic_set(&vha->vp_state, VP_FAILED);
  781. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  782. }
  783. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  784. ha->operating_mode = LOOP;
  785. vha->flags.management_server_logged_in = 0;
  786. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  787. break;
  788. /* case MBA_DCBX_COMPLETE: */
  789. case MBA_POINT_TO_POINT: /* Point-to-Point */
  790. ha->flags.lip_ae = 0;
  791. if (IS_QLA2100(ha))
  792. break;
  793. if (IS_CNA_CAPABLE(ha)) {
  794. ql_dbg(ql_dbg_async, vha, 0x500d,
  795. "DCBX Completed -- %04x %04x %04x.\n",
  796. mb[1], mb[2], mb[3]);
  797. if (ha->notify_dcbx_comp && !vha->vp_idx)
  798. complete(&ha->dcbx_comp);
  799. } else
  800. ql_dbg(ql_dbg_async, vha, 0x500e,
  801. "Asynchronous P2P MODE received.\n");
  802. /*
  803. * Until there's a transition from loop down to loop up, treat
  804. * this as loop down only.
  805. */
  806. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  807. atomic_set(&vha->loop_state, LOOP_DOWN);
  808. if (!atomic_read(&vha->loop_down_timer))
  809. atomic_set(&vha->loop_down_timer,
  810. LOOP_DOWN_TIME);
  811. if (!N2N_TOPO(ha))
  812. qla2x00_mark_all_devices_lost(vha, 1);
  813. }
  814. if (vha->vp_idx) {
  815. atomic_set(&vha->vp_state, VP_FAILED);
  816. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  817. }
  818. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  819. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  820. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  821. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  822. vha->flags.management_server_logged_in = 0;
  823. break;
  824. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  825. if (IS_QLA2100(ha))
  826. break;
  827. ql_dbg(ql_dbg_async, vha, 0x500f,
  828. "Configuration change detected: value=%x.\n", mb[1]);
  829. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  830. atomic_set(&vha->loop_state, LOOP_DOWN);
  831. if (!atomic_read(&vha->loop_down_timer))
  832. atomic_set(&vha->loop_down_timer,
  833. LOOP_DOWN_TIME);
  834. qla2x00_mark_all_devices_lost(vha, 1);
  835. }
  836. if (vha->vp_idx) {
  837. atomic_set(&vha->vp_state, VP_FAILED);
  838. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  839. }
  840. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  841. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  842. break;
  843. case MBA_PORT_UPDATE: /* Port database update */
  844. /*
  845. * Handle only global and vn-port update events
  846. *
  847. * Relevant inputs:
  848. * mb[1] = N_Port handle of changed port
  849. * OR 0xffff for global event
  850. * mb[2] = New login state
  851. * 7 = Port logged out
  852. * mb[3] = LSB is vp_idx, 0xff = all vps
  853. *
  854. * Skip processing if:
  855. * Event is global, vp_idx is NOT all vps,
  856. * vp_idx does not match
  857. * Event is not global, vp_idx does not match
  858. */
  859. if (IS_QLA2XXX_MIDTYPE(ha) &&
  860. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  861. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  862. break;
  863. if (mb[2] == 0x7) {
  864. ql_dbg(ql_dbg_async, vha, 0x5010,
  865. "Port %s %04x %04x %04x.\n",
  866. mb[1] == 0xffff ? "unavailable" : "logout",
  867. mb[1], mb[2], mb[3]);
  868. if (mb[1] == 0xffff)
  869. goto global_port_update;
  870. if (mb[1] == NPH_SNS_LID(ha)) {
  871. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  872. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  873. break;
  874. }
  875. /* use handle_cnt for loop id/nport handle */
  876. if (IS_FWI2_CAPABLE(ha))
  877. handle_cnt = NPH_SNS;
  878. else
  879. handle_cnt = SIMPLE_NAME_SERVER;
  880. if (mb[1] == handle_cnt) {
  881. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  882. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  883. break;
  884. }
  885. /* Port logout */
  886. fcport = qla2x00_find_fcport_by_loopid(vha, mb[1]);
  887. if (!fcport)
  888. break;
  889. if (atomic_read(&fcport->state) != FCS_ONLINE)
  890. break;
  891. ql_dbg(ql_dbg_async, vha, 0x508a,
  892. "Marking port lost loopid=%04x portid=%06x.\n",
  893. fcport->loop_id, fcport->d_id.b24);
  894. if (qla_ini_mode_enabled(vha)) {
  895. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  896. fcport->logout_on_delete = 0;
  897. qlt_schedule_sess_for_deletion(fcport);
  898. }
  899. break;
  900. global_port_update:
  901. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  902. atomic_set(&vha->loop_state, LOOP_DOWN);
  903. atomic_set(&vha->loop_down_timer,
  904. LOOP_DOWN_TIME);
  905. vha->device_flags |= DFLG_NO_CABLE;
  906. qla2x00_mark_all_devices_lost(vha, 1);
  907. }
  908. if (vha->vp_idx) {
  909. atomic_set(&vha->vp_state, VP_FAILED);
  910. fc_vport_set_state(vha->fc_vport,
  911. FC_VPORT_FAILED);
  912. qla2x00_mark_all_devices_lost(vha, 1);
  913. }
  914. vha->flags.management_server_logged_in = 0;
  915. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  916. break;
  917. }
  918. /*
  919. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  920. * event etc. earlier indicating loop is down) then process
  921. * it. Otherwise ignore it and Wait for RSCN to come in.
  922. */
  923. atomic_set(&vha->loop_down_timer, 0);
  924. if (atomic_read(&vha->loop_state) != LOOP_DOWN &&
  925. !ha->flags.n2n_ae &&
  926. atomic_read(&vha->loop_state) != LOOP_DEAD) {
  927. ql_dbg(ql_dbg_async, vha, 0x5011,
  928. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  929. mb[1], mb[2], mb[3]);
  930. break;
  931. }
  932. ql_dbg(ql_dbg_async, vha, 0x5012,
  933. "Port database changed %04x %04x %04x.\n",
  934. mb[1], mb[2], mb[3]);
  935. /*
  936. * Mark all devices as missing so we will login again.
  937. */
  938. atomic_set(&vha->loop_state, LOOP_UP);
  939. vha->scan.scan_retry = 0;
  940. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  941. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  942. set_bit(VP_CONFIG_OK, &vha->vp_flags);
  943. break;
  944. case MBA_RSCN_UPDATE: /* State Change Registration */
  945. /* Check if the Vport has issued a SCR */
  946. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  947. break;
  948. /* Only handle SCNs for our Vport index. */
  949. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  950. break;
  951. ql_dbg(ql_dbg_async, vha, 0x5013,
  952. "RSCN database changed -- %04x %04x %04x.\n",
  953. mb[1], mb[2], mb[3]);
  954. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  955. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  956. | vha->d_id.b.al_pa;
  957. if (rscn_entry == host_pid) {
  958. ql_dbg(ql_dbg_async, vha, 0x5014,
  959. "Ignoring RSCN update to local host "
  960. "port ID (%06x).\n", host_pid);
  961. break;
  962. }
  963. /* Ignore reserved bits from RSCN-payload. */
  964. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  965. /* Skip RSCNs for virtual ports on the same physical port */
  966. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  967. break;
  968. atomic_set(&vha->loop_down_timer, 0);
  969. vha->flags.management_server_logged_in = 0;
  970. {
  971. struct event_arg ea;
  972. memset(&ea, 0, sizeof(ea));
  973. ea.event = FCME_RSCN;
  974. ea.id.b24 = rscn_entry;
  975. ea.id.b.rsvd_1 = rscn_entry >> 24;
  976. qla2x00_fcport_event_handler(vha, &ea);
  977. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  978. }
  979. break;
  980. /* case MBA_RIO_RESPONSE: */
  981. case MBA_ZIO_RESPONSE:
  982. ql_dbg(ql_dbg_async, vha, 0x5015,
  983. "[R|Z]IO update completion.\n");
  984. if (IS_FWI2_CAPABLE(ha))
  985. qla24xx_process_response_queue(vha, rsp);
  986. else
  987. qla2x00_process_response_queue(rsp);
  988. break;
  989. case MBA_DISCARD_RND_FRAME:
  990. ql_dbg(ql_dbg_async, vha, 0x5016,
  991. "Discard RND Frame -- %04x %04x %04x.\n",
  992. mb[1], mb[2], mb[3]);
  993. break;
  994. case MBA_TRACE_NOTIFICATION:
  995. ql_dbg(ql_dbg_async, vha, 0x5017,
  996. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  997. break;
  998. case MBA_ISP84XX_ALERT:
  999. ql_dbg(ql_dbg_async, vha, 0x5018,
  1000. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  1001. mb[1], mb[2], mb[3]);
  1002. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  1003. switch (mb[1]) {
  1004. case A84_PANIC_RECOVERY:
  1005. ql_log(ql_log_info, vha, 0x5019,
  1006. "Alert 84XX: panic recovery %04x %04x.\n",
  1007. mb[2], mb[3]);
  1008. break;
  1009. case A84_OP_LOGIN_COMPLETE:
  1010. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  1011. ql_log(ql_log_info, vha, 0x501a,
  1012. "Alert 84XX: firmware version %x.\n",
  1013. ha->cs84xx->op_fw_version);
  1014. break;
  1015. case A84_DIAG_LOGIN_COMPLETE:
  1016. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  1017. ql_log(ql_log_info, vha, 0x501b,
  1018. "Alert 84XX: diagnostic firmware version %x.\n",
  1019. ha->cs84xx->diag_fw_version);
  1020. break;
  1021. case A84_GOLD_LOGIN_COMPLETE:
  1022. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  1023. ha->cs84xx->fw_update = 1;
  1024. ql_log(ql_log_info, vha, 0x501c,
  1025. "Alert 84XX: gold firmware version %x.\n",
  1026. ha->cs84xx->gold_fw_version);
  1027. break;
  1028. default:
  1029. ql_log(ql_log_warn, vha, 0x501d,
  1030. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  1031. mb[1], mb[2], mb[3]);
  1032. }
  1033. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  1034. break;
  1035. case MBA_DCBX_START:
  1036. ql_dbg(ql_dbg_async, vha, 0x501e,
  1037. "DCBX Started -- %04x %04x %04x.\n",
  1038. mb[1], mb[2], mb[3]);
  1039. break;
  1040. case MBA_DCBX_PARAM_UPDATE:
  1041. ql_dbg(ql_dbg_async, vha, 0x501f,
  1042. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  1043. mb[1], mb[2], mb[3]);
  1044. break;
  1045. case MBA_FCF_CONF_ERR:
  1046. ql_dbg(ql_dbg_async, vha, 0x5020,
  1047. "FCF Configuration Error -- %04x %04x %04x.\n",
  1048. mb[1], mb[2], mb[3]);
  1049. break;
  1050. case MBA_IDC_NOTIFY:
  1051. if (IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
  1052. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  1053. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  1054. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  1055. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  1056. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  1057. /*
  1058. * Extend loop down timer since port is active.
  1059. */
  1060. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  1061. atomic_set(&vha->loop_down_timer,
  1062. LOOP_DOWN_TIME);
  1063. qla2xxx_wake_dpc(vha);
  1064. }
  1065. }
  1066. /* fall through */
  1067. case MBA_IDC_COMPLETE:
  1068. if (ha->notify_lb_portup_comp && !vha->vp_idx)
  1069. complete(&ha->lb_portup_comp);
  1070. /* Fallthru */
  1071. case MBA_IDC_TIME_EXT:
  1072. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) ||
  1073. IS_QLA8044(ha))
  1074. qla81xx_idc_event(vha, mb[0], mb[1]);
  1075. break;
  1076. case MBA_IDC_AEN:
  1077. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  1078. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  1079. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  1080. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  1081. qla83xx_handle_8200_aen(vha, mb);
  1082. break;
  1083. case MBA_DPORT_DIAGNOSTICS:
  1084. ql_dbg(ql_dbg_async, vha, 0x5052,
  1085. "D-Port Diagnostics: %04x result=%s\n",
  1086. mb[0],
  1087. mb[1] == 0 ? "start" :
  1088. mb[1] == 1 ? "done (pass)" :
  1089. mb[1] == 2 ? "done (error)" : "other");
  1090. break;
  1091. case MBA_TEMPERATURE_ALERT:
  1092. ql_dbg(ql_dbg_async, vha, 0x505e,
  1093. "TEMPERATURE ALERT: %04x %04x %04x\n", mb[1], mb[2], mb[3]);
  1094. if (mb[1] == 0x12)
  1095. schedule_work(&ha->board_disable);
  1096. break;
  1097. case MBA_TRANS_INSERT:
  1098. ql_dbg(ql_dbg_async, vha, 0x5091,
  1099. "Transceiver Insertion: %04x\n", mb[1]);
  1100. break;
  1101. default:
  1102. ql_dbg(ql_dbg_async, vha, 0x5057,
  1103. "Unknown AEN:%04x %04x %04x %04x\n",
  1104. mb[0], mb[1], mb[2], mb[3]);
  1105. }
  1106. qlt_async_event(mb[0], vha, mb);
  1107. if (!vha->vp_idx && ha->num_vhosts)
  1108. qla2x00_alert_all_vps(rsp, mb);
  1109. }
  1110. /**
  1111. * qla2x00_process_completed_request() - Process a Fast Post response.
  1112. * @vha: SCSI driver HA context
  1113. * @req: request queue
  1114. * @index: SRB index
  1115. */
  1116. void
  1117. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  1118. struct req_que *req, uint32_t index)
  1119. {
  1120. srb_t *sp;
  1121. struct qla_hw_data *ha = vha->hw;
  1122. /* Validate handle. */
  1123. if (index >= req->num_outstanding_cmds) {
  1124. ql_log(ql_log_warn, vha, 0x3014,
  1125. "Invalid SCSI command index (%x).\n", index);
  1126. if (IS_P3P_TYPE(ha))
  1127. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1128. else
  1129. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1130. return;
  1131. }
  1132. sp = req->outstanding_cmds[index];
  1133. if (sp) {
  1134. /* Free outstanding command slot. */
  1135. req->outstanding_cmds[index] = NULL;
  1136. /* Save ISP completion status */
  1137. sp->done(sp, DID_OK << 16);
  1138. } else {
  1139. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  1140. if (IS_P3P_TYPE(ha))
  1141. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1142. else
  1143. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1144. }
  1145. }
  1146. srb_t *
  1147. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  1148. struct req_que *req, void *iocb)
  1149. {
  1150. struct qla_hw_data *ha = vha->hw;
  1151. sts_entry_t *pkt = iocb;
  1152. srb_t *sp = NULL;
  1153. uint16_t index;
  1154. index = LSW(pkt->handle);
  1155. if (index >= req->num_outstanding_cmds) {
  1156. ql_log(ql_log_warn, vha, 0x5031,
  1157. "Invalid command index (%x) type %8ph.\n",
  1158. index, iocb);
  1159. if (IS_P3P_TYPE(ha))
  1160. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1161. else
  1162. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1163. goto done;
  1164. }
  1165. sp = req->outstanding_cmds[index];
  1166. if (!sp) {
  1167. ql_log(ql_log_warn, vha, 0x5032,
  1168. "Invalid completion handle (%x) -- timed-out.\n", index);
  1169. return sp;
  1170. }
  1171. if (sp->handle != index) {
  1172. ql_log(ql_log_warn, vha, 0x5033,
  1173. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  1174. return NULL;
  1175. }
  1176. req->outstanding_cmds[index] = NULL;
  1177. done:
  1178. return sp;
  1179. }
  1180. static void
  1181. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1182. struct mbx_entry *mbx)
  1183. {
  1184. const char func[] = "MBX-IOCB";
  1185. const char *type;
  1186. fc_port_t *fcport;
  1187. srb_t *sp;
  1188. struct srb_iocb *lio;
  1189. uint16_t *data;
  1190. uint16_t status;
  1191. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1192. if (!sp)
  1193. return;
  1194. lio = &sp->u.iocb_cmd;
  1195. type = sp->name;
  1196. fcport = sp->fcport;
  1197. data = lio->u.logio.data;
  1198. data[0] = MBS_COMMAND_ERROR;
  1199. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1200. QLA_LOGIO_LOGIN_RETRIED : 0;
  1201. if (mbx->entry_status) {
  1202. ql_dbg(ql_dbg_async, vha, 0x5043,
  1203. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1204. "entry-status=%x status=%x state-flag=%x "
  1205. "status-flags=%x.\n", type, sp->handle,
  1206. fcport->d_id.b.domain, fcport->d_id.b.area,
  1207. fcport->d_id.b.al_pa, mbx->entry_status,
  1208. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1209. le16_to_cpu(mbx->status_flags));
  1210. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1211. (uint8_t *)mbx, sizeof(*mbx));
  1212. goto logio_done;
  1213. }
  1214. status = le16_to_cpu(mbx->status);
  1215. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1216. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1217. status = 0;
  1218. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1219. ql_dbg(ql_dbg_async, vha, 0x5045,
  1220. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1221. type, sp->handle, fcport->d_id.b.domain,
  1222. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1223. le16_to_cpu(mbx->mb1));
  1224. data[0] = MBS_COMMAND_COMPLETE;
  1225. if (sp->type == SRB_LOGIN_CMD) {
  1226. fcport->port_type = FCT_TARGET;
  1227. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1228. fcport->port_type = FCT_INITIATOR;
  1229. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1230. fcport->flags |= FCF_FCP2_DEVICE;
  1231. }
  1232. goto logio_done;
  1233. }
  1234. data[0] = le16_to_cpu(mbx->mb0);
  1235. switch (data[0]) {
  1236. case MBS_PORT_ID_USED:
  1237. data[1] = le16_to_cpu(mbx->mb1);
  1238. break;
  1239. case MBS_LOOP_ID_USED:
  1240. break;
  1241. default:
  1242. data[0] = MBS_COMMAND_ERROR;
  1243. break;
  1244. }
  1245. ql_log(ql_log_warn, vha, 0x5046,
  1246. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1247. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1248. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1249. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1250. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1251. le16_to_cpu(mbx->mb7));
  1252. logio_done:
  1253. sp->done(sp, 0);
  1254. }
  1255. static void
  1256. qla24xx_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1257. struct mbx_24xx_entry *pkt)
  1258. {
  1259. const char func[] = "MBX-IOCB2";
  1260. srb_t *sp;
  1261. struct srb_iocb *si;
  1262. u16 sz, i;
  1263. int res;
  1264. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1265. if (!sp)
  1266. return;
  1267. si = &sp->u.iocb_cmd;
  1268. sz = min(ARRAY_SIZE(pkt->mb), ARRAY_SIZE(sp->u.iocb_cmd.u.mbx.in_mb));
  1269. for (i = 0; i < sz; i++)
  1270. si->u.mbx.in_mb[i] = le16_to_cpu(pkt->mb[i]);
  1271. res = (si->u.mbx.in_mb[0] & MBS_MASK);
  1272. sp->done(sp, res);
  1273. }
  1274. static void
  1275. qla24xxx_nack_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1276. struct nack_to_isp *pkt)
  1277. {
  1278. const char func[] = "nack";
  1279. srb_t *sp;
  1280. int res = 0;
  1281. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1282. if (!sp)
  1283. return;
  1284. if (pkt->u.isp2x.status != cpu_to_le16(NOTIFY_ACK_SUCCESS))
  1285. res = QLA_FUNCTION_FAILED;
  1286. sp->done(sp, res);
  1287. }
  1288. static void
  1289. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1290. sts_entry_t *pkt, int iocb_type)
  1291. {
  1292. const char func[] = "CT_IOCB";
  1293. const char *type;
  1294. srb_t *sp;
  1295. struct bsg_job *bsg_job;
  1296. struct fc_bsg_reply *bsg_reply;
  1297. uint16_t comp_status;
  1298. int res = 0;
  1299. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1300. if (!sp)
  1301. return;
  1302. switch (sp->type) {
  1303. case SRB_CT_CMD:
  1304. bsg_job = sp->u.bsg_job;
  1305. bsg_reply = bsg_job->reply;
  1306. type = "ct pass-through";
  1307. comp_status = le16_to_cpu(pkt->comp_status);
  1308. /*
  1309. * return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1310. * fc payload to the caller
  1311. */
  1312. bsg_reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1313. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1314. if (comp_status != CS_COMPLETE) {
  1315. if (comp_status == CS_DATA_UNDERRUN) {
  1316. res = DID_OK << 16;
  1317. bsg_reply->reply_payload_rcv_len =
  1318. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1319. ql_log(ql_log_warn, vha, 0x5048,
  1320. "CT pass-through-%s error comp_status=0x%x total_byte=0x%x.\n",
  1321. type, comp_status,
  1322. bsg_reply->reply_payload_rcv_len);
  1323. } else {
  1324. ql_log(ql_log_warn, vha, 0x5049,
  1325. "CT pass-through-%s error comp_status=0x%x.\n",
  1326. type, comp_status);
  1327. res = DID_ERROR << 16;
  1328. bsg_reply->reply_payload_rcv_len = 0;
  1329. }
  1330. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1331. (uint8_t *)pkt, sizeof(*pkt));
  1332. } else {
  1333. res = DID_OK << 16;
  1334. bsg_reply->reply_payload_rcv_len =
  1335. bsg_job->reply_payload.payload_len;
  1336. bsg_job->reply_len = 0;
  1337. }
  1338. break;
  1339. case SRB_CT_PTHRU_CMD:
  1340. /*
  1341. * borrowing sts_entry_24xx.comp_status.
  1342. * same location as ct_entry_24xx.comp_status
  1343. */
  1344. res = qla2x00_chk_ms_status(vha, (ms_iocb_entry_t *)pkt,
  1345. (struct ct_sns_rsp *)sp->u.iocb_cmd.u.ctarg.rsp,
  1346. sp->name);
  1347. break;
  1348. }
  1349. sp->done(sp, res);
  1350. }
  1351. static void
  1352. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1353. struct sts_entry_24xx *pkt, int iocb_type)
  1354. {
  1355. const char func[] = "ELS_CT_IOCB";
  1356. const char *type;
  1357. srb_t *sp;
  1358. struct bsg_job *bsg_job;
  1359. struct fc_bsg_reply *bsg_reply;
  1360. uint16_t comp_status;
  1361. uint32_t fw_status[3];
  1362. int res;
  1363. struct srb_iocb *els;
  1364. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1365. if (!sp)
  1366. return;
  1367. type = NULL;
  1368. switch (sp->type) {
  1369. case SRB_ELS_CMD_RPT:
  1370. case SRB_ELS_CMD_HST:
  1371. type = "els";
  1372. break;
  1373. case SRB_CT_CMD:
  1374. type = "ct pass-through";
  1375. break;
  1376. case SRB_ELS_DCMD:
  1377. type = "Driver ELS logo";
  1378. if (iocb_type != ELS_IOCB_TYPE) {
  1379. ql_dbg(ql_dbg_user, vha, 0x5047,
  1380. "Completing %s: (%p) type=%d.\n",
  1381. type, sp, sp->type);
  1382. sp->done(sp, 0);
  1383. return;
  1384. }
  1385. break;
  1386. case SRB_CT_PTHRU_CMD:
  1387. /* borrowing sts_entry_24xx.comp_status.
  1388. same location as ct_entry_24xx.comp_status
  1389. */
  1390. res = qla2x00_chk_ms_status(sp->vha, (ms_iocb_entry_t *)pkt,
  1391. (struct ct_sns_rsp *)sp->u.iocb_cmd.u.ctarg.rsp,
  1392. sp->name);
  1393. sp->done(sp, res);
  1394. return;
  1395. default:
  1396. ql_dbg(ql_dbg_user, vha, 0x503e,
  1397. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1398. return;
  1399. }
  1400. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1401. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1402. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1403. if (iocb_type == ELS_IOCB_TYPE) {
  1404. els = &sp->u.iocb_cmd;
  1405. els->u.els_plogi.fw_status[0] = fw_status[0];
  1406. els->u.els_plogi.fw_status[1] = fw_status[1];
  1407. els->u.els_plogi.fw_status[2] = fw_status[2];
  1408. els->u.els_plogi.comp_status = fw_status[0];
  1409. if (comp_status == CS_COMPLETE) {
  1410. res = DID_OK << 16;
  1411. } else {
  1412. if (comp_status == CS_DATA_UNDERRUN) {
  1413. res = DID_OK << 16;
  1414. els->u.els_plogi.len =
  1415. le16_to_cpu(((struct els_sts_entry_24xx *)
  1416. pkt)->total_byte_count);
  1417. } else {
  1418. els->u.els_plogi.len = 0;
  1419. res = DID_ERROR << 16;
  1420. }
  1421. }
  1422. ql_log(ql_log_info, vha, 0x503f,
  1423. "ELS IOCB Done -%s error hdl=%x comp_status=0x%x error subcode 1=0x%x error subcode 2=0x%x total_byte=0x%x\n",
  1424. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1425. le16_to_cpu(((struct els_sts_entry_24xx *)
  1426. pkt)->total_byte_count));
  1427. goto els_ct_done;
  1428. }
  1429. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1430. * fc payload to the caller
  1431. */
  1432. bsg_job = sp->u.bsg_job;
  1433. bsg_reply = bsg_job->reply;
  1434. bsg_reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1435. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1436. if (comp_status != CS_COMPLETE) {
  1437. if (comp_status == CS_DATA_UNDERRUN) {
  1438. res = DID_OK << 16;
  1439. bsg_reply->reply_payload_rcv_len =
  1440. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1441. ql_dbg(ql_dbg_user, vha, 0x503f,
  1442. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1443. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1444. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1445. le16_to_cpu(((struct els_sts_entry_24xx *)
  1446. pkt)->total_byte_count));
  1447. } else {
  1448. ql_dbg(ql_dbg_user, vha, 0x5040,
  1449. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1450. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1451. type, sp->handle, comp_status,
  1452. le16_to_cpu(((struct els_sts_entry_24xx *)
  1453. pkt)->error_subcode_1),
  1454. le16_to_cpu(((struct els_sts_entry_24xx *)
  1455. pkt)->error_subcode_2));
  1456. res = DID_ERROR << 16;
  1457. bsg_reply->reply_payload_rcv_len = 0;
  1458. }
  1459. memcpy(bsg_job->reply + sizeof(struct fc_bsg_reply),
  1460. fw_status, sizeof(fw_status));
  1461. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1462. (uint8_t *)pkt, sizeof(*pkt));
  1463. }
  1464. else {
  1465. res = DID_OK << 16;
  1466. bsg_reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1467. bsg_job->reply_len = 0;
  1468. }
  1469. els_ct_done:
  1470. sp->done(sp, res);
  1471. }
  1472. static void
  1473. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1474. struct logio_entry_24xx *logio)
  1475. {
  1476. const char func[] = "LOGIO-IOCB";
  1477. const char *type;
  1478. fc_port_t *fcport;
  1479. srb_t *sp;
  1480. struct srb_iocb *lio;
  1481. uint16_t *data;
  1482. uint32_t iop[2];
  1483. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1484. if (!sp)
  1485. return;
  1486. lio = &sp->u.iocb_cmd;
  1487. type = sp->name;
  1488. fcport = sp->fcport;
  1489. data = lio->u.logio.data;
  1490. data[0] = MBS_COMMAND_ERROR;
  1491. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1492. QLA_LOGIO_LOGIN_RETRIED : 0;
  1493. if (logio->entry_status) {
  1494. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1495. "Async-%s error entry - %8phC hdl=%x"
  1496. "portid=%02x%02x%02x entry-status=%x.\n",
  1497. type, fcport->port_name, sp->handle, fcport->d_id.b.domain,
  1498. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1499. logio->entry_status);
  1500. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1501. (uint8_t *)logio, sizeof(*logio));
  1502. goto logio_done;
  1503. }
  1504. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1505. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1506. "Async-%s complete - %8phC hdl=%x portid=%02x%02x%02x "
  1507. "iop0=%x.\n", type, fcport->port_name, sp->handle,
  1508. fcport->d_id.b.domain,
  1509. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1510. le32_to_cpu(logio->io_parameter[0]));
  1511. vha->hw->exch_starvation = 0;
  1512. data[0] = MBS_COMMAND_COMPLETE;
  1513. if (sp->type != SRB_LOGIN_CMD)
  1514. goto logio_done;
  1515. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1516. if (iop[0] & BIT_4) {
  1517. fcport->port_type = FCT_TARGET;
  1518. if (iop[0] & BIT_8)
  1519. fcport->flags |= FCF_FCP2_DEVICE;
  1520. } else if (iop[0] & BIT_5)
  1521. fcport->port_type = FCT_INITIATOR;
  1522. if (iop[0] & BIT_7)
  1523. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1524. if (logio->io_parameter[7] || logio->io_parameter[8])
  1525. fcport->supported_classes |= FC_COS_CLASS2;
  1526. if (logio->io_parameter[9] || logio->io_parameter[10])
  1527. fcport->supported_classes |= FC_COS_CLASS3;
  1528. goto logio_done;
  1529. }
  1530. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1531. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1532. lio->u.logio.iop[0] = iop[0];
  1533. lio->u.logio.iop[1] = iop[1];
  1534. switch (iop[0]) {
  1535. case LSC_SCODE_PORTID_USED:
  1536. data[0] = MBS_PORT_ID_USED;
  1537. data[1] = LSW(iop[1]);
  1538. break;
  1539. case LSC_SCODE_NPORT_USED:
  1540. data[0] = MBS_LOOP_ID_USED;
  1541. break;
  1542. case LSC_SCODE_CMD_FAILED:
  1543. if (iop[1] == 0x0606) {
  1544. /*
  1545. * PLOGI/PRLI Completed. We must have Recv PLOGI/PRLI,
  1546. * Target side acked.
  1547. */
  1548. data[0] = MBS_COMMAND_COMPLETE;
  1549. goto logio_done;
  1550. }
  1551. data[0] = MBS_COMMAND_ERROR;
  1552. break;
  1553. case LSC_SCODE_NOXCB:
  1554. vha->hw->exch_starvation++;
  1555. if (vha->hw->exch_starvation > 5) {
  1556. ql_log(ql_log_warn, vha, 0xd046,
  1557. "Exchange starvation. Resetting RISC\n");
  1558. vha->hw->exch_starvation = 0;
  1559. if (IS_P3P_TYPE(vha->hw))
  1560. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1561. else
  1562. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1563. qla2xxx_wake_dpc(vha);
  1564. }
  1565. /* fall through */
  1566. default:
  1567. data[0] = MBS_COMMAND_ERROR;
  1568. break;
  1569. }
  1570. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1571. "Async-%s failed - %8phC hdl=%x portid=%02x%02x%02x comp=%x "
  1572. "iop0=%x iop1=%x.\n", type, fcport->port_name,
  1573. sp->handle, fcport->d_id.b.domain,
  1574. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1575. le16_to_cpu(logio->comp_status),
  1576. le32_to_cpu(logio->io_parameter[0]),
  1577. le32_to_cpu(logio->io_parameter[1]));
  1578. logio_done:
  1579. sp->done(sp, 0);
  1580. }
  1581. static void
  1582. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
  1583. {
  1584. const char func[] = "TMF-IOCB";
  1585. const char *type;
  1586. fc_port_t *fcport;
  1587. srb_t *sp;
  1588. struct srb_iocb *iocb;
  1589. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1590. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1591. if (!sp)
  1592. return;
  1593. iocb = &sp->u.iocb_cmd;
  1594. type = sp->name;
  1595. fcport = sp->fcport;
  1596. iocb->u.tmf.data = QLA_SUCCESS;
  1597. if (sts->entry_status) {
  1598. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1599. "Async-%s error - hdl=%x entry-status(%x).\n",
  1600. type, sp->handle, sts->entry_status);
  1601. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1602. } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
  1603. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1604. "Async-%s error - hdl=%x completion status(%x).\n",
  1605. type, sp->handle, sts->comp_status);
  1606. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1607. } else if ((le16_to_cpu(sts->scsi_status) &
  1608. SS_RESPONSE_INFO_LEN_VALID)) {
  1609. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1610. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1611. "Async-%s error - hdl=%x not enough response(%d).\n",
  1612. type, sp->handle, sts->rsp_data_len);
  1613. } else if (sts->data[3]) {
  1614. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1615. "Async-%s error - hdl=%x response(%x).\n",
  1616. type, sp->handle, sts->data[3]);
  1617. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1618. }
  1619. }
  1620. if (iocb->u.tmf.data != QLA_SUCCESS)
  1621. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1622. (uint8_t *)sts, sizeof(*sts));
  1623. sp->done(sp, 0);
  1624. }
  1625. static void qla24xx_nvme_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1626. void *tsk, srb_t *sp)
  1627. {
  1628. fc_port_t *fcport;
  1629. struct srb_iocb *iocb;
  1630. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1631. uint16_t state_flags;
  1632. struct nvmefc_fcp_req *fd;
  1633. uint16_t ret = 0;
  1634. iocb = &sp->u.iocb_cmd;
  1635. fcport = sp->fcport;
  1636. iocb->u.nvme.comp_status = le16_to_cpu(sts->comp_status);
  1637. state_flags = le16_to_cpu(sts->state_flags);
  1638. fd = iocb->u.nvme.desc;
  1639. if (unlikely(iocb->u.nvme.aen_op))
  1640. atomic_dec(&sp->vha->hw->nvme_active_aen_cnt);
  1641. /*
  1642. * State flags: Bit 6 and 0.
  1643. * If 0 is set, we don't care about 6.
  1644. * both cases resp was dma'd to host buffer
  1645. * if both are 0, that is good path case.
  1646. * if six is set and 0 is clear, we need to
  1647. * copy resp data from status iocb to resp buffer.
  1648. */
  1649. if (!(state_flags & (SF_FCP_RSP_DMA | SF_NVME_ERSP))) {
  1650. iocb->u.nvme.rsp_pyld_len = 0;
  1651. } else if ((state_flags & SF_FCP_RSP_DMA)) {
  1652. iocb->u.nvme.rsp_pyld_len = le16_to_cpu(sts->nvme_rsp_pyld_len);
  1653. } else if (state_flags & SF_NVME_ERSP) {
  1654. uint32_t *inbuf, *outbuf;
  1655. uint16_t iter;
  1656. inbuf = (uint32_t *)&sts->nvme_ersp_data;
  1657. outbuf = (uint32_t *)fd->rspaddr;
  1658. iocb->u.nvme.rsp_pyld_len = le16_to_cpu(sts->nvme_rsp_pyld_len);
  1659. if (unlikely(iocb->u.nvme.rsp_pyld_len >
  1660. sizeof(struct nvme_fc_ersp_iu))) {
  1661. if (ql_mask_match(ql_dbg_io)) {
  1662. WARN_ONCE(1, "Unexpected response payload length %u.\n",
  1663. iocb->u.nvme.rsp_pyld_len);
  1664. ql_log(ql_log_warn, fcport->vha, 0x5100,
  1665. "Unexpected response payload length %u.\n",
  1666. iocb->u.nvme.rsp_pyld_len);
  1667. }
  1668. iocb->u.nvme.rsp_pyld_len =
  1669. sizeof(struct nvme_fc_ersp_iu);
  1670. }
  1671. iter = iocb->u.nvme.rsp_pyld_len >> 2;
  1672. for (; iter; iter--)
  1673. *outbuf++ = swab32(*inbuf++);
  1674. } else { /* unhandled case */
  1675. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1676. "NVME-%s error. Unhandled state_flags of %x\n",
  1677. sp->name, state_flags);
  1678. }
  1679. fd->transferred_length = fd->payload_length -
  1680. le32_to_cpu(sts->residual_len);
  1681. switch (le16_to_cpu(sts->comp_status)) {
  1682. case CS_COMPLETE:
  1683. ret = QLA_SUCCESS;
  1684. break;
  1685. case CS_ABORTED:
  1686. case CS_RESET:
  1687. case CS_PORT_UNAVAILABLE:
  1688. case CS_PORT_LOGGED_OUT:
  1689. case CS_PORT_BUSY:
  1690. ql_log(ql_log_warn, fcport->vha, 0x5060,
  1691. "NVME-%s ERR Handling - hdl=%x completion status(%x) resid=%x ox_id=%x\n",
  1692. sp->name, sp->handle, sts->comp_status,
  1693. le32_to_cpu(sts->residual_len), sts->ox_id);
  1694. fd->transferred_length = 0;
  1695. iocb->u.nvme.rsp_pyld_len = 0;
  1696. ret = QLA_ABORTED;
  1697. break;
  1698. default:
  1699. ql_log(ql_log_warn, fcport->vha, 0x5060,
  1700. "NVME-%s error - hdl=%x completion status(%x) resid=%x ox_id=%x\n",
  1701. sp->name, sp->handle, sts->comp_status,
  1702. le32_to_cpu(sts->residual_len), sts->ox_id);
  1703. ret = QLA_FUNCTION_FAILED;
  1704. break;
  1705. }
  1706. sp->done(sp, ret);
  1707. }
  1708. static void qla_ctrlvp_completed(scsi_qla_host_t *vha, struct req_que *req,
  1709. struct vp_ctrl_entry_24xx *vce)
  1710. {
  1711. const char func[] = "CTRLVP-IOCB";
  1712. srb_t *sp;
  1713. int rval = QLA_SUCCESS;
  1714. sp = qla2x00_get_sp_from_handle(vha, func, req, vce);
  1715. if (!sp)
  1716. return;
  1717. if (vce->entry_status != 0) {
  1718. ql_dbg(ql_dbg_vport, vha, 0x10c4,
  1719. "%s: Failed to complete IOCB -- error status (%x)\n",
  1720. sp->name, vce->entry_status);
  1721. rval = QLA_FUNCTION_FAILED;
  1722. } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) {
  1723. ql_dbg(ql_dbg_vport, vha, 0x10c5,
  1724. "%s: Failed to complete IOCB -- completion status (%x) vpidx %x\n",
  1725. sp->name, le16_to_cpu(vce->comp_status),
  1726. le16_to_cpu(vce->vp_idx_failed));
  1727. rval = QLA_FUNCTION_FAILED;
  1728. } else {
  1729. ql_dbg(ql_dbg_vport, vha, 0x10c6,
  1730. "Done %s.\n", __func__);
  1731. }
  1732. sp->rc = rval;
  1733. sp->done(sp, rval);
  1734. }
  1735. /**
  1736. * qla2x00_process_response_queue() - Process response queue entries.
  1737. * @rsp: response queue
  1738. */
  1739. void
  1740. qla2x00_process_response_queue(struct rsp_que *rsp)
  1741. {
  1742. struct scsi_qla_host *vha;
  1743. struct qla_hw_data *ha = rsp->hw;
  1744. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1745. sts_entry_t *pkt;
  1746. uint16_t handle_cnt;
  1747. uint16_t cnt;
  1748. vha = pci_get_drvdata(ha->pdev);
  1749. if (!vha->flags.online)
  1750. return;
  1751. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1752. pkt = (sts_entry_t *)rsp->ring_ptr;
  1753. rsp->ring_index++;
  1754. if (rsp->ring_index == rsp->length) {
  1755. rsp->ring_index = 0;
  1756. rsp->ring_ptr = rsp->ring;
  1757. } else {
  1758. rsp->ring_ptr++;
  1759. }
  1760. if (pkt->entry_status != 0) {
  1761. qla2x00_error_entry(vha, rsp, pkt);
  1762. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1763. wmb();
  1764. continue;
  1765. }
  1766. switch (pkt->entry_type) {
  1767. case STATUS_TYPE:
  1768. qla2x00_status_entry(vha, rsp, pkt);
  1769. break;
  1770. case STATUS_TYPE_21:
  1771. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1772. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1773. qla2x00_process_completed_request(vha, rsp->req,
  1774. ((sts21_entry_t *)pkt)->handle[cnt]);
  1775. }
  1776. break;
  1777. case STATUS_TYPE_22:
  1778. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1779. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1780. qla2x00_process_completed_request(vha, rsp->req,
  1781. ((sts22_entry_t *)pkt)->handle[cnt]);
  1782. }
  1783. break;
  1784. case STATUS_CONT_TYPE:
  1785. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1786. break;
  1787. case MBX_IOCB_TYPE:
  1788. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1789. (struct mbx_entry *)pkt);
  1790. break;
  1791. case CT_IOCB_TYPE:
  1792. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1793. break;
  1794. default:
  1795. /* Type Not Supported. */
  1796. ql_log(ql_log_warn, vha, 0x504a,
  1797. "Received unknown response pkt type %x "
  1798. "entry status=%x.\n",
  1799. pkt->entry_type, pkt->entry_status);
  1800. break;
  1801. }
  1802. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1803. wmb();
  1804. }
  1805. /* Adjust ring index */
  1806. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1807. }
  1808. static inline void
  1809. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1810. uint32_t sense_len, struct rsp_que *rsp, int res)
  1811. {
  1812. struct scsi_qla_host *vha = sp->vha;
  1813. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1814. uint32_t track_sense_len;
  1815. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1816. sense_len = SCSI_SENSE_BUFFERSIZE;
  1817. SET_CMD_SENSE_LEN(sp, sense_len);
  1818. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1819. track_sense_len = sense_len;
  1820. if (sense_len > par_sense_len)
  1821. sense_len = par_sense_len;
  1822. memcpy(cp->sense_buffer, sense_data, sense_len);
  1823. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1824. track_sense_len -= sense_len;
  1825. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1826. if (track_sense_len != 0) {
  1827. rsp->status_srb = sp;
  1828. cp->result = res;
  1829. }
  1830. if (sense_len) {
  1831. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1832. "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
  1833. sp->vha->host_no, cp->device->id, cp->device->lun,
  1834. cp);
  1835. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1836. cp->sense_buffer, sense_len);
  1837. }
  1838. }
  1839. struct scsi_dif_tuple {
  1840. __be16 guard; /* Checksum */
  1841. __be16 app_tag; /* APPL identifier */
  1842. __be32 ref_tag; /* Target LBA or indirect LBA */
  1843. };
  1844. /*
  1845. * Checks the guard or meta-data for the type of error
  1846. * detected by the HBA. In case of errors, we set the
  1847. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1848. * to indicate to the kernel that the HBA detected error.
  1849. */
  1850. static inline int
  1851. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1852. {
  1853. struct scsi_qla_host *vha = sp->vha;
  1854. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1855. uint8_t *ap = &sts24->data[12];
  1856. uint8_t *ep = &sts24->data[20];
  1857. uint32_t e_ref_tag, a_ref_tag;
  1858. uint16_t e_app_tag, a_app_tag;
  1859. uint16_t e_guard, a_guard;
  1860. /*
  1861. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1862. * would make guard field appear at offset 2
  1863. */
  1864. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1865. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1866. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1867. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1868. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1869. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1870. ql_dbg(ql_dbg_io, vha, 0x3023,
  1871. "iocb(s) %p Returned STATUS.\n", sts24);
  1872. ql_dbg(ql_dbg_io, vha, 0x3024,
  1873. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1874. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1875. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1876. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1877. a_app_tag, e_app_tag, a_guard, e_guard);
  1878. /*
  1879. * Ignore sector if:
  1880. * For type 3: ref & app tag is all 'f's
  1881. * For type 0,1,2: app tag is all 'f's
  1882. */
  1883. if ((a_app_tag == T10_PI_APP_ESCAPE) &&
  1884. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1885. (a_ref_tag == T10_PI_REF_ESCAPE))) {
  1886. uint32_t blocks_done, resid;
  1887. sector_t lba_s = scsi_get_lba(cmd);
  1888. /* 2TB boundary case covered automatically with this */
  1889. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1890. resid = scsi_bufflen(cmd) - (blocks_done *
  1891. cmd->device->sector_size);
  1892. scsi_set_resid(cmd, resid);
  1893. cmd->result = DID_OK << 16;
  1894. /* Update protection tag */
  1895. if (scsi_prot_sg_count(cmd)) {
  1896. uint32_t i, j = 0, k = 0, num_ent;
  1897. struct scatterlist *sg;
  1898. struct t10_pi_tuple *spt;
  1899. /* Patch the corresponding protection tags */
  1900. scsi_for_each_prot_sg(cmd, sg,
  1901. scsi_prot_sg_count(cmd), i) {
  1902. num_ent = sg_dma_len(sg) / 8;
  1903. if (k + num_ent < blocks_done) {
  1904. k += num_ent;
  1905. continue;
  1906. }
  1907. j = blocks_done - k - 1;
  1908. k = blocks_done;
  1909. break;
  1910. }
  1911. if (k != blocks_done) {
  1912. ql_log(ql_log_warn, vha, 0x302f,
  1913. "unexpected tag values tag:lba=%x:%llx)\n",
  1914. e_ref_tag, (unsigned long long)lba_s);
  1915. return 1;
  1916. }
  1917. spt = page_address(sg_page(sg)) + sg->offset;
  1918. spt += j;
  1919. spt->app_tag = T10_PI_APP_ESCAPE;
  1920. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1921. spt->ref_tag = T10_PI_REF_ESCAPE;
  1922. }
  1923. return 0;
  1924. }
  1925. /* check guard */
  1926. if (e_guard != a_guard) {
  1927. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1928. 0x10, 0x1);
  1929. set_driver_byte(cmd, DRIVER_SENSE);
  1930. set_host_byte(cmd, DID_ABORT);
  1931. cmd->result |= SAM_STAT_CHECK_CONDITION;
  1932. return 1;
  1933. }
  1934. /* check ref tag */
  1935. if (e_ref_tag != a_ref_tag) {
  1936. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1937. 0x10, 0x3);
  1938. set_driver_byte(cmd, DRIVER_SENSE);
  1939. set_host_byte(cmd, DID_ABORT);
  1940. cmd->result |= SAM_STAT_CHECK_CONDITION;
  1941. return 1;
  1942. }
  1943. /* check appl tag */
  1944. if (e_app_tag != a_app_tag) {
  1945. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1946. 0x10, 0x2);
  1947. set_driver_byte(cmd, DRIVER_SENSE);
  1948. set_host_byte(cmd, DID_ABORT);
  1949. cmd->result |= SAM_STAT_CHECK_CONDITION;
  1950. return 1;
  1951. }
  1952. return 1;
  1953. }
  1954. static void
  1955. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1956. struct req_que *req, uint32_t index)
  1957. {
  1958. struct qla_hw_data *ha = vha->hw;
  1959. srb_t *sp;
  1960. uint16_t comp_status;
  1961. uint16_t scsi_status;
  1962. uint16_t thread_id;
  1963. uint32_t rval = EXT_STATUS_OK;
  1964. struct bsg_job *bsg_job = NULL;
  1965. struct fc_bsg_request *bsg_request;
  1966. struct fc_bsg_reply *bsg_reply;
  1967. sts_entry_t *sts;
  1968. struct sts_entry_24xx *sts24;
  1969. sts = (sts_entry_t *) pkt;
  1970. sts24 = (struct sts_entry_24xx *) pkt;
  1971. /* Validate handle. */
  1972. if (index >= req->num_outstanding_cmds) {
  1973. ql_log(ql_log_warn, vha, 0x70af,
  1974. "Invalid SCSI completion handle 0x%x.\n", index);
  1975. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1976. return;
  1977. }
  1978. sp = req->outstanding_cmds[index];
  1979. if (!sp) {
  1980. ql_log(ql_log_warn, vha, 0x70b0,
  1981. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1982. req->id, index);
  1983. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1984. return;
  1985. }
  1986. /* Free outstanding command slot. */
  1987. req->outstanding_cmds[index] = NULL;
  1988. bsg_job = sp->u.bsg_job;
  1989. bsg_request = bsg_job->request;
  1990. bsg_reply = bsg_job->reply;
  1991. if (IS_FWI2_CAPABLE(ha)) {
  1992. comp_status = le16_to_cpu(sts24->comp_status);
  1993. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1994. } else {
  1995. comp_status = le16_to_cpu(sts->comp_status);
  1996. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1997. }
  1998. thread_id = bsg_request->rqst_data.h_vendor.vendor_cmd[1];
  1999. switch (comp_status) {
  2000. case CS_COMPLETE:
  2001. if (scsi_status == 0) {
  2002. bsg_reply->reply_payload_rcv_len =
  2003. bsg_job->reply_payload.payload_len;
  2004. vha->qla_stats.input_bytes +=
  2005. bsg_reply->reply_payload_rcv_len;
  2006. vha->qla_stats.input_requests++;
  2007. rval = EXT_STATUS_OK;
  2008. }
  2009. goto done;
  2010. case CS_DATA_OVERRUN:
  2011. ql_dbg(ql_dbg_user, vha, 0x70b1,
  2012. "Command completed with data overrun thread_id=%d\n",
  2013. thread_id);
  2014. rval = EXT_STATUS_DATA_OVERRUN;
  2015. break;
  2016. case CS_DATA_UNDERRUN:
  2017. ql_dbg(ql_dbg_user, vha, 0x70b2,
  2018. "Command completed with data underrun thread_id=%d\n",
  2019. thread_id);
  2020. rval = EXT_STATUS_DATA_UNDERRUN;
  2021. break;
  2022. case CS_BIDIR_RD_OVERRUN:
  2023. ql_dbg(ql_dbg_user, vha, 0x70b3,
  2024. "Command completed with read data overrun thread_id=%d\n",
  2025. thread_id);
  2026. rval = EXT_STATUS_DATA_OVERRUN;
  2027. break;
  2028. case CS_BIDIR_RD_WR_OVERRUN:
  2029. ql_dbg(ql_dbg_user, vha, 0x70b4,
  2030. "Command completed with read and write data overrun "
  2031. "thread_id=%d\n", thread_id);
  2032. rval = EXT_STATUS_DATA_OVERRUN;
  2033. break;
  2034. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  2035. ql_dbg(ql_dbg_user, vha, 0x70b5,
  2036. "Command completed with read data over and write data "
  2037. "underrun thread_id=%d\n", thread_id);
  2038. rval = EXT_STATUS_DATA_OVERRUN;
  2039. break;
  2040. case CS_BIDIR_RD_UNDERRUN:
  2041. ql_dbg(ql_dbg_user, vha, 0x70b6,
  2042. "Command completed with read data underrun "
  2043. "thread_id=%d\n", thread_id);
  2044. rval = EXT_STATUS_DATA_UNDERRUN;
  2045. break;
  2046. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  2047. ql_dbg(ql_dbg_user, vha, 0x70b7,
  2048. "Command completed with read data under and write data "
  2049. "overrun thread_id=%d\n", thread_id);
  2050. rval = EXT_STATUS_DATA_UNDERRUN;
  2051. break;
  2052. case CS_BIDIR_RD_WR_UNDERRUN:
  2053. ql_dbg(ql_dbg_user, vha, 0x70b8,
  2054. "Command completed with read and write data underrun "
  2055. "thread_id=%d\n", thread_id);
  2056. rval = EXT_STATUS_DATA_UNDERRUN;
  2057. break;
  2058. case CS_BIDIR_DMA:
  2059. ql_dbg(ql_dbg_user, vha, 0x70b9,
  2060. "Command completed with data DMA error thread_id=%d\n",
  2061. thread_id);
  2062. rval = EXT_STATUS_DMA_ERR;
  2063. break;
  2064. case CS_TIMEOUT:
  2065. ql_dbg(ql_dbg_user, vha, 0x70ba,
  2066. "Command completed with timeout thread_id=%d\n",
  2067. thread_id);
  2068. rval = EXT_STATUS_TIMEOUT;
  2069. break;
  2070. default:
  2071. ql_dbg(ql_dbg_user, vha, 0x70bb,
  2072. "Command completed with completion status=0x%x "
  2073. "thread_id=%d\n", comp_status, thread_id);
  2074. rval = EXT_STATUS_ERR;
  2075. break;
  2076. }
  2077. bsg_reply->reply_payload_rcv_len = 0;
  2078. done:
  2079. /* Return the vendor specific reply to API */
  2080. bsg_reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  2081. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  2082. /* Always return DID_OK, bsg will send the vendor specific response
  2083. * in this case only */
  2084. sp->done(sp, DID_OK << 16);
  2085. }
  2086. /**
  2087. * qla2x00_status_entry() - Process a Status IOCB entry.
  2088. * @vha: SCSI driver HA context
  2089. * @rsp: response queue
  2090. * @pkt: Entry pointer
  2091. */
  2092. static void
  2093. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  2094. {
  2095. srb_t *sp;
  2096. fc_port_t *fcport;
  2097. struct scsi_cmnd *cp;
  2098. sts_entry_t *sts;
  2099. struct sts_entry_24xx *sts24;
  2100. uint16_t comp_status;
  2101. uint16_t scsi_status;
  2102. uint16_t ox_id;
  2103. uint8_t lscsi_status;
  2104. int32_t resid;
  2105. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  2106. fw_resid_len;
  2107. uint8_t *rsp_info, *sense_data;
  2108. struct qla_hw_data *ha = vha->hw;
  2109. uint32_t handle;
  2110. uint16_t que;
  2111. struct req_que *req;
  2112. int logit = 1;
  2113. int res = 0;
  2114. uint16_t state_flags = 0;
  2115. uint16_t retry_delay = 0;
  2116. sts = (sts_entry_t *) pkt;
  2117. sts24 = (struct sts_entry_24xx *) pkt;
  2118. if (IS_FWI2_CAPABLE(ha)) {
  2119. comp_status = le16_to_cpu(sts24->comp_status);
  2120. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  2121. state_flags = le16_to_cpu(sts24->state_flags);
  2122. } else {
  2123. comp_status = le16_to_cpu(sts->comp_status);
  2124. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  2125. }
  2126. handle = (uint32_t) LSW(sts->handle);
  2127. que = MSW(sts->handle);
  2128. req = ha->req_q_map[que];
  2129. /* Check for invalid queue pointer */
  2130. if (req == NULL ||
  2131. que >= find_first_zero_bit(ha->req_qid_map, ha->max_req_queues)) {
  2132. ql_dbg(ql_dbg_io, vha, 0x3059,
  2133. "Invalid status handle (0x%x): Bad req pointer. req=%p, "
  2134. "que=%u.\n", sts->handle, req, que);
  2135. return;
  2136. }
  2137. /* Validate handle. */
  2138. if (handle < req->num_outstanding_cmds) {
  2139. sp = req->outstanding_cmds[handle];
  2140. if (!sp) {
  2141. ql_dbg(ql_dbg_io, vha, 0x3075,
  2142. "%s(%ld): Already returned command for status handle (0x%x).\n",
  2143. __func__, vha->host_no, sts->handle);
  2144. return;
  2145. }
  2146. } else {
  2147. ql_dbg(ql_dbg_io, vha, 0x3017,
  2148. "Invalid status handle, out of range (0x%x).\n",
  2149. sts->handle);
  2150. if (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
  2151. if (IS_P3P_TYPE(ha))
  2152. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2153. else
  2154. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2155. qla2xxx_wake_dpc(vha);
  2156. }
  2157. return;
  2158. }
  2159. if (sp->cmd_type != TYPE_SRB) {
  2160. req->outstanding_cmds[handle] = NULL;
  2161. ql_dbg(ql_dbg_io, vha, 0x3015,
  2162. "Unknown sp->cmd_type %x %p).\n",
  2163. sp->cmd_type, sp);
  2164. return;
  2165. }
  2166. /* NVME completion. */
  2167. if (sp->type == SRB_NVME_CMD) {
  2168. req->outstanding_cmds[handle] = NULL;
  2169. qla24xx_nvme_iocb_entry(vha, req, pkt, sp);
  2170. return;
  2171. }
  2172. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  2173. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  2174. return;
  2175. }
  2176. /* Task Management completion. */
  2177. if (sp->type == SRB_TM_CMD) {
  2178. qla24xx_tm_iocb_entry(vha, req, pkt);
  2179. return;
  2180. }
  2181. /* Fast path completion. */
  2182. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  2183. qla2x00_process_completed_request(vha, req, handle);
  2184. return;
  2185. }
  2186. req->outstanding_cmds[handle] = NULL;
  2187. cp = GET_CMD_SP(sp);
  2188. if (cp == NULL) {
  2189. ql_dbg(ql_dbg_io, vha, 0x3018,
  2190. "Command already returned (0x%x/%p).\n",
  2191. sts->handle, sp);
  2192. return;
  2193. }
  2194. lscsi_status = scsi_status & STATUS_MASK;
  2195. fcport = sp->fcport;
  2196. ox_id = 0;
  2197. sense_len = par_sense_len = rsp_info_len = resid_len =
  2198. fw_resid_len = 0;
  2199. if (IS_FWI2_CAPABLE(ha)) {
  2200. if (scsi_status & SS_SENSE_LEN_VALID)
  2201. sense_len = le32_to_cpu(sts24->sense_len);
  2202. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  2203. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  2204. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  2205. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  2206. if (comp_status == CS_DATA_UNDERRUN)
  2207. fw_resid_len = le32_to_cpu(sts24->residual_len);
  2208. rsp_info = sts24->data;
  2209. sense_data = sts24->data;
  2210. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  2211. ox_id = le16_to_cpu(sts24->ox_id);
  2212. par_sense_len = sizeof(sts24->data);
  2213. /* Valid values of the retry delay timer are 0x1-0xffef */
  2214. if (sts24->retry_delay > 0 && sts24->retry_delay < 0xfff1) {
  2215. retry_delay = sts24->retry_delay & 0x3fff;
  2216. ql_dbg(ql_dbg_io, sp->vha, 0x3033,
  2217. "%s: scope=%#x retry_delay=%#x\n", __func__,
  2218. sts24->retry_delay >> 14, retry_delay);
  2219. }
  2220. } else {
  2221. if (scsi_status & SS_SENSE_LEN_VALID)
  2222. sense_len = le16_to_cpu(sts->req_sense_length);
  2223. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  2224. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  2225. resid_len = le32_to_cpu(sts->residual_length);
  2226. rsp_info = sts->rsp_info;
  2227. sense_data = sts->req_sense_data;
  2228. par_sense_len = sizeof(sts->req_sense_data);
  2229. }
  2230. /* Check for any FCP transport errors. */
  2231. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  2232. /* Sense data lies beyond any FCP RESPONSE data. */
  2233. if (IS_FWI2_CAPABLE(ha)) {
  2234. sense_data += rsp_info_len;
  2235. par_sense_len -= rsp_info_len;
  2236. }
  2237. if (rsp_info_len > 3 && rsp_info[3]) {
  2238. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  2239. "FCP I/O protocol failure (0x%x/0x%x).\n",
  2240. rsp_info_len, rsp_info[3]);
  2241. res = DID_BUS_BUSY << 16;
  2242. goto out;
  2243. }
  2244. }
  2245. /* Check for overrun. */
  2246. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  2247. scsi_status & SS_RESIDUAL_OVER)
  2248. comp_status = CS_DATA_OVERRUN;
  2249. /*
  2250. * Check retry_delay_timer value if we receive a busy or
  2251. * queue full.
  2252. */
  2253. if (lscsi_status == SAM_STAT_TASK_SET_FULL ||
  2254. lscsi_status == SAM_STAT_BUSY)
  2255. qla2x00_set_retry_delay_timestamp(fcport, retry_delay);
  2256. /*
  2257. * Based on Host and scsi status generate status code for Linux
  2258. */
  2259. switch (comp_status) {
  2260. case CS_COMPLETE:
  2261. case CS_QUEUE_FULL:
  2262. if (scsi_status == 0) {
  2263. res = DID_OK << 16;
  2264. break;
  2265. }
  2266. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  2267. resid = resid_len;
  2268. scsi_set_resid(cp, resid);
  2269. if (!lscsi_status &&
  2270. ((unsigned)(scsi_bufflen(cp) - resid) <
  2271. cp->underflow)) {
  2272. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  2273. "Mid-layer underflow detected (0x%x of 0x%x bytes).\n",
  2274. resid, scsi_bufflen(cp));
  2275. res = DID_ERROR << 16;
  2276. break;
  2277. }
  2278. }
  2279. res = DID_OK << 16 | lscsi_status;
  2280. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  2281. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  2282. "QUEUE FULL detected.\n");
  2283. break;
  2284. }
  2285. logit = 0;
  2286. if (lscsi_status != SS_CHECK_CONDITION)
  2287. break;
  2288. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2289. if (!(scsi_status & SS_SENSE_LEN_VALID))
  2290. break;
  2291. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2292. rsp, res);
  2293. break;
  2294. case CS_DATA_UNDERRUN:
  2295. /* Use F/W calculated residual length. */
  2296. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  2297. scsi_set_resid(cp, resid);
  2298. if (scsi_status & SS_RESIDUAL_UNDER) {
  2299. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  2300. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  2301. "Dropped frame(s) detected (0x%x of 0x%x bytes).\n",
  2302. resid, scsi_bufflen(cp));
  2303. res = DID_ERROR << 16 | lscsi_status;
  2304. goto check_scsi_status;
  2305. }
  2306. if (!lscsi_status &&
  2307. ((unsigned)(scsi_bufflen(cp) - resid) <
  2308. cp->underflow)) {
  2309. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  2310. "Mid-layer underflow detected (0x%x of 0x%x bytes).\n",
  2311. resid, scsi_bufflen(cp));
  2312. res = DID_ERROR << 16;
  2313. break;
  2314. }
  2315. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  2316. lscsi_status != SAM_STAT_BUSY) {
  2317. /*
  2318. * scsi status of task set and busy are considered to be
  2319. * task not completed.
  2320. */
  2321. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  2322. "Dropped frame(s) detected (0x%x of 0x%x bytes).\n",
  2323. resid, scsi_bufflen(cp));
  2324. res = DID_ERROR << 16 | lscsi_status;
  2325. goto check_scsi_status;
  2326. } else {
  2327. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  2328. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2329. scsi_status, lscsi_status);
  2330. }
  2331. res = DID_OK << 16 | lscsi_status;
  2332. logit = 0;
  2333. check_scsi_status:
  2334. /*
  2335. * Check to see if SCSI Status is non zero. If so report SCSI
  2336. * Status.
  2337. */
  2338. if (lscsi_status != 0) {
  2339. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  2340. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  2341. "QUEUE FULL detected.\n");
  2342. logit = 1;
  2343. break;
  2344. }
  2345. if (lscsi_status != SS_CHECK_CONDITION)
  2346. break;
  2347. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2348. if (!(scsi_status & SS_SENSE_LEN_VALID))
  2349. break;
  2350. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  2351. sense_len, rsp, res);
  2352. }
  2353. break;
  2354. case CS_PORT_LOGGED_OUT:
  2355. case CS_PORT_CONFIG_CHG:
  2356. case CS_PORT_BUSY:
  2357. case CS_INCOMPLETE:
  2358. case CS_PORT_UNAVAILABLE:
  2359. case CS_TIMEOUT:
  2360. case CS_RESET:
  2361. /*
  2362. * We are going to have the fc class block the rport
  2363. * while we try to recover so instruct the mid layer
  2364. * to requeue until the class decides how to handle this.
  2365. */
  2366. res = DID_TRANSPORT_DISRUPTED << 16;
  2367. if (comp_status == CS_TIMEOUT) {
  2368. if (IS_FWI2_CAPABLE(ha))
  2369. break;
  2370. else if ((le16_to_cpu(sts->status_flags) &
  2371. SF_LOGOUT_SENT) == 0)
  2372. break;
  2373. }
  2374. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  2375. ql_dbg(ql_dbg_disc, fcport->vha, 0x3021,
  2376. "Port to be marked lost on fcport=%02x%02x%02x, current "
  2377. "port state= %s comp_status %x.\n", fcport->d_id.b.domain,
  2378. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  2379. port_state_str[atomic_read(&fcport->state)],
  2380. comp_status);
  2381. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2382. qlt_schedule_sess_for_deletion(fcport);
  2383. }
  2384. break;
  2385. case CS_ABORTED:
  2386. res = DID_RESET << 16;
  2387. break;
  2388. case CS_DIF_ERROR:
  2389. logit = qla2x00_handle_dif_error(sp, sts24);
  2390. res = cp->result;
  2391. break;
  2392. case CS_TRANSPORT:
  2393. res = DID_ERROR << 16;
  2394. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  2395. break;
  2396. if (state_flags & BIT_4)
  2397. scmd_printk(KERN_WARNING, cp,
  2398. "Unsupported device '%s' found.\n",
  2399. cp->device->vendor);
  2400. break;
  2401. default:
  2402. res = DID_ERROR << 16;
  2403. break;
  2404. }
  2405. out:
  2406. if (logit)
  2407. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  2408. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
  2409. "portid=%02x%02x%02x oxid=0x%x cdb=%10phN len=0x%x "
  2410. "rsp_info=0x%x resid=0x%x fw_resid=0x%x sp=%p cp=%p.\n",
  2411. comp_status, scsi_status, res, vha->host_no,
  2412. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  2413. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  2414. cp->cmnd, scsi_bufflen(cp), rsp_info_len,
  2415. resid_len, fw_resid_len, sp, cp);
  2416. if (rsp->status_srb == NULL)
  2417. sp->done(sp, res);
  2418. }
  2419. /**
  2420. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  2421. * @rsp: response queue
  2422. * @pkt: Entry pointer
  2423. *
  2424. * Extended sense data.
  2425. */
  2426. static void
  2427. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2428. {
  2429. uint8_t sense_sz = 0;
  2430. struct qla_hw_data *ha = rsp->hw;
  2431. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2432. srb_t *sp = rsp->status_srb;
  2433. struct scsi_cmnd *cp;
  2434. uint32_t sense_len;
  2435. uint8_t *sense_ptr;
  2436. if (!sp || !GET_CMD_SENSE_LEN(sp))
  2437. return;
  2438. sense_len = GET_CMD_SENSE_LEN(sp);
  2439. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2440. cp = GET_CMD_SP(sp);
  2441. if (cp == NULL) {
  2442. ql_log(ql_log_warn, vha, 0x3025,
  2443. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2444. rsp->status_srb = NULL;
  2445. return;
  2446. }
  2447. if (sense_len > sizeof(pkt->data))
  2448. sense_sz = sizeof(pkt->data);
  2449. else
  2450. sense_sz = sense_len;
  2451. /* Move sense data. */
  2452. if (IS_FWI2_CAPABLE(ha))
  2453. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  2454. memcpy(sense_ptr, pkt->data, sense_sz);
  2455. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  2456. sense_ptr, sense_sz);
  2457. sense_len -= sense_sz;
  2458. sense_ptr += sense_sz;
  2459. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2460. SET_CMD_SENSE_LEN(sp, sense_len);
  2461. /* Place command on done queue. */
  2462. if (sense_len == 0) {
  2463. rsp->status_srb = NULL;
  2464. sp->done(sp, cp->result);
  2465. }
  2466. }
  2467. /**
  2468. * qla2x00_error_entry() - Process an error entry.
  2469. * @vha: SCSI driver HA context
  2470. * @rsp: response queue
  2471. * @pkt: Entry pointer
  2472. * return : 1=allow further error analysis. 0=no additional error analysis.
  2473. */
  2474. static int
  2475. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2476. {
  2477. srb_t *sp;
  2478. struct qla_hw_data *ha = vha->hw;
  2479. const char func[] = "ERROR-IOCB";
  2480. uint16_t que = MSW(pkt->handle);
  2481. struct req_que *req = NULL;
  2482. int res = DID_ERROR << 16;
  2483. ql_dbg(ql_dbg_async, vha, 0x502a,
  2484. "iocb type %xh with error status %xh, handle %xh, rspq id %d\n",
  2485. pkt->entry_type, pkt->entry_status, pkt->handle, rsp->id);
  2486. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2487. goto fatal;
  2488. req = ha->req_q_map[que];
  2489. if (pkt->entry_status & RF_BUSY)
  2490. res = DID_BUS_BUSY << 16;
  2491. if ((pkt->handle & ~QLA_TGT_HANDLE_MASK) == QLA_TGT_SKIP_HANDLE)
  2492. return 0;
  2493. switch (pkt->entry_type) {
  2494. case NOTIFY_ACK_TYPE:
  2495. case STATUS_TYPE:
  2496. case STATUS_CONT_TYPE:
  2497. case LOGINOUT_PORT_IOCB_TYPE:
  2498. case CT_IOCB_TYPE:
  2499. case ELS_IOCB_TYPE:
  2500. case ABORT_IOCB_TYPE:
  2501. case MBX_IOCB_TYPE:
  2502. default:
  2503. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2504. if (sp) {
  2505. sp->done(sp, res);
  2506. return 0;
  2507. }
  2508. break;
  2509. case ABTS_RESP_24XX:
  2510. case CTIO_TYPE7:
  2511. case CTIO_CRC2:
  2512. return 1;
  2513. }
  2514. fatal:
  2515. ql_log(ql_log_warn, vha, 0x5030,
  2516. "Error entry - invalid handle/queue (%04x).\n", que);
  2517. return 0;
  2518. }
  2519. /**
  2520. * qla24xx_mbx_completion() - Process mailbox command completions.
  2521. * @vha: SCSI driver HA context
  2522. * @mb0: Mailbox0 register
  2523. */
  2524. static void
  2525. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2526. {
  2527. uint16_t cnt;
  2528. uint32_t mboxes;
  2529. uint16_t __iomem *wptr;
  2530. struct qla_hw_data *ha = vha->hw;
  2531. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2532. /* Read all mbox registers? */
  2533. WARN_ON_ONCE(ha->mbx_count > 32);
  2534. mboxes = (1ULL << ha->mbx_count) - 1;
  2535. if (!ha->mcp)
  2536. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2537. else
  2538. mboxes = ha->mcp->in_mb;
  2539. /* Load return mailbox registers. */
  2540. ha->flags.mbox_int = 1;
  2541. ha->mailbox_out[0] = mb0;
  2542. mboxes >>= 1;
  2543. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2544. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2545. if (mboxes & BIT_0)
  2546. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2547. mboxes >>= 1;
  2548. wptr++;
  2549. }
  2550. }
  2551. static void
  2552. qla24xx_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  2553. struct abort_entry_24xx *pkt)
  2554. {
  2555. const char func[] = "ABT_IOCB";
  2556. srb_t *sp;
  2557. struct srb_iocb *abt;
  2558. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2559. if (!sp)
  2560. return;
  2561. abt = &sp->u.iocb_cmd;
  2562. abt->u.abt.comp_status = le16_to_cpu(pkt->nport_handle);
  2563. sp->done(sp, 0);
  2564. }
  2565. void qla24xx_nvme_ls4_iocb(struct scsi_qla_host *vha,
  2566. struct pt_ls4_request *pkt, struct req_que *req)
  2567. {
  2568. srb_t *sp;
  2569. const char func[] = "LS4_IOCB";
  2570. uint16_t comp_status;
  2571. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2572. if (!sp)
  2573. return;
  2574. comp_status = le16_to_cpu(pkt->status);
  2575. sp->done(sp, comp_status);
  2576. }
  2577. /**
  2578. * qla24xx_process_response_queue() - Process response queue entries.
  2579. * @vha: SCSI driver HA context
  2580. * @rsp: response queue
  2581. */
  2582. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2583. struct rsp_que *rsp)
  2584. {
  2585. struct sts_entry_24xx *pkt;
  2586. struct qla_hw_data *ha = vha->hw;
  2587. if (!ha->flags.fw_started)
  2588. return;
  2589. if (rsp->qpair->cpuid != smp_processor_id())
  2590. qla_cpu_update(rsp->qpair, smp_processor_id());
  2591. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2592. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2593. rsp->ring_index++;
  2594. if (rsp->ring_index == rsp->length) {
  2595. rsp->ring_index = 0;
  2596. rsp->ring_ptr = rsp->ring;
  2597. } else {
  2598. rsp->ring_ptr++;
  2599. }
  2600. if (pkt->entry_status != 0) {
  2601. if (qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt))
  2602. goto process_err;
  2603. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2604. wmb();
  2605. continue;
  2606. }
  2607. process_err:
  2608. switch (pkt->entry_type) {
  2609. case STATUS_TYPE:
  2610. qla2x00_status_entry(vha, rsp, pkt);
  2611. break;
  2612. case STATUS_CONT_TYPE:
  2613. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2614. break;
  2615. case VP_RPT_ID_IOCB_TYPE:
  2616. qla24xx_report_id_acquisition(vha,
  2617. (struct vp_rpt_id_entry_24xx *)pkt);
  2618. break;
  2619. case LOGINOUT_PORT_IOCB_TYPE:
  2620. qla24xx_logio_entry(vha, rsp->req,
  2621. (struct logio_entry_24xx *)pkt);
  2622. break;
  2623. case CT_IOCB_TYPE:
  2624. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2625. break;
  2626. case ELS_IOCB_TYPE:
  2627. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2628. break;
  2629. case ABTS_RECV_24XX:
  2630. if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  2631. /* ensure that the ATIO queue is empty */
  2632. qlt_handle_abts_recv(vha, rsp,
  2633. (response_t *)pkt);
  2634. break;
  2635. } else {
  2636. qlt_24xx_process_atio_queue(vha, 1);
  2637. }
  2638. /* fall through */
  2639. case ABTS_RESP_24XX:
  2640. case CTIO_TYPE7:
  2641. case CTIO_CRC2:
  2642. qlt_response_pkt_all_vps(vha, rsp, (response_t *)pkt);
  2643. break;
  2644. case PT_LS4_REQUEST:
  2645. qla24xx_nvme_ls4_iocb(vha, (struct pt_ls4_request *)pkt,
  2646. rsp->req);
  2647. break;
  2648. case NOTIFY_ACK_TYPE:
  2649. if (pkt->handle == QLA_TGT_SKIP_HANDLE)
  2650. qlt_response_pkt_all_vps(vha, rsp,
  2651. (response_t *)pkt);
  2652. else
  2653. qla24xxx_nack_iocb_entry(vha, rsp->req,
  2654. (struct nack_to_isp *)pkt);
  2655. break;
  2656. case MARKER_TYPE:
  2657. /* Do nothing in this case, this check is to prevent it
  2658. * from falling into default case
  2659. */
  2660. break;
  2661. case ABORT_IOCB_TYPE:
  2662. qla24xx_abort_iocb_entry(vha, rsp->req,
  2663. (struct abort_entry_24xx *)pkt);
  2664. break;
  2665. case MBX_IOCB_TYPE:
  2666. qla24xx_mbx_iocb_entry(vha, rsp->req,
  2667. (struct mbx_24xx_entry *)pkt);
  2668. break;
  2669. case VP_CTRL_IOCB_TYPE:
  2670. qla_ctrlvp_completed(vha, rsp->req,
  2671. (struct vp_ctrl_entry_24xx *)pkt);
  2672. break;
  2673. default:
  2674. /* Type Not Supported. */
  2675. ql_dbg(ql_dbg_async, vha, 0x5042,
  2676. "Received unknown response pkt type %x "
  2677. "entry status=%x.\n",
  2678. pkt->entry_type, pkt->entry_status);
  2679. break;
  2680. }
  2681. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2682. wmb();
  2683. }
  2684. /* Adjust ring index */
  2685. if (IS_P3P_TYPE(ha)) {
  2686. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2687. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2688. } else {
  2689. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2690. }
  2691. }
  2692. static void
  2693. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2694. {
  2695. int rval;
  2696. uint32_t cnt;
  2697. struct qla_hw_data *ha = vha->hw;
  2698. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2699. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
  2700. !IS_QLA27XX(ha))
  2701. return;
  2702. rval = QLA_SUCCESS;
  2703. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2704. RD_REG_DWORD(&reg->iobase_addr);
  2705. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2706. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2707. rval == QLA_SUCCESS; cnt--) {
  2708. if (cnt) {
  2709. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2710. udelay(10);
  2711. } else
  2712. rval = QLA_FUNCTION_TIMEOUT;
  2713. }
  2714. if (rval == QLA_SUCCESS)
  2715. goto next_test;
  2716. rval = QLA_SUCCESS;
  2717. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2718. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2719. rval == QLA_SUCCESS; cnt--) {
  2720. if (cnt) {
  2721. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2722. udelay(10);
  2723. } else
  2724. rval = QLA_FUNCTION_TIMEOUT;
  2725. }
  2726. if (rval != QLA_SUCCESS)
  2727. goto done;
  2728. next_test:
  2729. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2730. ql_log(ql_log_info, vha, 0x504c,
  2731. "Additional code -- 0x55AA.\n");
  2732. done:
  2733. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2734. RD_REG_DWORD(&reg->iobase_window);
  2735. }
  2736. /**
  2737. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2738. * @irq:
  2739. * @dev_id: SCSI driver HA context
  2740. *
  2741. * Called by system whenever the host adapter generates an interrupt.
  2742. *
  2743. * Returns handled flag.
  2744. */
  2745. irqreturn_t
  2746. qla24xx_intr_handler(int irq, void *dev_id)
  2747. {
  2748. scsi_qla_host_t *vha;
  2749. struct qla_hw_data *ha;
  2750. struct device_reg_24xx __iomem *reg;
  2751. int status;
  2752. unsigned long iter;
  2753. uint32_t stat;
  2754. uint32_t hccr;
  2755. uint16_t mb[8];
  2756. struct rsp_que *rsp;
  2757. unsigned long flags;
  2758. bool process_atio = false;
  2759. rsp = (struct rsp_que *) dev_id;
  2760. if (!rsp) {
  2761. ql_log(ql_log_info, NULL, 0x5059,
  2762. "%s: NULL response queue pointer.\n", __func__);
  2763. return IRQ_NONE;
  2764. }
  2765. ha = rsp->hw;
  2766. reg = &ha->iobase->isp24;
  2767. status = 0;
  2768. if (unlikely(pci_channel_offline(ha->pdev)))
  2769. return IRQ_HANDLED;
  2770. spin_lock_irqsave(&ha->hardware_lock, flags);
  2771. vha = pci_get_drvdata(ha->pdev);
  2772. for (iter = 50; iter--; ) {
  2773. stat = RD_REG_DWORD(&reg->host_status);
  2774. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2775. break;
  2776. if (stat & HSRX_RISC_PAUSED) {
  2777. if (unlikely(pci_channel_offline(ha->pdev)))
  2778. break;
  2779. hccr = RD_REG_DWORD(&reg->hccr);
  2780. ql_log(ql_log_warn, vha, 0x504b,
  2781. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2782. hccr);
  2783. qla2xxx_check_risc_status(vha);
  2784. ha->isp_ops->fw_dump(vha, 1);
  2785. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2786. break;
  2787. } else if ((stat & HSRX_RISC_INT) == 0)
  2788. break;
  2789. switch (stat & 0xff) {
  2790. case INTR_ROM_MB_SUCCESS:
  2791. case INTR_ROM_MB_FAILED:
  2792. case INTR_MB_SUCCESS:
  2793. case INTR_MB_FAILED:
  2794. qla24xx_mbx_completion(vha, MSW(stat));
  2795. status |= MBX_INTERRUPT;
  2796. break;
  2797. case INTR_ASYNC_EVENT:
  2798. mb[0] = MSW(stat);
  2799. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2800. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2801. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2802. qla2x00_async_event(vha, rsp, mb);
  2803. break;
  2804. case INTR_RSP_QUE_UPDATE:
  2805. case INTR_RSP_QUE_UPDATE_83XX:
  2806. qla24xx_process_response_queue(vha, rsp);
  2807. break;
  2808. case INTR_ATIO_QUE_UPDATE_27XX:
  2809. case INTR_ATIO_QUE_UPDATE:
  2810. process_atio = true;
  2811. break;
  2812. case INTR_ATIO_RSP_QUE_UPDATE:
  2813. process_atio = true;
  2814. qla24xx_process_response_queue(vha, rsp);
  2815. break;
  2816. default:
  2817. ql_dbg(ql_dbg_async, vha, 0x504f,
  2818. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2819. break;
  2820. }
  2821. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2822. RD_REG_DWORD_RELAXED(&reg->hccr);
  2823. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2824. ndelay(3500);
  2825. }
  2826. qla2x00_handle_mbx_completion(ha, status);
  2827. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2828. if (process_atio) {
  2829. spin_lock_irqsave(&ha->tgt.atio_lock, flags);
  2830. qlt_24xx_process_atio_queue(vha, 0);
  2831. spin_unlock_irqrestore(&ha->tgt.atio_lock, flags);
  2832. }
  2833. return IRQ_HANDLED;
  2834. }
  2835. static irqreturn_t
  2836. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2837. {
  2838. struct qla_hw_data *ha;
  2839. struct rsp_que *rsp;
  2840. struct device_reg_24xx __iomem *reg;
  2841. struct scsi_qla_host *vha;
  2842. unsigned long flags;
  2843. rsp = (struct rsp_que *) dev_id;
  2844. if (!rsp) {
  2845. ql_log(ql_log_info, NULL, 0x505a,
  2846. "%s: NULL response queue pointer.\n", __func__);
  2847. return IRQ_NONE;
  2848. }
  2849. ha = rsp->hw;
  2850. reg = &ha->iobase->isp24;
  2851. spin_lock_irqsave(&ha->hardware_lock, flags);
  2852. vha = pci_get_drvdata(ha->pdev);
  2853. qla24xx_process_response_queue(vha, rsp);
  2854. if (!ha->flags.disable_msix_handshake) {
  2855. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2856. RD_REG_DWORD_RELAXED(&reg->hccr);
  2857. }
  2858. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2859. return IRQ_HANDLED;
  2860. }
  2861. static irqreturn_t
  2862. qla24xx_msix_default(int irq, void *dev_id)
  2863. {
  2864. scsi_qla_host_t *vha;
  2865. struct qla_hw_data *ha;
  2866. struct rsp_que *rsp;
  2867. struct device_reg_24xx __iomem *reg;
  2868. int status;
  2869. uint32_t stat;
  2870. uint32_t hccr;
  2871. uint16_t mb[8];
  2872. unsigned long flags;
  2873. bool process_atio = false;
  2874. rsp = (struct rsp_que *) dev_id;
  2875. if (!rsp) {
  2876. ql_log(ql_log_info, NULL, 0x505c,
  2877. "%s: NULL response queue pointer.\n", __func__);
  2878. return IRQ_NONE;
  2879. }
  2880. ha = rsp->hw;
  2881. reg = &ha->iobase->isp24;
  2882. status = 0;
  2883. spin_lock_irqsave(&ha->hardware_lock, flags);
  2884. vha = pci_get_drvdata(ha->pdev);
  2885. do {
  2886. stat = RD_REG_DWORD(&reg->host_status);
  2887. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2888. break;
  2889. if (stat & HSRX_RISC_PAUSED) {
  2890. if (unlikely(pci_channel_offline(ha->pdev)))
  2891. break;
  2892. hccr = RD_REG_DWORD(&reg->hccr);
  2893. ql_log(ql_log_info, vha, 0x5050,
  2894. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2895. hccr);
  2896. qla2xxx_check_risc_status(vha);
  2897. ha->isp_ops->fw_dump(vha, 1);
  2898. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2899. break;
  2900. } else if ((stat & HSRX_RISC_INT) == 0)
  2901. break;
  2902. switch (stat & 0xff) {
  2903. case INTR_ROM_MB_SUCCESS:
  2904. case INTR_ROM_MB_FAILED:
  2905. case INTR_MB_SUCCESS:
  2906. case INTR_MB_FAILED:
  2907. qla24xx_mbx_completion(vha, MSW(stat));
  2908. status |= MBX_INTERRUPT;
  2909. break;
  2910. case INTR_ASYNC_EVENT:
  2911. mb[0] = MSW(stat);
  2912. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2913. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2914. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2915. qla2x00_async_event(vha, rsp, mb);
  2916. break;
  2917. case INTR_RSP_QUE_UPDATE:
  2918. case INTR_RSP_QUE_UPDATE_83XX:
  2919. qla24xx_process_response_queue(vha, rsp);
  2920. break;
  2921. case INTR_ATIO_QUE_UPDATE_27XX:
  2922. case INTR_ATIO_QUE_UPDATE:
  2923. process_atio = true;
  2924. break;
  2925. case INTR_ATIO_RSP_QUE_UPDATE:
  2926. process_atio = true;
  2927. qla24xx_process_response_queue(vha, rsp);
  2928. break;
  2929. default:
  2930. ql_dbg(ql_dbg_async, vha, 0x5051,
  2931. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2932. break;
  2933. }
  2934. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2935. } while (0);
  2936. qla2x00_handle_mbx_completion(ha, status);
  2937. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2938. if (process_atio) {
  2939. spin_lock_irqsave(&ha->tgt.atio_lock, flags);
  2940. qlt_24xx_process_atio_queue(vha, 0);
  2941. spin_unlock_irqrestore(&ha->tgt.atio_lock, flags);
  2942. }
  2943. return IRQ_HANDLED;
  2944. }
  2945. irqreturn_t
  2946. qla2xxx_msix_rsp_q(int irq, void *dev_id)
  2947. {
  2948. struct qla_hw_data *ha;
  2949. struct qla_qpair *qpair;
  2950. struct device_reg_24xx __iomem *reg;
  2951. unsigned long flags;
  2952. qpair = dev_id;
  2953. if (!qpair) {
  2954. ql_log(ql_log_info, NULL, 0x505b,
  2955. "%s: NULL response queue pointer.\n", __func__);
  2956. return IRQ_NONE;
  2957. }
  2958. ha = qpair->hw;
  2959. /* Clear the interrupt, if enabled, for this response queue */
  2960. if (unlikely(!ha->flags.disable_msix_handshake)) {
  2961. reg = &ha->iobase->isp24;
  2962. spin_lock_irqsave(&ha->hardware_lock, flags);
  2963. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2964. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2965. }
  2966. queue_work(ha->wq, &qpair->q_work);
  2967. return IRQ_HANDLED;
  2968. }
  2969. /* Interrupt handling helpers. */
  2970. struct qla_init_msix_entry {
  2971. const char *name;
  2972. irq_handler_t handler;
  2973. };
  2974. static const struct qla_init_msix_entry msix_entries[] = {
  2975. { "default", qla24xx_msix_default },
  2976. { "rsp_q", qla24xx_msix_rsp_q },
  2977. { "atio_q", qla83xx_msix_atio_q },
  2978. { "qpair_multiq", qla2xxx_msix_rsp_q },
  2979. };
  2980. static const struct qla_init_msix_entry qla82xx_msix_entries[] = {
  2981. { "qla2xxx (default)", qla82xx_msix_default },
  2982. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2983. };
  2984. static int
  2985. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2986. {
  2987. int i, ret;
  2988. struct qla_msix_entry *qentry;
  2989. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2990. int min_vecs = QLA_BASE_VECTORS;
  2991. struct irq_affinity desc = {
  2992. .pre_vectors = QLA_BASE_VECTORS,
  2993. };
  2994. if (QLA_TGT_MODE_ENABLED() && (ql2xenablemsix != 0) &&
  2995. IS_ATIO_MSIX_CAPABLE(ha)) {
  2996. desc.pre_vectors++;
  2997. min_vecs++;
  2998. }
  2999. if (USER_CTRL_IRQ(ha)) {
  3000. /* user wants to control IRQ setting for target mode */
  3001. ret = pci_alloc_irq_vectors(ha->pdev, min_vecs,
  3002. ha->msix_count, PCI_IRQ_MSIX);
  3003. } else
  3004. ret = pci_alloc_irq_vectors_affinity(ha->pdev, min_vecs,
  3005. ha->msix_count, PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
  3006. &desc);
  3007. if (ret < 0) {
  3008. ql_log(ql_log_fatal, vha, 0x00c7,
  3009. "MSI-X: Failed to enable support, "
  3010. "giving up -- %d/%d.\n",
  3011. ha->msix_count, ret);
  3012. goto msix_out;
  3013. } else if (ret < ha->msix_count) {
  3014. ql_log(ql_log_info, vha, 0x00c6,
  3015. "MSI-X: Using %d vectors\n", ret);
  3016. ha->msix_count = ret;
  3017. /* Recalculate queue values */
  3018. if (ha->mqiobase && (ql2xmqsupport || ql2xnvmeenable)) {
  3019. ha->max_req_queues = ha->msix_count - 1;
  3020. /* ATIOQ needs 1 vector. That's 1 less QPair */
  3021. if (QLA_TGT_MODE_ENABLED())
  3022. ha->max_req_queues--;
  3023. ha->max_rsp_queues = ha->max_req_queues;
  3024. ha->max_qpairs = ha->max_req_queues - 1;
  3025. ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
  3026. "Adjusted Max no of queues pairs: %d.\n", ha->max_qpairs);
  3027. }
  3028. }
  3029. ha->msix_entries = kcalloc(ha->msix_count,
  3030. sizeof(struct qla_msix_entry),
  3031. GFP_KERNEL);
  3032. if (!ha->msix_entries) {
  3033. ql_log(ql_log_fatal, vha, 0x00c8,
  3034. "Failed to allocate memory for ha->msix_entries.\n");
  3035. ret = -ENOMEM;
  3036. goto free_irqs;
  3037. }
  3038. ha->flags.msix_enabled = 1;
  3039. for (i = 0; i < ha->msix_count; i++) {
  3040. qentry = &ha->msix_entries[i];
  3041. qentry->vector = pci_irq_vector(ha->pdev, i);
  3042. qentry->entry = i;
  3043. qentry->have_irq = 0;
  3044. qentry->in_use = 0;
  3045. qentry->handle = NULL;
  3046. }
  3047. /* Enable MSI-X vectors for the base queue */
  3048. for (i = 0; i < QLA_BASE_VECTORS; i++) {
  3049. qentry = &ha->msix_entries[i];
  3050. qentry->handle = rsp;
  3051. rsp->msix = qentry;
  3052. scnprintf(qentry->name, sizeof(qentry->name),
  3053. "qla2xxx%lu_%s", vha->host_no, msix_entries[i].name);
  3054. if (IS_P3P_TYPE(ha))
  3055. ret = request_irq(qentry->vector,
  3056. qla82xx_msix_entries[i].handler,
  3057. 0, qla82xx_msix_entries[i].name, rsp);
  3058. else
  3059. ret = request_irq(qentry->vector,
  3060. msix_entries[i].handler,
  3061. 0, qentry->name, rsp);
  3062. if (ret)
  3063. goto msix_register_fail;
  3064. qentry->have_irq = 1;
  3065. qentry->in_use = 1;
  3066. }
  3067. /*
  3068. * If target mode is enable, also request the vector for the ATIO
  3069. * queue.
  3070. */
  3071. if (QLA_TGT_MODE_ENABLED() && (ql2xenablemsix != 0) &&
  3072. IS_ATIO_MSIX_CAPABLE(ha)) {
  3073. qentry = &ha->msix_entries[QLA_ATIO_VECTOR];
  3074. rsp->msix = qentry;
  3075. qentry->handle = rsp;
  3076. scnprintf(qentry->name, sizeof(qentry->name),
  3077. "qla2xxx%lu_%s", vha->host_no,
  3078. msix_entries[QLA_ATIO_VECTOR].name);
  3079. qentry->in_use = 1;
  3080. ret = request_irq(qentry->vector,
  3081. msix_entries[QLA_ATIO_VECTOR].handler,
  3082. 0, qentry->name, rsp);
  3083. qentry->have_irq = 1;
  3084. }
  3085. msix_register_fail:
  3086. if (ret) {
  3087. ql_log(ql_log_fatal, vha, 0x00cb,
  3088. "MSI-X: unable to register handler -- %x/%d.\n",
  3089. qentry->vector, ret);
  3090. qla2x00_free_irqs(vha);
  3091. ha->mqenable = 0;
  3092. goto msix_out;
  3093. }
  3094. /* Enable MSI-X vector for response queue update for queue 0 */
  3095. if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  3096. if (ha->msixbase && ha->mqiobase &&
  3097. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1 ||
  3098. ql2xmqsupport))
  3099. ha->mqenable = 1;
  3100. } else
  3101. if (ha->mqiobase &&
  3102. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1 ||
  3103. ql2xmqsupport))
  3104. ha->mqenable = 1;
  3105. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  3106. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  3107. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  3108. ql_dbg(ql_dbg_init, vha, 0x0055,
  3109. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  3110. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  3111. msix_out:
  3112. return ret;
  3113. free_irqs:
  3114. pci_free_irq_vectors(ha->pdev);
  3115. goto msix_out;
  3116. }
  3117. int
  3118. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  3119. {
  3120. int ret = QLA_FUNCTION_FAILED;
  3121. device_reg_t *reg = ha->iobase;
  3122. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  3123. /* If possible, enable MSI-X. */
  3124. if (ql2xenablemsix == 0 || (!IS_QLA2432(ha) && !IS_QLA2532(ha) &&
  3125. !IS_QLA8432(ha) && !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) &&
  3126. !IS_QLAFX00(ha) && !IS_QLA27XX(ha)))
  3127. goto skip_msi;
  3128. if (ql2xenablemsix == 2)
  3129. goto skip_msix;
  3130. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  3131. (ha->pdev->subsystem_device == 0x7040 ||
  3132. ha->pdev->subsystem_device == 0x7041 ||
  3133. ha->pdev->subsystem_device == 0x1705)) {
  3134. ql_log(ql_log_warn, vha, 0x0034,
  3135. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  3136. ha->pdev->subsystem_vendor,
  3137. ha->pdev->subsystem_device);
  3138. goto skip_msi;
  3139. }
  3140. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  3141. ql_log(ql_log_warn, vha, 0x0035,
  3142. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  3143. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  3144. goto skip_msix;
  3145. }
  3146. ret = qla24xx_enable_msix(ha, rsp);
  3147. if (!ret) {
  3148. ql_dbg(ql_dbg_init, vha, 0x0036,
  3149. "MSI-X: Enabled (0x%X, 0x%X).\n",
  3150. ha->chip_revision, ha->fw_attributes);
  3151. goto clear_risc_ints;
  3152. }
  3153. skip_msix:
  3154. ql_log(ql_log_info, vha, 0x0037,
  3155. "Falling back-to MSI mode -- ret=%d.\n", ret);
  3156. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  3157. !IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha) &&
  3158. !IS_QLA27XX(ha))
  3159. goto skip_msi;
  3160. ret = pci_alloc_irq_vectors(ha->pdev, 1, 1, PCI_IRQ_MSI);
  3161. if (ret > 0) {
  3162. ql_dbg(ql_dbg_init, vha, 0x0038,
  3163. "MSI: Enabled.\n");
  3164. ha->flags.msi_enabled = 1;
  3165. } else
  3166. ql_log(ql_log_warn, vha, 0x0039,
  3167. "Falling back-to INTa mode -- ret=%d.\n", ret);
  3168. skip_msi:
  3169. /* Skip INTx on ISP82xx. */
  3170. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  3171. return QLA_FUNCTION_FAILED;
  3172. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  3173. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  3174. QLA2XXX_DRIVER_NAME, rsp);
  3175. if (ret) {
  3176. ql_log(ql_log_warn, vha, 0x003a,
  3177. "Failed to reserve interrupt %d already in use.\n",
  3178. ha->pdev->irq);
  3179. goto fail;
  3180. } else if (!ha->flags.msi_enabled) {
  3181. ql_dbg(ql_dbg_init, vha, 0x0125,
  3182. "INTa mode: Enabled.\n");
  3183. ha->flags.mr_intr_valid = 1;
  3184. }
  3185. clear_risc_ints:
  3186. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  3187. goto fail;
  3188. spin_lock_irq(&ha->hardware_lock);
  3189. WRT_REG_WORD(&reg->isp.semaphore, 0);
  3190. spin_unlock_irq(&ha->hardware_lock);
  3191. fail:
  3192. return ret;
  3193. }
  3194. void
  3195. qla2x00_free_irqs(scsi_qla_host_t *vha)
  3196. {
  3197. struct qla_hw_data *ha = vha->hw;
  3198. struct rsp_que *rsp;
  3199. struct qla_msix_entry *qentry;
  3200. int i;
  3201. /*
  3202. * We need to check that ha->rsp_q_map is valid in case we are called
  3203. * from a probe failure context.
  3204. */
  3205. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  3206. goto free_irqs;
  3207. rsp = ha->rsp_q_map[0];
  3208. if (ha->flags.msix_enabled) {
  3209. for (i = 0; i < ha->msix_count; i++) {
  3210. qentry = &ha->msix_entries[i];
  3211. if (qentry->have_irq) {
  3212. irq_set_affinity_notifier(qentry->vector, NULL);
  3213. free_irq(pci_irq_vector(ha->pdev, i), qentry->handle);
  3214. }
  3215. }
  3216. kfree(ha->msix_entries);
  3217. ha->msix_entries = NULL;
  3218. ha->flags.msix_enabled = 0;
  3219. ql_dbg(ql_dbg_init, vha, 0x0042,
  3220. "Disabled MSI-X.\n");
  3221. } else {
  3222. free_irq(pci_irq_vector(ha->pdev, 0), rsp);
  3223. }
  3224. free_irqs:
  3225. pci_free_irq_vectors(ha->pdev);
  3226. }
  3227. int qla25xx_request_irq(struct qla_hw_data *ha, struct qla_qpair *qpair,
  3228. struct qla_msix_entry *msix, int vector_type)
  3229. {
  3230. const struct qla_init_msix_entry *intr = &msix_entries[vector_type];
  3231. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  3232. int ret;
  3233. scnprintf(msix->name, sizeof(msix->name),
  3234. "qla2xxx%lu_qpair%d", vha->host_no, qpair->id);
  3235. ret = request_irq(msix->vector, intr->handler, 0, msix->name, qpair);
  3236. if (ret) {
  3237. ql_log(ql_log_fatal, vha, 0x00e6,
  3238. "MSI-X: Unable to register handler -- %x/%d.\n",
  3239. msix->vector, ret);
  3240. return ret;
  3241. }
  3242. msix->have_irq = 1;
  3243. msix->handle = qpair;
  3244. return ret;
  3245. }