smartpqi_init.c 201 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248624962506251625262536254625562566257625862596260626162626263626462656266626762686269627062716272627362746275627662776278627962806281628262836284628562866287628862896290629162926293629462956296629762986299630063016302630363046305630663076308630963106311631263136314631563166317631863196320632163226323632463256326632763286329633063316332633363346335633663376338633963406341634263436344634563466347634863496350635163526353635463556356635763586359636063616362636363646365636663676368636963706371637263736374637563766377637863796380638163826383638463856386638763886389639063916392639363946395639663976398639964006401640264036404640564066407640864096410641164126413641464156416641764186419642064216422642364246425642664276428642964306431643264336434643564366437643864396440644164426443644464456446644764486449645064516452645364546455645664576458645964606461646264636464646564666467646864696470647164726473647464756476647764786479648064816482648364846485648664876488648964906491649264936494649564966497649864996500650165026503650465056506650765086509651065116512651365146515651665176518651965206521652265236524652565266527652865296530653165326533653465356536653765386539654065416542654365446545654665476548654965506551655265536554655565566557655865596560656165626563656465656566656765686569657065716572657365746575657665776578657965806581658265836584658565866587658865896590659165926593659465956596659765986599660066016602660366046605660666076608660966106611661266136614661566166617661866196620662166226623662466256626662766286629663066316632663366346635663666376638663966406641664266436644664566466647664866496650665166526653665466556656665766586659666066616662666366646665666666676668666966706671667266736674667566766677667866796680668166826683668466856686668766886689669066916692669366946695669666976698669967006701670267036704670567066707670867096710671167126713671467156716671767186719672067216722672367246725672667276728672967306731673267336734673567366737673867396740674167426743674467456746674767486749675067516752675367546755675667576758675967606761676267636764676567666767676867696770677167726773677467756776677767786779678067816782678367846785678667876788678967906791679267936794679567966797679867996800680168026803680468056806680768086809681068116812681368146815681668176818681968206821682268236824682568266827682868296830683168326833683468356836683768386839684068416842684368446845684668476848684968506851685268536854685568566857685868596860686168626863686468656866686768686869687068716872687368746875687668776878687968806881688268836884688568866887688868896890689168926893689468956896689768986899690069016902690369046905690669076908690969106911691269136914691569166917691869196920692169226923692469256926692769286929693069316932693369346935693669376938693969406941694269436944694569466947694869496950695169526953695469556956695769586959696069616962696369646965696669676968696969706971697269736974697569766977697869796980698169826983698469856986698769886989699069916992699369946995699669976998699970007001700270037004700570067007700870097010701170127013701470157016701770187019702070217022702370247025702670277028702970307031703270337034703570367037703870397040704170427043704470457046704770487049705070517052705370547055705670577058705970607061706270637064706570667067706870697070707170727073707470757076707770787079708070817082708370847085708670877088708970907091709270937094709570967097709870997100710171027103710471057106710771087109711071117112711371147115711671177118711971207121712271237124712571267127712871297130713171327133713471357136713771387139714071417142714371447145714671477148714971507151715271537154715571567157715871597160716171627163716471657166716771687169717071717172717371747175717671777178717971807181718271837184718571867187718871897190719171927193719471957196719771987199720072017202720372047205720672077208720972107211721272137214721572167217721872197220722172227223722472257226722772287229723072317232723372347235723672377238723972407241724272437244724572467247724872497250725172527253725472557256725772587259726072617262726372647265726672677268726972707271727272737274727572767277727872797280728172827283728472857286728772887289729072917292729372947295729672977298729973007301730273037304730573067307730873097310731173127313731473157316731773187319732073217322732373247325732673277328732973307331733273337334733573367337733873397340734173427343734473457346734773487349735073517352735373547355735673577358735973607361736273637364736573667367736873697370737173727373737473757376737773787379738073817382738373847385738673877388738973907391739273937394739573967397739873997400740174027403740474057406740774087409741074117412741374147415741674177418741974207421742274237424742574267427742874297430743174327433743474357436743774387439744074417442744374447445744674477448744974507451745274537454745574567457745874597460746174627463746474657466746774687469747074717472747374747475747674777478747974807481748274837484748574867487748874897490749174927493749474957496749774987499750075017502750375047505750675077508750975107511751275137514751575167517751875197520752175227523752475257526752775287529753075317532753375347535753675377538753975407541754275437544754575467547754875497550755175527553755475557556755775587559
  1. /*
  2. * driver for Microsemi PQI-based storage controllers
  3. * Copyright (c) 2016-2017 Microsemi Corporation
  4. * Copyright (c) 2016 PMC-Sierra, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; version 2 of the License.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13. * NON INFRINGEMENT. See the GNU General Public License for more details.
  14. *
  15. * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
  16. *
  17. */
  18. #include <linux/module.h>
  19. #include <linux/kernel.h>
  20. #include <linux/pci.h>
  21. #include <linux/delay.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/sched.h>
  24. #include <linux/rtc.h>
  25. #include <linux/bcd.h>
  26. #include <linux/reboot.h>
  27. #include <linux/cciss_ioctl.h>
  28. #include <linux/blk-mq-pci.h>
  29. #include <scsi/scsi_host.h>
  30. #include <scsi/scsi_cmnd.h>
  31. #include <scsi/scsi_device.h>
  32. #include <scsi/scsi_eh.h>
  33. #include <scsi/scsi_transport_sas.h>
  34. #include <asm/unaligned.h>
  35. #include "smartpqi.h"
  36. #include "smartpqi_sis.h"
  37. #if !defined(BUILD_TIMESTAMP)
  38. #define BUILD_TIMESTAMP
  39. #endif
  40. #define DRIVER_VERSION "1.1.4-130"
  41. #define DRIVER_MAJOR 1
  42. #define DRIVER_MINOR 1
  43. #define DRIVER_RELEASE 4
  44. #define DRIVER_REVISION 130
  45. #define DRIVER_NAME "Microsemi PQI Driver (v" \
  46. DRIVER_VERSION BUILD_TIMESTAMP ")"
  47. #define DRIVER_NAME_SHORT "smartpqi"
  48. #define PQI_EXTRA_SGL_MEMORY (12 * sizeof(struct pqi_sg_descriptor))
  49. MODULE_AUTHOR("Microsemi");
  50. MODULE_DESCRIPTION("Driver for Microsemi Smart Family Controller version "
  51. DRIVER_VERSION);
  52. MODULE_SUPPORTED_DEVICE("Microsemi Smart Family Controllers");
  53. MODULE_VERSION(DRIVER_VERSION);
  54. MODULE_LICENSE("GPL");
  55. static void pqi_take_ctrl_offline(struct pqi_ctrl_info *ctrl_info);
  56. static void pqi_ctrl_offline_worker(struct work_struct *work);
  57. static void pqi_retry_raid_bypass_requests(struct pqi_ctrl_info *ctrl_info);
  58. static int pqi_scan_scsi_devices(struct pqi_ctrl_info *ctrl_info);
  59. static void pqi_scan_start(struct Scsi_Host *shost);
  60. static void pqi_start_io(struct pqi_ctrl_info *ctrl_info,
  61. struct pqi_queue_group *queue_group, enum pqi_io_path path,
  62. struct pqi_io_request *io_request);
  63. static int pqi_submit_raid_request_synchronous(struct pqi_ctrl_info *ctrl_info,
  64. struct pqi_iu_header *request, unsigned int flags,
  65. struct pqi_raid_error_info *error_info, unsigned long timeout_msecs);
  66. static int pqi_aio_submit_io(struct pqi_ctrl_info *ctrl_info,
  67. struct scsi_cmnd *scmd, u32 aio_handle, u8 *cdb,
  68. unsigned int cdb_length, struct pqi_queue_group *queue_group,
  69. struct pqi_encryption_info *encryption_info, bool raid_bypass);
  70. /* for flags argument to pqi_submit_raid_request_synchronous() */
  71. #define PQI_SYNC_FLAGS_INTERRUPTABLE 0x1
  72. static struct scsi_transport_template *pqi_sas_transport_template;
  73. static atomic_t pqi_controller_count = ATOMIC_INIT(0);
  74. enum pqi_lockup_action {
  75. NONE,
  76. REBOOT,
  77. PANIC
  78. };
  79. static enum pqi_lockup_action pqi_lockup_action = NONE;
  80. static struct {
  81. enum pqi_lockup_action action;
  82. char *name;
  83. } pqi_lockup_actions[] = {
  84. {
  85. .action = NONE,
  86. .name = "none",
  87. },
  88. {
  89. .action = REBOOT,
  90. .name = "reboot",
  91. },
  92. {
  93. .action = PANIC,
  94. .name = "panic",
  95. },
  96. };
  97. static unsigned int pqi_supported_event_types[] = {
  98. PQI_EVENT_TYPE_HOTPLUG,
  99. PQI_EVENT_TYPE_HARDWARE,
  100. PQI_EVENT_TYPE_PHYSICAL_DEVICE,
  101. PQI_EVENT_TYPE_LOGICAL_DEVICE,
  102. PQI_EVENT_TYPE_AIO_STATE_CHANGE,
  103. PQI_EVENT_TYPE_AIO_CONFIG_CHANGE,
  104. };
  105. static int pqi_disable_device_id_wildcards;
  106. module_param_named(disable_device_id_wildcards,
  107. pqi_disable_device_id_wildcards, int, 0644);
  108. MODULE_PARM_DESC(disable_device_id_wildcards,
  109. "Disable device ID wildcards.");
  110. static int pqi_disable_heartbeat;
  111. module_param_named(disable_heartbeat,
  112. pqi_disable_heartbeat, int, 0644);
  113. MODULE_PARM_DESC(disable_heartbeat,
  114. "Disable heartbeat.");
  115. static int pqi_disable_ctrl_shutdown;
  116. module_param_named(disable_ctrl_shutdown,
  117. pqi_disable_ctrl_shutdown, int, 0644);
  118. MODULE_PARM_DESC(disable_ctrl_shutdown,
  119. "Disable controller shutdown when controller locked up.");
  120. static char *pqi_lockup_action_param;
  121. module_param_named(lockup_action,
  122. pqi_lockup_action_param, charp, 0644);
  123. MODULE_PARM_DESC(lockup_action, "Action to take when controller locked up.\n"
  124. "\t\tSupported: none, reboot, panic\n"
  125. "\t\tDefault: none");
  126. static char *raid_levels[] = {
  127. "RAID-0",
  128. "RAID-4",
  129. "RAID-1(1+0)",
  130. "RAID-5",
  131. "RAID-5+1",
  132. "RAID-ADG",
  133. "RAID-1(ADM)",
  134. };
  135. static char *pqi_raid_level_to_string(u8 raid_level)
  136. {
  137. if (raid_level < ARRAY_SIZE(raid_levels))
  138. return raid_levels[raid_level];
  139. return "RAID UNKNOWN";
  140. }
  141. #define SA_RAID_0 0
  142. #define SA_RAID_4 1
  143. #define SA_RAID_1 2 /* also used for RAID 10 */
  144. #define SA_RAID_5 3 /* also used for RAID 50 */
  145. #define SA_RAID_51 4
  146. #define SA_RAID_6 5 /* also used for RAID 60 */
  147. #define SA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
  148. #define SA_RAID_MAX SA_RAID_ADM
  149. #define SA_RAID_UNKNOWN 0xff
  150. static inline void pqi_scsi_done(struct scsi_cmnd *scmd)
  151. {
  152. pqi_prep_for_scsi_done(scmd);
  153. scmd->scsi_done(scmd);
  154. }
  155. static inline bool pqi_scsi3addr_equal(u8 *scsi3addr1, u8 *scsi3addr2)
  156. {
  157. return memcmp(scsi3addr1, scsi3addr2, 8) == 0;
  158. }
  159. static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost)
  160. {
  161. void *hostdata = shost_priv(shost);
  162. return *((struct pqi_ctrl_info **)hostdata);
  163. }
  164. static inline bool pqi_is_logical_device(struct pqi_scsi_dev *device)
  165. {
  166. return !device->is_physical_device;
  167. }
  168. static inline bool pqi_is_external_raid_addr(u8 *scsi3addr)
  169. {
  170. return scsi3addr[2] != 0;
  171. }
  172. static inline bool pqi_ctrl_offline(struct pqi_ctrl_info *ctrl_info)
  173. {
  174. return !ctrl_info->controller_online;
  175. }
  176. static inline void pqi_check_ctrl_health(struct pqi_ctrl_info *ctrl_info)
  177. {
  178. if (ctrl_info->controller_online)
  179. if (!sis_is_firmware_running(ctrl_info))
  180. pqi_take_ctrl_offline(ctrl_info);
  181. }
  182. static inline bool pqi_is_hba_lunid(u8 *scsi3addr)
  183. {
  184. return pqi_scsi3addr_equal(scsi3addr, RAID_CTLR_LUNID);
  185. }
  186. static inline enum pqi_ctrl_mode pqi_get_ctrl_mode(
  187. struct pqi_ctrl_info *ctrl_info)
  188. {
  189. return sis_read_driver_scratch(ctrl_info);
  190. }
  191. static inline void pqi_save_ctrl_mode(struct pqi_ctrl_info *ctrl_info,
  192. enum pqi_ctrl_mode mode)
  193. {
  194. sis_write_driver_scratch(ctrl_info, mode);
  195. }
  196. static inline void pqi_ctrl_block_requests(struct pqi_ctrl_info *ctrl_info)
  197. {
  198. ctrl_info->block_requests = true;
  199. scsi_block_requests(ctrl_info->scsi_host);
  200. }
  201. static inline void pqi_ctrl_unblock_requests(struct pqi_ctrl_info *ctrl_info)
  202. {
  203. ctrl_info->block_requests = false;
  204. wake_up_all(&ctrl_info->block_requests_wait);
  205. pqi_retry_raid_bypass_requests(ctrl_info);
  206. scsi_unblock_requests(ctrl_info->scsi_host);
  207. }
  208. static inline bool pqi_ctrl_blocked(struct pqi_ctrl_info *ctrl_info)
  209. {
  210. return ctrl_info->block_requests;
  211. }
  212. static unsigned long pqi_wait_if_ctrl_blocked(struct pqi_ctrl_info *ctrl_info,
  213. unsigned long timeout_msecs)
  214. {
  215. unsigned long remaining_msecs;
  216. if (!pqi_ctrl_blocked(ctrl_info))
  217. return timeout_msecs;
  218. atomic_inc(&ctrl_info->num_blocked_threads);
  219. if (timeout_msecs == NO_TIMEOUT) {
  220. wait_event(ctrl_info->block_requests_wait,
  221. !pqi_ctrl_blocked(ctrl_info));
  222. remaining_msecs = timeout_msecs;
  223. } else {
  224. unsigned long remaining_jiffies;
  225. remaining_jiffies =
  226. wait_event_timeout(ctrl_info->block_requests_wait,
  227. !pqi_ctrl_blocked(ctrl_info),
  228. msecs_to_jiffies(timeout_msecs));
  229. remaining_msecs = jiffies_to_msecs(remaining_jiffies);
  230. }
  231. atomic_dec(&ctrl_info->num_blocked_threads);
  232. return remaining_msecs;
  233. }
  234. static inline void pqi_ctrl_busy(struct pqi_ctrl_info *ctrl_info)
  235. {
  236. atomic_inc(&ctrl_info->num_busy_threads);
  237. }
  238. static inline void pqi_ctrl_unbusy(struct pqi_ctrl_info *ctrl_info)
  239. {
  240. atomic_dec(&ctrl_info->num_busy_threads);
  241. }
  242. static inline void pqi_ctrl_wait_until_quiesced(struct pqi_ctrl_info *ctrl_info)
  243. {
  244. while (atomic_read(&ctrl_info->num_busy_threads) >
  245. atomic_read(&ctrl_info->num_blocked_threads))
  246. usleep_range(1000, 2000);
  247. }
  248. static inline bool pqi_device_offline(struct pqi_scsi_dev *device)
  249. {
  250. return device->device_offline;
  251. }
  252. static inline void pqi_device_reset_start(struct pqi_scsi_dev *device)
  253. {
  254. device->in_reset = true;
  255. }
  256. static inline void pqi_device_reset_done(struct pqi_scsi_dev *device)
  257. {
  258. device->in_reset = false;
  259. }
  260. static inline bool pqi_device_in_reset(struct pqi_scsi_dev *device)
  261. {
  262. return device->in_reset;
  263. }
  264. static inline void pqi_schedule_rescan_worker_with_delay(
  265. struct pqi_ctrl_info *ctrl_info, unsigned long delay)
  266. {
  267. if (pqi_ctrl_offline(ctrl_info))
  268. return;
  269. schedule_delayed_work(&ctrl_info->rescan_work, delay);
  270. }
  271. static inline void pqi_schedule_rescan_worker(struct pqi_ctrl_info *ctrl_info)
  272. {
  273. pqi_schedule_rescan_worker_with_delay(ctrl_info, 0);
  274. }
  275. #define PQI_RESCAN_WORK_DELAY (10 * HZ)
  276. static inline void pqi_schedule_rescan_worker_delayed(
  277. struct pqi_ctrl_info *ctrl_info)
  278. {
  279. pqi_schedule_rescan_worker_with_delay(ctrl_info, PQI_RESCAN_WORK_DELAY);
  280. }
  281. static inline void pqi_cancel_rescan_worker(struct pqi_ctrl_info *ctrl_info)
  282. {
  283. cancel_delayed_work_sync(&ctrl_info->rescan_work);
  284. }
  285. static inline u32 pqi_read_heartbeat_counter(struct pqi_ctrl_info *ctrl_info)
  286. {
  287. if (!ctrl_info->heartbeat_counter)
  288. return 0;
  289. return readl(ctrl_info->heartbeat_counter);
  290. }
  291. static int pqi_map_single(struct pci_dev *pci_dev,
  292. struct pqi_sg_descriptor *sg_descriptor, void *buffer,
  293. size_t buffer_length, int data_direction)
  294. {
  295. dma_addr_t bus_address;
  296. if (!buffer || buffer_length == 0 || data_direction == PCI_DMA_NONE)
  297. return 0;
  298. bus_address = pci_map_single(pci_dev, buffer, buffer_length,
  299. data_direction);
  300. if (pci_dma_mapping_error(pci_dev, bus_address))
  301. return -ENOMEM;
  302. put_unaligned_le64((u64)bus_address, &sg_descriptor->address);
  303. put_unaligned_le32(buffer_length, &sg_descriptor->length);
  304. put_unaligned_le32(CISS_SG_LAST, &sg_descriptor->flags);
  305. return 0;
  306. }
  307. static void pqi_pci_unmap(struct pci_dev *pci_dev,
  308. struct pqi_sg_descriptor *descriptors, int num_descriptors,
  309. int data_direction)
  310. {
  311. int i;
  312. if (data_direction == PCI_DMA_NONE)
  313. return;
  314. for (i = 0; i < num_descriptors; i++)
  315. pci_unmap_single(pci_dev,
  316. (dma_addr_t)get_unaligned_le64(&descriptors[i].address),
  317. get_unaligned_le32(&descriptors[i].length),
  318. data_direction);
  319. }
  320. static int pqi_build_raid_path_request(struct pqi_ctrl_info *ctrl_info,
  321. struct pqi_raid_path_request *request, u8 cmd,
  322. u8 *scsi3addr, void *buffer, size_t buffer_length,
  323. u16 vpd_page, int *pci_direction)
  324. {
  325. u8 *cdb;
  326. int pci_dir;
  327. memset(request, 0, sizeof(*request));
  328. request->header.iu_type = PQI_REQUEST_IU_RAID_PATH_IO;
  329. put_unaligned_le16(offsetof(struct pqi_raid_path_request,
  330. sg_descriptors[1]) - PQI_REQUEST_HEADER_LENGTH,
  331. &request->header.iu_length);
  332. put_unaligned_le32(buffer_length, &request->buffer_length);
  333. memcpy(request->lun_number, scsi3addr, sizeof(request->lun_number));
  334. request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  335. request->additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_0;
  336. cdb = request->cdb;
  337. switch (cmd) {
  338. case INQUIRY:
  339. request->data_direction = SOP_READ_FLAG;
  340. cdb[0] = INQUIRY;
  341. if (vpd_page & VPD_PAGE) {
  342. cdb[1] = 0x1;
  343. cdb[2] = (u8)vpd_page;
  344. }
  345. cdb[4] = (u8)buffer_length;
  346. break;
  347. case CISS_REPORT_LOG:
  348. case CISS_REPORT_PHYS:
  349. request->data_direction = SOP_READ_FLAG;
  350. cdb[0] = cmd;
  351. if (cmd == CISS_REPORT_PHYS)
  352. cdb[1] = CISS_REPORT_PHYS_EXTENDED;
  353. else
  354. cdb[1] = CISS_REPORT_LOG_EXTENDED;
  355. put_unaligned_be32(buffer_length, &cdb[6]);
  356. break;
  357. case CISS_GET_RAID_MAP:
  358. request->data_direction = SOP_READ_FLAG;
  359. cdb[0] = CISS_READ;
  360. cdb[1] = CISS_GET_RAID_MAP;
  361. put_unaligned_be32(buffer_length, &cdb[6]);
  362. break;
  363. case SA_FLUSH_CACHE:
  364. request->data_direction = SOP_WRITE_FLAG;
  365. cdb[0] = BMIC_WRITE;
  366. cdb[6] = BMIC_FLUSH_CACHE;
  367. put_unaligned_be16(buffer_length, &cdb[7]);
  368. break;
  369. case BMIC_IDENTIFY_CONTROLLER:
  370. case BMIC_IDENTIFY_PHYSICAL_DEVICE:
  371. request->data_direction = SOP_READ_FLAG;
  372. cdb[0] = BMIC_READ;
  373. cdb[6] = cmd;
  374. put_unaligned_be16(buffer_length, &cdb[7]);
  375. break;
  376. case BMIC_WRITE_HOST_WELLNESS:
  377. request->data_direction = SOP_WRITE_FLAG;
  378. cdb[0] = BMIC_WRITE;
  379. cdb[6] = cmd;
  380. put_unaligned_be16(buffer_length, &cdb[7]);
  381. break;
  382. default:
  383. dev_err(&ctrl_info->pci_dev->dev, "unknown command 0x%c\n",
  384. cmd);
  385. break;
  386. }
  387. switch (request->data_direction) {
  388. case SOP_READ_FLAG:
  389. pci_dir = PCI_DMA_FROMDEVICE;
  390. break;
  391. case SOP_WRITE_FLAG:
  392. pci_dir = PCI_DMA_TODEVICE;
  393. break;
  394. case SOP_NO_DIRECTION_FLAG:
  395. pci_dir = PCI_DMA_NONE;
  396. break;
  397. default:
  398. pci_dir = PCI_DMA_BIDIRECTIONAL;
  399. break;
  400. }
  401. *pci_direction = pci_dir;
  402. return pqi_map_single(ctrl_info->pci_dev, &request->sg_descriptors[0],
  403. buffer, buffer_length, pci_dir);
  404. }
  405. static inline void pqi_reinit_io_request(struct pqi_io_request *io_request)
  406. {
  407. io_request->scmd = NULL;
  408. io_request->status = 0;
  409. io_request->error_info = NULL;
  410. io_request->raid_bypass = false;
  411. }
  412. static struct pqi_io_request *pqi_alloc_io_request(
  413. struct pqi_ctrl_info *ctrl_info)
  414. {
  415. struct pqi_io_request *io_request;
  416. u16 i = ctrl_info->next_io_request_slot; /* benignly racy */
  417. while (1) {
  418. io_request = &ctrl_info->io_request_pool[i];
  419. if (atomic_inc_return(&io_request->refcount) == 1)
  420. break;
  421. atomic_dec(&io_request->refcount);
  422. i = (i + 1) % ctrl_info->max_io_slots;
  423. }
  424. /* benignly racy */
  425. ctrl_info->next_io_request_slot = (i + 1) % ctrl_info->max_io_slots;
  426. pqi_reinit_io_request(io_request);
  427. return io_request;
  428. }
  429. static void pqi_free_io_request(struct pqi_io_request *io_request)
  430. {
  431. atomic_dec(&io_request->refcount);
  432. }
  433. static int pqi_identify_controller(struct pqi_ctrl_info *ctrl_info,
  434. struct bmic_identify_controller *buffer)
  435. {
  436. int rc;
  437. int pci_direction;
  438. struct pqi_raid_path_request request;
  439. rc = pqi_build_raid_path_request(ctrl_info, &request,
  440. BMIC_IDENTIFY_CONTROLLER, RAID_CTLR_LUNID, buffer,
  441. sizeof(*buffer), 0, &pci_direction);
  442. if (rc)
  443. return rc;
  444. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0,
  445. NULL, NO_TIMEOUT);
  446. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  447. pci_direction);
  448. return rc;
  449. }
  450. static int pqi_scsi_inquiry(struct pqi_ctrl_info *ctrl_info,
  451. u8 *scsi3addr, u16 vpd_page, void *buffer, size_t buffer_length)
  452. {
  453. int rc;
  454. int pci_direction;
  455. struct pqi_raid_path_request request;
  456. rc = pqi_build_raid_path_request(ctrl_info, &request,
  457. INQUIRY, scsi3addr, buffer, buffer_length, vpd_page,
  458. &pci_direction);
  459. if (rc)
  460. return rc;
  461. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0,
  462. NULL, NO_TIMEOUT);
  463. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  464. pci_direction);
  465. return rc;
  466. }
  467. static int pqi_identify_physical_device(struct pqi_ctrl_info *ctrl_info,
  468. struct pqi_scsi_dev *device,
  469. struct bmic_identify_physical_device *buffer,
  470. size_t buffer_length)
  471. {
  472. int rc;
  473. int pci_direction;
  474. u16 bmic_device_index;
  475. struct pqi_raid_path_request request;
  476. rc = pqi_build_raid_path_request(ctrl_info, &request,
  477. BMIC_IDENTIFY_PHYSICAL_DEVICE, RAID_CTLR_LUNID, buffer,
  478. buffer_length, 0, &pci_direction);
  479. if (rc)
  480. return rc;
  481. bmic_device_index = CISS_GET_DRIVE_NUMBER(device->scsi3addr);
  482. request.cdb[2] = (u8)bmic_device_index;
  483. request.cdb[9] = (u8)(bmic_device_index >> 8);
  484. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header,
  485. 0, NULL, NO_TIMEOUT);
  486. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  487. pci_direction);
  488. return rc;
  489. }
  490. static int pqi_flush_cache(struct pqi_ctrl_info *ctrl_info,
  491. enum bmic_flush_cache_shutdown_event shutdown_event)
  492. {
  493. int rc;
  494. struct pqi_raid_path_request request;
  495. int pci_direction;
  496. struct bmic_flush_cache *flush_cache;
  497. /*
  498. * Don't bother trying to flush the cache if the controller is
  499. * locked up.
  500. */
  501. if (pqi_ctrl_offline(ctrl_info))
  502. return -ENXIO;
  503. flush_cache = kzalloc(sizeof(*flush_cache), GFP_KERNEL);
  504. if (!flush_cache)
  505. return -ENOMEM;
  506. flush_cache->shutdown_event = shutdown_event;
  507. rc = pqi_build_raid_path_request(ctrl_info, &request,
  508. SA_FLUSH_CACHE, RAID_CTLR_LUNID, flush_cache,
  509. sizeof(*flush_cache), 0, &pci_direction);
  510. if (rc)
  511. goto out;
  512. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header,
  513. 0, NULL, NO_TIMEOUT);
  514. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  515. pci_direction);
  516. out:
  517. kfree(flush_cache);
  518. return rc;
  519. }
  520. static int pqi_write_host_wellness(struct pqi_ctrl_info *ctrl_info,
  521. void *buffer, size_t buffer_length)
  522. {
  523. int rc;
  524. struct pqi_raid_path_request request;
  525. int pci_direction;
  526. rc = pqi_build_raid_path_request(ctrl_info, &request,
  527. BMIC_WRITE_HOST_WELLNESS, RAID_CTLR_LUNID, buffer,
  528. buffer_length, 0, &pci_direction);
  529. if (rc)
  530. return rc;
  531. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header,
  532. 0, NULL, NO_TIMEOUT);
  533. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  534. pci_direction);
  535. return rc;
  536. }
  537. #pragma pack(1)
  538. struct bmic_host_wellness_driver_version {
  539. u8 start_tag[4];
  540. u8 driver_version_tag[2];
  541. __le16 driver_version_length;
  542. char driver_version[32];
  543. u8 dont_write_tag[2];
  544. u8 end_tag[2];
  545. };
  546. #pragma pack()
  547. static int pqi_write_driver_version_to_host_wellness(
  548. struct pqi_ctrl_info *ctrl_info)
  549. {
  550. int rc;
  551. struct bmic_host_wellness_driver_version *buffer;
  552. size_t buffer_length;
  553. buffer_length = sizeof(*buffer);
  554. buffer = kmalloc(buffer_length, GFP_KERNEL);
  555. if (!buffer)
  556. return -ENOMEM;
  557. buffer->start_tag[0] = '<';
  558. buffer->start_tag[1] = 'H';
  559. buffer->start_tag[2] = 'W';
  560. buffer->start_tag[3] = '>';
  561. buffer->driver_version_tag[0] = 'D';
  562. buffer->driver_version_tag[1] = 'V';
  563. put_unaligned_le16(sizeof(buffer->driver_version),
  564. &buffer->driver_version_length);
  565. strncpy(buffer->driver_version, "Linux " DRIVER_VERSION,
  566. sizeof(buffer->driver_version) - 1);
  567. buffer->driver_version[sizeof(buffer->driver_version) - 1] = '\0';
  568. buffer->dont_write_tag[0] = 'D';
  569. buffer->dont_write_tag[1] = 'W';
  570. buffer->end_tag[0] = 'Z';
  571. buffer->end_tag[1] = 'Z';
  572. rc = pqi_write_host_wellness(ctrl_info, buffer, buffer_length);
  573. kfree(buffer);
  574. return rc;
  575. }
  576. #pragma pack(1)
  577. struct bmic_host_wellness_time {
  578. u8 start_tag[4];
  579. u8 time_tag[2];
  580. __le16 time_length;
  581. u8 time[8];
  582. u8 dont_write_tag[2];
  583. u8 end_tag[2];
  584. };
  585. #pragma pack()
  586. static int pqi_write_current_time_to_host_wellness(
  587. struct pqi_ctrl_info *ctrl_info)
  588. {
  589. int rc;
  590. struct bmic_host_wellness_time *buffer;
  591. size_t buffer_length;
  592. time64_t local_time;
  593. unsigned int year;
  594. struct tm tm;
  595. buffer_length = sizeof(*buffer);
  596. buffer = kmalloc(buffer_length, GFP_KERNEL);
  597. if (!buffer)
  598. return -ENOMEM;
  599. buffer->start_tag[0] = '<';
  600. buffer->start_tag[1] = 'H';
  601. buffer->start_tag[2] = 'W';
  602. buffer->start_tag[3] = '>';
  603. buffer->time_tag[0] = 'T';
  604. buffer->time_tag[1] = 'D';
  605. put_unaligned_le16(sizeof(buffer->time),
  606. &buffer->time_length);
  607. local_time = ktime_get_real_seconds();
  608. time64_to_tm(local_time, -sys_tz.tz_minuteswest * 60, &tm);
  609. year = tm.tm_year + 1900;
  610. buffer->time[0] = bin2bcd(tm.tm_hour);
  611. buffer->time[1] = bin2bcd(tm.tm_min);
  612. buffer->time[2] = bin2bcd(tm.tm_sec);
  613. buffer->time[3] = 0;
  614. buffer->time[4] = bin2bcd(tm.tm_mon + 1);
  615. buffer->time[5] = bin2bcd(tm.tm_mday);
  616. buffer->time[6] = bin2bcd(year / 100);
  617. buffer->time[7] = bin2bcd(year % 100);
  618. buffer->dont_write_tag[0] = 'D';
  619. buffer->dont_write_tag[1] = 'W';
  620. buffer->end_tag[0] = 'Z';
  621. buffer->end_tag[1] = 'Z';
  622. rc = pqi_write_host_wellness(ctrl_info, buffer, buffer_length);
  623. kfree(buffer);
  624. return rc;
  625. }
  626. #define PQI_UPDATE_TIME_WORK_INTERVAL (24UL * 60 * 60 * HZ)
  627. static void pqi_update_time_worker(struct work_struct *work)
  628. {
  629. int rc;
  630. struct pqi_ctrl_info *ctrl_info;
  631. ctrl_info = container_of(to_delayed_work(work), struct pqi_ctrl_info,
  632. update_time_work);
  633. if (pqi_ctrl_offline(ctrl_info))
  634. return;
  635. rc = pqi_write_current_time_to_host_wellness(ctrl_info);
  636. if (rc)
  637. dev_warn(&ctrl_info->pci_dev->dev,
  638. "error updating time on controller\n");
  639. schedule_delayed_work(&ctrl_info->update_time_work,
  640. PQI_UPDATE_TIME_WORK_INTERVAL);
  641. }
  642. static inline void pqi_schedule_update_time_worker(
  643. struct pqi_ctrl_info *ctrl_info)
  644. {
  645. schedule_delayed_work(&ctrl_info->update_time_work, 0);
  646. }
  647. static inline void pqi_cancel_update_time_worker(
  648. struct pqi_ctrl_info *ctrl_info)
  649. {
  650. cancel_delayed_work_sync(&ctrl_info->update_time_work);
  651. }
  652. static int pqi_report_luns(struct pqi_ctrl_info *ctrl_info, u8 cmd,
  653. void *buffer, size_t buffer_length)
  654. {
  655. int rc;
  656. int pci_direction;
  657. struct pqi_raid_path_request request;
  658. rc = pqi_build_raid_path_request(ctrl_info, &request,
  659. cmd, RAID_CTLR_LUNID, buffer, buffer_length, 0, &pci_direction);
  660. if (rc)
  661. return rc;
  662. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0,
  663. NULL, NO_TIMEOUT);
  664. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  665. pci_direction);
  666. return rc;
  667. }
  668. static int pqi_report_phys_logical_luns(struct pqi_ctrl_info *ctrl_info, u8 cmd,
  669. void **buffer)
  670. {
  671. int rc;
  672. size_t lun_list_length;
  673. size_t lun_data_length;
  674. size_t new_lun_list_length;
  675. void *lun_data = NULL;
  676. struct report_lun_header *report_lun_header;
  677. report_lun_header = kmalloc(sizeof(*report_lun_header), GFP_KERNEL);
  678. if (!report_lun_header) {
  679. rc = -ENOMEM;
  680. goto out;
  681. }
  682. rc = pqi_report_luns(ctrl_info, cmd, report_lun_header,
  683. sizeof(*report_lun_header));
  684. if (rc)
  685. goto out;
  686. lun_list_length = get_unaligned_be32(&report_lun_header->list_length);
  687. again:
  688. lun_data_length = sizeof(struct report_lun_header) + lun_list_length;
  689. lun_data = kmalloc(lun_data_length, GFP_KERNEL);
  690. if (!lun_data) {
  691. rc = -ENOMEM;
  692. goto out;
  693. }
  694. if (lun_list_length == 0) {
  695. memcpy(lun_data, report_lun_header, sizeof(*report_lun_header));
  696. goto out;
  697. }
  698. rc = pqi_report_luns(ctrl_info, cmd, lun_data, lun_data_length);
  699. if (rc)
  700. goto out;
  701. new_lun_list_length = get_unaligned_be32(
  702. &((struct report_lun_header *)lun_data)->list_length);
  703. if (new_lun_list_length > lun_list_length) {
  704. lun_list_length = new_lun_list_length;
  705. kfree(lun_data);
  706. goto again;
  707. }
  708. out:
  709. kfree(report_lun_header);
  710. if (rc) {
  711. kfree(lun_data);
  712. lun_data = NULL;
  713. }
  714. *buffer = lun_data;
  715. return rc;
  716. }
  717. static inline int pqi_report_phys_luns(struct pqi_ctrl_info *ctrl_info,
  718. void **buffer)
  719. {
  720. return pqi_report_phys_logical_luns(ctrl_info, CISS_REPORT_PHYS,
  721. buffer);
  722. }
  723. static inline int pqi_report_logical_luns(struct pqi_ctrl_info *ctrl_info,
  724. void **buffer)
  725. {
  726. return pqi_report_phys_logical_luns(ctrl_info, CISS_REPORT_LOG, buffer);
  727. }
  728. static int pqi_get_device_lists(struct pqi_ctrl_info *ctrl_info,
  729. struct report_phys_lun_extended **physdev_list,
  730. struct report_log_lun_extended **logdev_list)
  731. {
  732. int rc;
  733. size_t logdev_list_length;
  734. size_t logdev_data_length;
  735. struct report_log_lun_extended *internal_logdev_list;
  736. struct report_log_lun_extended *logdev_data;
  737. struct report_lun_header report_lun_header;
  738. rc = pqi_report_phys_luns(ctrl_info, (void **)physdev_list);
  739. if (rc)
  740. dev_err(&ctrl_info->pci_dev->dev,
  741. "report physical LUNs failed\n");
  742. rc = pqi_report_logical_luns(ctrl_info, (void **)logdev_list);
  743. if (rc)
  744. dev_err(&ctrl_info->pci_dev->dev,
  745. "report logical LUNs failed\n");
  746. /*
  747. * Tack the controller itself onto the end of the logical device list.
  748. */
  749. logdev_data = *logdev_list;
  750. if (logdev_data) {
  751. logdev_list_length =
  752. get_unaligned_be32(&logdev_data->header.list_length);
  753. } else {
  754. memset(&report_lun_header, 0, sizeof(report_lun_header));
  755. logdev_data =
  756. (struct report_log_lun_extended *)&report_lun_header;
  757. logdev_list_length = 0;
  758. }
  759. logdev_data_length = sizeof(struct report_lun_header) +
  760. logdev_list_length;
  761. internal_logdev_list = kmalloc(logdev_data_length +
  762. sizeof(struct report_log_lun_extended), GFP_KERNEL);
  763. if (!internal_logdev_list) {
  764. kfree(*logdev_list);
  765. *logdev_list = NULL;
  766. return -ENOMEM;
  767. }
  768. memcpy(internal_logdev_list, logdev_data, logdev_data_length);
  769. memset((u8 *)internal_logdev_list + logdev_data_length, 0,
  770. sizeof(struct report_log_lun_extended_entry));
  771. put_unaligned_be32(logdev_list_length +
  772. sizeof(struct report_log_lun_extended_entry),
  773. &internal_logdev_list->header.list_length);
  774. kfree(*logdev_list);
  775. *logdev_list = internal_logdev_list;
  776. return 0;
  777. }
  778. static inline void pqi_set_bus_target_lun(struct pqi_scsi_dev *device,
  779. int bus, int target, int lun)
  780. {
  781. device->bus = bus;
  782. device->target = target;
  783. device->lun = lun;
  784. }
  785. static void pqi_assign_bus_target_lun(struct pqi_scsi_dev *device)
  786. {
  787. u8 *scsi3addr;
  788. u32 lunid;
  789. int bus;
  790. int target;
  791. int lun;
  792. scsi3addr = device->scsi3addr;
  793. lunid = get_unaligned_le32(scsi3addr);
  794. if (pqi_is_hba_lunid(scsi3addr)) {
  795. /* The specified device is the controller. */
  796. pqi_set_bus_target_lun(device, PQI_HBA_BUS, 0, lunid & 0x3fff);
  797. device->target_lun_valid = true;
  798. return;
  799. }
  800. if (pqi_is_logical_device(device)) {
  801. if (device->is_external_raid_device) {
  802. bus = PQI_EXTERNAL_RAID_VOLUME_BUS;
  803. target = (lunid >> 16) & 0x3fff;
  804. lun = lunid & 0xff;
  805. } else {
  806. bus = PQI_RAID_VOLUME_BUS;
  807. target = 0;
  808. lun = lunid & 0x3fff;
  809. }
  810. pqi_set_bus_target_lun(device, bus, target, lun);
  811. device->target_lun_valid = true;
  812. return;
  813. }
  814. /*
  815. * Defer target and LUN assignment for non-controller physical devices
  816. * because the SAS transport layer will make these assignments later.
  817. */
  818. pqi_set_bus_target_lun(device, PQI_PHYSICAL_DEVICE_BUS, 0, 0);
  819. }
  820. static void pqi_get_raid_level(struct pqi_ctrl_info *ctrl_info,
  821. struct pqi_scsi_dev *device)
  822. {
  823. int rc;
  824. u8 raid_level;
  825. u8 *buffer;
  826. raid_level = SA_RAID_UNKNOWN;
  827. buffer = kmalloc(64, GFP_KERNEL);
  828. if (buffer) {
  829. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr,
  830. VPD_PAGE | CISS_VPD_LV_DEVICE_GEOMETRY, buffer, 64);
  831. if (rc == 0) {
  832. raid_level = buffer[8];
  833. if (raid_level > SA_RAID_MAX)
  834. raid_level = SA_RAID_UNKNOWN;
  835. }
  836. kfree(buffer);
  837. }
  838. device->raid_level = raid_level;
  839. }
  840. static int pqi_validate_raid_map(struct pqi_ctrl_info *ctrl_info,
  841. struct pqi_scsi_dev *device, struct raid_map *raid_map)
  842. {
  843. char *err_msg;
  844. u32 raid_map_size;
  845. u32 r5or6_blocks_per_row;
  846. unsigned int num_phys_disks;
  847. unsigned int num_raid_map_entries;
  848. raid_map_size = get_unaligned_le32(&raid_map->structure_size);
  849. if (raid_map_size < offsetof(struct raid_map, disk_data)) {
  850. err_msg = "RAID map too small";
  851. goto bad_raid_map;
  852. }
  853. if (raid_map_size > sizeof(*raid_map)) {
  854. err_msg = "RAID map too large";
  855. goto bad_raid_map;
  856. }
  857. num_phys_disks = get_unaligned_le16(&raid_map->layout_map_count) *
  858. (get_unaligned_le16(&raid_map->data_disks_per_row) +
  859. get_unaligned_le16(&raid_map->metadata_disks_per_row));
  860. num_raid_map_entries = num_phys_disks *
  861. get_unaligned_le16(&raid_map->row_cnt);
  862. if (num_raid_map_entries > RAID_MAP_MAX_ENTRIES) {
  863. err_msg = "invalid number of map entries in RAID map";
  864. goto bad_raid_map;
  865. }
  866. if (device->raid_level == SA_RAID_1) {
  867. if (get_unaligned_le16(&raid_map->layout_map_count) != 2) {
  868. err_msg = "invalid RAID-1 map";
  869. goto bad_raid_map;
  870. }
  871. } else if (device->raid_level == SA_RAID_ADM) {
  872. if (get_unaligned_le16(&raid_map->layout_map_count) != 3) {
  873. err_msg = "invalid RAID-1(ADM) map";
  874. goto bad_raid_map;
  875. }
  876. } else if ((device->raid_level == SA_RAID_5 ||
  877. device->raid_level == SA_RAID_6) &&
  878. get_unaligned_le16(&raid_map->layout_map_count) > 1) {
  879. /* RAID 50/60 */
  880. r5or6_blocks_per_row =
  881. get_unaligned_le16(&raid_map->strip_size) *
  882. get_unaligned_le16(&raid_map->data_disks_per_row);
  883. if (r5or6_blocks_per_row == 0) {
  884. err_msg = "invalid RAID-5 or RAID-6 map";
  885. goto bad_raid_map;
  886. }
  887. }
  888. return 0;
  889. bad_raid_map:
  890. dev_warn(&ctrl_info->pci_dev->dev,
  891. "logical device %08x%08x %s\n",
  892. *((u32 *)&device->scsi3addr),
  893. *((u32 *)&device->scsi3addr[4]), err_msg);
  894. return -EINVAL;
  895. }
  896. static int pqi_get_raid_map(struct pqi_ctrl_info *ctrl_info,
  897. struct pqi_scsi_dev *device)
  898. {
  899. int rc;
  900. int pci_direction;
  901. struct pqi_raid_path_request request;
  902. struct raid_map *raid_map;
  903. raid_map = kmalloc(sizeof(*raid_map), GFP_KERNEL);
  904. if (!raid_map)
  905. return -ENOMEM;
  906. rc = pqi_build_raid_path_request(ctrl_info, &request,
  907. CISS_GET_RAID_MAP, device->scsi3addr, raid_map,
  908. sizeof(*raid_map), 0, &pci_direction);
  909. if (rc)
  910. goto error;
  911. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0,
  912. NULL, NO_TIMEOUT);
  913. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  914. pci_direction);
  915. if (rc)
  916. goto error;
  917. rc = pqi_validate_raid_map(ctrl_info, device, raid_map);
  918. if (rc)
  919. goto error;
  920. device->raid_map = raid_map;
  921. return 0;
  922. error:
  923. kfree(raid_map);
  924. return rc;
  925. }
  926. static void pqi_get_raid_bypass_status(struct pqi_ctrl_info *ctrl_info,
  927. struct pqi_scsi_dev *device)
  928. {
  929. int rc;
  930. u8 *buffer;
  931. u8 bypass_status;
  932. buffer = kmalloc(64, GFP_KERNEL);
  933. if (!buffer)
  934. return;
  935. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr,
  936. VPD_PAGE | CISS_VPD_LV_BYPASS_STATUS, buffer, 64);
  937. if (rc)
  938. goto out;
  939. #define RAID_BYPASS_STATUS 4
  940. #define RAID_BYPASS_CONFIGURED 0x1
  941. #define RAID_BYPASS_ENABLED 0x2
  942. bypass_status = buffer[RAID_BYPASS_STATUS];
  943. device->raid_bypass_configured =
  944. (bypass_status & RAID_BYPASS_CONFIGURED) != 0;
  945. if (device->raid_bypass_configured &&
  946. (bypass_status & RAID_BYPASS_ENABLED) &&
  947. pqi_get_raid_map(ctrl_info, device) == 0)
  948. device->raid_bypass_enabled = true;
  949. out:
  950. kfree(buffer);
  951. }
  952. /*
  953. * Use vendor-specific VPD to determine online/offline status of a volume.
  954. */
  955. static void pqi_get_volume_status(struct pqi_ctrl_info *ctrl_info,
  956. struct pqi_scsi_dev *device)
  957. {
  958. int rc;
  959. size_t page_length;
  960. u8 volume_status = CISS_LV_STATUS_UNAVAILABLE;
  961. bool volume_offline = true;
  962. u32 volume_flags;
  963. struct ciss_vpd_logical_volume_status *vpd;
  964. vpd = kmalloc(sizeof(*vpd), GFP_KERNEL);
  965. if (!vpd)
  966. goto no_buffer;
  967. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr,
  968. VPD_PAGE | CISS_VPD_LV_STATUS, vpd, sizeof(*vpd));
  969. if (rc)
  970. goto out;
  971. if (vpd->page_code != CISS_VPD_LV_STATUS)
  972. goto out;
  973. page_length = offsetof(struct ciss_vpd_logical_volume_status,
  974. volume_status) + vpd->page_length;
  975. if (page_length < sizeof(*vpd))
  976. goto out;
  977. volume_status = vpd->volume_status;
  978. volume_flags = get_unaligned_be32(&vpd->flags);
  979. volume_offline = (volume_flags & CISS_LV_FLAGS_NO_HOST_IO) != 0;
  980. out:
  981. kfree(vpd);
  982. no_buffer:
  983. device->volume_status = volume_status;
  984. device->volume_offline = volume_offline;
  985. }
  986. #define PQI_INQUIRY_PAGE0_RETRIES 3
  987. static int pqi_get_device_info(struct pqi_ctrl_info *ctrl_info,
  988. struct pqi_scsi_dev *device)
  989. {
  990. int rc;
  991. u8 *buffer;
  992. unsigned int retries;
  993. buffer = kmalloc(64, GFP_KERNEL);
  994. if (!buffer)
  995. return -ENOMEM;
  996. /* Send an inquiry to the device to see what it is. */
  997. for (retries = 0;;) {
  998. rc = pqi_scsi_inquiry(ctrl_info, device->scsi3addr, 0,
  999. buffer, 64);
  1000. if (rc == 0)
  1001. break;
  1002. if (pqi_is_logical_device(device) ||
  1003. rc != PQI_CMD_STATUS_ABORTED ||
  1004. ++retries > PQI_INQUIRY_PAGE0_RETRIES)
  1005. goto out;
  1006. }
  1007. scsi_sanitize_inquiry_string(&buffer[8], 8);
  1008. scsi_sanitize_inquiry_string(&buffer[16], 16);
  1009. device->devtype = buffer[0] & 0x1f;
  1010. memcpy(device->vendor, &buffer[8], sizeof(device->vendor));
  1011. memcpy(device->model, &buffer[16], sizeof(device->model));
  1012. if (pqi_is_logical_device(device) && device->devtype == TYPE_DISK) {
  1013. if (device->is_external_raid_device) {
  1014. device->raid_level = SA_RAID_UNKNOWN;
  1015. device->volume_status = CISS_LV_OK;
  1016. device->volume_offline = false;
  1017. } else {
  1018. pqi_get_raid_level(ctrl_info, device);
  1019. pqi_get_raid_bypass_status(ctrl_info, device);
  1020. pqi_get_volume_status(ctrl_info, device);
  1021. }
  1022. }
  1023. out:
  1024. kfree(buffer);
  1025. return rc;
  1026. }
  1027. static void pqi_get_physical_disk_info(struct pqi_ctrl_info *ctrl_info,
  1028. struct pqi_scsi_dev *device,
  1029. struct bmic_identify_physical_device *id_phys)
  1030. {
  1031. int rc;
  1032. memset(id_phys, 0, sizeof(*id_phys));
  1033. rc = pqi_identify_physical_device(ctrl_info, device,
  1034. id_phys, sizeof(*id_phys));
  1035. if (rc) {
  1036. device->queue_depth = PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH;
  1037. return;
  1038. }
  1039. device->queue_depth =
  1040. get_unaligned_le16(&id_phys->current_queue_depth_limit);
  1041. device->device_type = id_phys->device_type;
  1042. device->active_path_index = id_phys->active_path_number;
  1043. device->path_map = id_phys->redundant_path_present_map;
  1044. memcpy(&device->box,
  1045. &id_phys->alternate_paths_phys_box_on_port,
  1046. sizeof(device->box));
  1047. memcpy(&device->phys_connector,
  1048. &id_phys->alternate_paths_phys_connector,
  1049. sizeof(device->phys_connector));
  1050. device->bay = id_phys->phys_bay_in_box;
  1051. }
  1052. static void pqi_show_volume_status(struct pqi_ctrl_info *ctrl_info,
  1053. struct pqi_scsi_dev *device)
  1054. {
  1055. char *status;
  1056. static const char unknown_state_str[] =
  1057. "Volume is in an unknown state (%u)";
  1058. char unknown_state_buffer[sizeof(unknown_state_str) + 10];
  1059. switch (device->volume_status) {
  1060. case CISS_LV_OK:
  1061. status = "Volume online";
  1062. break;
  1063. case CISS_LV_FAILED:
  1064. status = "Volume failed";
  1065. break;
  1066. case CISS_LV_NOT_CONFIGURED:
  1067. status = "Volume not configured";
  1068. break;
  1069. case CISS_LV_DEGRADED:
  1070. status = "Volume degraded";
  1071. break;
  1072. case CISS_LV_READY_FOR_RECOVERY:
  1073. status = "Volume ready for recovery operation";
  1074. break;
  1075. case CISS_LV_UNDERGOING_RECOVERY:
  1076. status = "Volume undergoing recovery";
  1077. break;
  1078. case CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED:
  1079. status = "Wrong physical drive was replaced";
  1080. break;
  1081. case CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM:
  1082. status = "A physical drive not properly connected";
  1083. break;
  1084. case CISS_LV_HARDWARE_OVERHEATING:
  1085. status = "Hardware is overheating";
  1086. break;
  1087. case CISS_LV_HARDWARE_HAS_OVERHEATED:
  1088. status = "Hardware has overheated";
  1089. break;
  1090. case CISS_LV_UNDERGOING_EXPANSION:
  1091. status = "Volume undergoing expansion";
  1092. break;
  1093. case CISS_LV_NOT_AVAILABLE:
  1094. status = "Volume waiting for transforming volume";
  1095. break;
  1096. case CISS_LV_QUEUED_FOR_EXPANSION:
  1097. status = "Volume queued for expansion";
  1098. break;
  1099. case CISS_LV_DISABLED_SCSI_ID_CONFLICT:
  1100. status = "Volume disabled due to SCSI ID conflict";
  1101. break;
  1102. case CISS_LV_EJECTED:
  1103. status = "Volume has been ejected";
  1104. break;
  1105. case CISS_LV_UNDERGOING_ERASE:
  1106. status = "Volume undergoing background erase";
  1107. break;
  1108. case CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD:
  1109. status = "Volume ready for predictive spare rebuild";
  1110. break;
  1111. case CISS_LV_UNDERGOING_RPI:
  1112. status = "Volume undergoing rapid parity initialization";
  1113. break;
  1114. case CISS_LV_PENDING_RPI:
  1115. status = "Volume queued for rapid parity initialization";
  1116. break;
  1117. case CISS_LV_ENCRYPTED_NO_KEY:
  1118. status = "Encrypted volume inaccessible - key not present";
  1119. break;
  1120. case CISS_LV_UNDERGOING_ENCRYPTION:
  1121. status = "Volume undergoing encryption process";
  1122. break;
  1123. case CISS_LV_UNDERGOING_ENCRYPTION_REKEYING:
  1124. status = "Volume undergoing encryption re-keying process";
  1125. break;
  1126. case CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  1127. status = "Volume encrypted but encryption is disabled";
  1128. break;
  1129. case CISS_LV_PENDING_ENCRYPTION:
  1130. status = "Volume pending migration to encrypted state";
  1131. break;
  1132. case CISS_LV_PENDING_ENCRYPTION_REKEYING:
  1133. status = "Volume pending encryption rekeying";
  1134. break;
  1135. case CISS_LV_NOT_SUPPORTED:
  1136. status = "Volume not supported on this controller";
  1137. break;
  1138. case CISS_LV_STATUS_UNAVAILABLE:
  1139. status = "Volume status not available";
  1140. break;
  1141. default:
  1142. snprintf(unknown_state_buffer, sizeof(unknown_state_buffer),
  1143. unknown_state_str, device->volume_status);
  1144. status = unknown_state_buffer;
  1145. break;
  1146. }
  1147. dev_info(&ctrl_info->pci_dev->dev,
  1148. "scsi %d:%d:%d:%d %s\n",
  1149. ctrl_info->scsi_host->host_no,
  1150. device->bus, device->target, device->lun, status);
  1151. }
  1152. static void pqi_rescan_worker(struct work_struct *work)
  1153. {
  1154. struct pqi_ctrl_info *ctrl_info;
  1155. ctrl_info = container_of(to_delayed_work(work), struct pqi_ctrl_info,
  1156. rescan_work);
  1157. pqi_scan_scsi_devices(ctrl_info);
  1158. }
  1159. static int pqi_add_device(struct pqi_ctrl_info *ctrl_info,
  1160. struct pqi_scsi_dev *device)
  1161. {
  1162. int rc;
  1163. if (pqi_is_logical_device(device))
  1164. rc = scsi_add_device(ctrl_info->scsi_host, device->bus,
  1165. device->target, device->lun);
  1166. else
  1167. rc = pqi_add_sas_device(ctrl_info->sas_host, device);
  1168. return rc;
  1169. }
  1170. static inline void pqi_remove_device(struct pqi_ctrl_info *ctrl_info,
  1171. struct pqi_scsi_dev *device)
  1172. {
  1173. if (pqi_is_logical_device(device))
  1174. scsi_remove_device(device->sdev);
  1175. else
  1176. pqi_remove_sas_device(device);
  1177. }
  1178. /* Assumes the SCSI device list lock is held. */
  1179. static struct pqi_scsi_dev *pqi_find_scsi_dev(struct pqi_ctrl_info *ctrl_info,
  1180. int bus, int target, int lun)
  1181. {
  1182. struct pqi_scsi_dev *device;
  1183. list_for_each_entry(device, &ctrl_info->scsi_device_list,
  1184. scsi_device_list_entry)
  1185. if (device->bus == bus && device->target == target &&
  1186. device->lun == lun)
  1187. return device;
  1188. return NULL;
  1189. }
  1190. static inline bool pqi_device_equal(struct pqi_scsi_dev *dev1,
  1191. struct pqi_scsi_dev *dev2)
  1192. {
  1193. if (dev1->is_physical_device != dev2->is_physical_device)
  1194. return false;
  1195. if (dev1->is_physical_device)
  1196. return dev1->wwid == dev2->wwid;
  1197. return memcmp(dev1->volume_id, dev2->volume_id,
  1198. sizeof(dev1->volume_id)) == 0;
  1199. }
  1200. enum pqi_find_result {
  1201. DEVICE_NOT_FOUND,
  1202. DEVICE_CHANGED,
  1203. DEVICE_SAME,
  1204. };
  1205. static enum pqi_find_result pqi_scsi_find_entry(struct pqi_ctrl_info *ctrl_info,
  1206. struct pqi_scsi_dev *device_to_find,
  1207. struct pqi_scsi_dev **matching_device)
  1208. {
  1209. struct pqi_scsi_dev *device;
  1210. list_for_each_entry(device, &ctrl_info->scsi_device_list,
  1211. scsi_device_list_entry) {
  1212. if (pqi_scsi3addr_equal(device_to_find->scsi3addr,
  1213. device->scsi3addr)) {
  1214. *matching_device = device;
  1215. if (pqi_device_equal(device_to_find, device)) {
  1216. if (device_to_find->volume_offline)
  1217. return DEVICE_CHANGED;
  1218. return DEVICE_SAME;
  1219. }
  1220. return DEVICE_CHANGED;
  1221. }
  1222. }
  1223. return DEVICE_NOT_FOUND;
  1224. }
  1225. #define PQI_DEV_INFO_BUFFER_LENGTH 128
  1226. static void pqi_dev_info(struct pqi_ctrl_info *ctrl_info,
  1227. char *action, struct pqi_scsi_dev *device)
  1228. {
  1229. ssize_t count;
  1230. char buffer[PQI_DEV_INFO_BUFFER_LENGTH];
  1231. count = snprintf(buffer, PQI_DEV_INFO_BUFFER_LENGTH,
  1232. "%d:%d:", ctrl_info->scsi_host->host_no, device->bus);
  1233. if (device->target_lun_valid)
  1234. count += snprintf(buffer + count,
  1235. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1236. "%d:%d",
  1237. device->target,
  1238. device->lun);
  1239. else
  1240. count += snprintf(buffer + count,
  1241. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1242. "-:-");
  1243. if (pqi_is_logical_device(device))
  1244. count += snprintf(buffer + count,
  1245. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1246. " %08x%08x",
  1247. *((u32 *)&device->scsi3addr),
  1248. *((u32 *)&device->scsi3addr[4]));
  1249. else
  1250. count += snprintf(buffer + count,
  1251. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1252. " %016llx", device->sas_address);
  1253. count += snprintf(buffer + count, PQI_DEV_INFO_BUFFER_LENGTH - count,
  1254. " %s %.8s %.16s ",
  1255. scsi_device_type(device->devtype),
  1256. device->vendor,
  1257. device->model);
  1258. if (pqi_is_logical_device(device)) {
  1259. if (device->devtype == TYPE_DISK)
  1260. count += snprintf(buffer + count,
  1261. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1262. "SSDSmartPathCap%c En%c %-12s",
  1263. device->raid_bypass_configured ? '+' : '-',
  1264. device->raid_bypass_enabled ? '+' : '-',
  1265. pqi_raid_level_to_string(device->raid_level));
  1266. } else {
  1267. count += snprintf(buffer + count,
  1268. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1269. "AIO%c", device->aio_enabled ? '+' : '-');
  1270. if (device->devtype == TYPE_DISK ||
  1271. device->devtype == TYPE_ZBC)
  1272. count += snprintf(buffer + count,
  1273. PQI_DEV_INFO_BUFFER_LENGTH - count,
  1274. " qd=%-6d", device->queue_depth);
  1275. }
  1276. dev_info(&ctrl_info->pci_dev->dev, "%s %s\n", action, buffer);
  1277. }
  1278. /* Assumes the SCSI device list lock is held. */
  1279. static void pqi_scsi_update_device(struct pqi_scsi_dev *existing_device,
  1280. struct pqi_scsi_dev *new_device)
  1281. {
  1282. existing_device->devtype = new_device->devtype;
  1283. existing_device->device_type = new_device->device_type;
  1284. existing_device->bus = new_device->bus;
  1285. if (new_device->target_lun_valid) {
  1286. existing_device->target = new_device->target;
  1287. existing_device->lun = new_device->lun;
  1288. existing_device->target_lun_valid = true;
  1289. }
  1290. /* By definition, the scsi3addr and wwid fields are already the same. */
  1291. existing_device->is_physical_device = new_device->is_physical_device;
  1292. existing_device->is_external_raid_device =
  1293. new_device->is_external_raid_device;
  1294. existing_device->aio_enabled = new_device->aio_enabled;
  1295. memcpy(existing_device->vendor, new_device->vendor,
  1296. sizeof(existing_device->vendor));
  1297. memcpy(existing_device->model, new_device->model,
  1298. sizeof(existing_device->model));
  1299. existing_device->sas_address = new_device->sas_address;
  1300. existing_device->raid_level = new_device->raid_level;
  1301. existing_device->queue_depth = new_device->queue_depth;
  1302. existing_device->aio_handle = new_device->aio_handle;
  1303. existing_device->volume_status = new_device->volume_status;
  1304. existing_device->active_path_index = new_device->active_path_index;
  1305. existing_device->path_map = new_device->path_map;
  1306. existing_device->bay = new_device->bay;
  1307. memcpy(existing_device->box, new_device->box,
  1308. sizeof(existing_device->box));
  1309. memcpy(existing_device->phys_connector, new_device->phys_connector,
  1310. sizeof(existing_device->phys_connector));
  1311. existing_device->offload_to_mirror = 0;
  1312. kfree(existing_device->raid_map);
  1313. existing_device->raid_map = new_device->raid_map;
  1314. existing_device->raid_bypass_configured =
  1315. new_device->raid_bypass_configured;
  1316. existing_device->raid_bypass_enabled =
  1317. new_device->raid_bypass_enabled;
  1318. /* To prevent this from being freed later. */
  1319. new_device->raid_map = NULL;
  1320. }
  1321. static inline void pqi_free_device(struct pqi_scsi_dev *device)
  1322. {
  1323. if (device) {
  1324. kfree(device->raid_map);
  1325. kfree(device);
  1326. }
  1327. }
  1328. /*
  1329. * Called when exposing a new device to the OS fails in order to re-adjust
  1330. * our internal SCSI device list to match the SCSI ML's view.
  1331. */
  1332. static inline void pqi_fixup_botched_add(struct pqi_ctrl_info *ctrl_info,
  1333. struct pqi_scsi_dev *device)
  1334. {
  1335. unsigned long flags;
  1336. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  1337. list_del(&device->scsi_device_list_entry);
  1338. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  1339. /* Allow the device structure to be freed later. */
  1340. device->keep_device = false;
  1341. }
  1342. static void pqi_update_device_list(struct pqi_ctrl_info *ctrl_info,
  1343. struct pqi_scsi_dev *new_device_list[], unsigned int num_new_devices)
  1344. {
  1345. int rc;
  1346. unsigned int i;
  1347. unsigned long flags;
  1348. enum pqi_find_result find_result;
  1349. struct pqi_scsi_dev *device;
  1350. struct pqi_scsi_dev *next;
  1351. struct pqi_scsi_dev *matching_device;
  1352. LIST_HEAD(add_list);
  1353. LIST_HEAD(delete_list);
  1354. /*
  1355. * The idea here is to do as little work as possible while holding the
  1356. * spinlock. That's why we go to great pains to defer anything other
  1357. * than updating the internal device list until after we release the
  1358. * spinlock.
  1359. */
  1360. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  1361. /* Assume that all devices in the existing list have gone away. */
  1362. list_for_each_entry(device, &ctrl_info->scsi_device_list,
  1363. scsi_device_list_entry)
  1364. device->device_gone = true;
  1365. for (i = 0; i < num_new_devices; i++) {
  1366. device = new_device_list[i];
  1367. find_result = pqi_scsi_find_entry(ctrl_info, device,
  1368. &matching_device);
  1369. switch (find_result) {
  1370. case DEVICE_SAME:
  1371. /*
  1372. * The newly found device is already in the existing
  1373. * device list.
  1374. */
  1375. device->new_device = false;
  1376. matching_device->device_gone = false;
  1377. pqi_scsi_update_device(matching_device, device);
  1378. break;
  1379. case DEVICE_NOT_FOUND:
  1380. /*
  1381. * The newly found device is NOT in the existing device
  1382. * list.
  1383. */
  1384. device->new_device = true;
  1385. break;
  1386. case DEVICE_CHANGED:
  1387. /*
  1388. * The original device has gone away and we need to add
  1389. * the new device.
  1390. */
  1391. device->new_device = true;
  1392. break;
  1393. }
  1394. }
  1395. /* Process all devices that have gone away. */
  1396. list_for_each_entry_safe(device, next, &ctrl_info->scsi_device_list,
  1397. scsi_device_list_entry) {
  1398. if (device->device_gone) {
  1399. list_del(&device->scsi_device_list_entry);
  1400. list_add_tail(&device->delete_list_entry, &delete_list);
  1401. }
  1402. }
  1403. /* Process all new devices. */
  1404. for (i = 0; i < num_new_devices; i++) {
  1405. device = new_device_list[i];
  1406. if (!device->new_device)
  1407. continue;
  1408. if (device->volume_offline)
  1409. continue;
  1410. list_add_tail(&device->scsi_device_list_entry,
  1411. &ctrl_info->scsi_device_list);
  1412. list_add_tail(&device->add_list_entry, &add_list);
  1413. /* To prevent this device structure from being freed later. */
  1414. device->keep_device = true;
  1415. }
  1416. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  1417. /* Remove all devices that have gone away. */
  1418. list_for_each_entry_safe(device, next, &delete_list,
  1419. delete_list_entry) {
  1420. if (device->volume_offline) {
  1421. pqi_dev_info(ctrl_info, "offline", device);
  1422. pqi_show_volume_status(ctrl_info, device);
  1423. } else {
  1424. pqi_dev_info(ctrl_info, "removed", device);
  1425. }
  1426. if (device->sdev)
  1427. pqi_remove_device(ctrl_info, device);
  1428. list_del(&device->delete_list_entry);
  1429. pqi_free_device(device);
  1430. }
  1431. /*
  1432. * Notify the SCSI ML if the queue depth of any existing device has
  1433. * changed.
  1434. */
  1435. list_for_each_entry(device, &ctrl_info->scsi_device_list,
  1436. scsi_device_list_entry) {
  1437. if (device->sdev && device->queue_depth !=
  1438. device->advertised_queue_depth) {
  1439. device->advertised_queue_depth = device->queue_depth;
  1440. scsi_change_queue_depth(device->sdev,
  1441. device->advertised_queue_depth);
  1442. }
  1443. }
  1444. /* Expose any new devices. */
  1445. list_for_each_entry_safe(device, next, &add_list, add_list_entry) {
  1446. if (!device->sdev) {
  1447. pqi_dev_info(ctrl_info, "added", device);
  1448. rc = pqi_add_device(ctrl_info, device);
  1449. if (rc) {
  1450. dev_warn(&ctrl_info->pci_dev->dev,
  1451. "scsi %d:%d:%d:%d addition failed, device not added\n",
  1452. ctrl_info->scsi_host->host_no,
  1453. device->bus, device->target,
  1454. device->lun);
  1455. pqi_fixup_botched_add(ctrl_info, device);
  1456. }
  1457. }
  1458. }
  1459. }
  1460. static bool pqi_is_supported_device(struct pqi_scsi_dev *device)
  1461. {
  1462. bool is_supported = false;
  1463. switch (device->devtype) {
  1464. case TYPE_DISK:
  1465. case TYPE_ZBC:
  1466. case TYPE_TAPE:
  1467. case TYPE_MEDIUM_CHANGER:
  1468. case TYPE_ENCLOSURE:
  1469. is_supported = true;
  1470. break;
  1471. case TYPE_RAID:
  1472. /*
  1473. * Only support the HBA controller itself as a RAID
  1474. * controller. If it's a RAID controller other than
  1475. * the HBA itself (an external RAID controller, for
  1476. * example), we don't support it.
  1477. */
  1478. if (pqi_is_hba_lunid(device->scsi3addr))
  1479. is_supported = true;
  1480. break;
  1481. }
  1482. return is_supported;
  1483. }
  1484. static inline bool pqi_skip_device(u8 *scsi3addr)
  1485. {
  1486. /* Ignore all masked devices. */
  1487. if (MASKED_DEVICE(scsi3addr))
  1488. return true;
  1489. return false;
  1490. }
  1491. static int pqi_update_scsi_devices(struct pqi_ctrl_info *ctrl_info)
  1492. {
  1493. int i;
  1494. int rc;
  1495. LIST_HEAD(new_device_list_head);
  1496. struct report_phys_lun_extended *physdev_list = NULL;
  1497. struct report_log_lun_extended *logdev_list = NULL;
  1498. struct report_phys_lun_extended_entry *phys_lun_ext_entry;
  1499. struct report_log_lun_extended_entry *log_lun_ext_entry;
  1500. struct bmic_identify_physical_device *id_phys = NULL;
  1501. u32 num_physicals;
  1502. u32 num_logicals;
  1503. struct pqi_scsi_dev **new_device_list = NULL;
  1504. struct pqi_scsi_dev *device;
  1505. struct pqi_scsi_dev *next;
  1506. unsigned int num_new_devices;
  1507. unsigned int num_valid_devices;
  1508. bool is_physical_device;
  1509. u8 *scsi3addr;
  1510. static char *out_of_memory_msg =
  1511. "failed to allocate memory, device discovery stopped";
  1512. rc = pqi_get_device_lists(ctrl_info, &physdev_list, &logdev_list);
  1513. if (rc)
  1514. goto out;
  1515. if (physdev_list)
  1516. num_physicals =
  1517. get_unaligned_be32(&physdev_list->header.list_length)
  1518. / sizeof(physdev_list->lun_entries[0]);
  1519. else
  1520. num_physicals = 0;
  1521. if (logdev_list)
  1522. num_logicals =
  1523. get_unaligned_be32(&logdev_list->header.list_length)
  1524. / sizeof(logdev_list->lun_entries[0]);
  1525. else
  1526. num_logicals = 0;
  1527. if (num_physicals) {
  1528. /*
  1529. * We need this buffer for calls to pqi_get_physical_disk_info()
  1530. * below. We allocate it here instead of inside
  1531. * pqi_get_physical_disk_info() because it's a fairly large
  1532. * buffer.
  1533. */
  1534. id_phys = kmalloc(sizeof(*id_phys), GFP_KERNEL);
  1535. if (!id_phys) {
  1536. dev_warn(&ctrl_info->pci_dev->dev, "%s\n",
  1537. out_of_memory_msg);
  1538. rc = -ENOMEM;
  1539. goto out;
  1540. }
  1541. }
  1542. num_new_devices = num_physicals + num_logicals;
  1543. new_device_list = kmalloc_array(num_new_devices,
  1544. sizeof(*new_device_list),
  1545. GFP_KERNEL);
  1546. if (!new_device_list) {
  1547. dev_warn(&ctrl_info->pci_dev->dev, "%s\n", out_of_memory_msg);
  1548. rc = -ENOMEM;
  1549. goto out;
  1550. }
  1551. for (i = 0; i < num_new_devices; i++) {
  1552. device = kzalloc(sizeof(*device), GFP_KERNEL);
  1553. if (!device) {
  1554. dev_warn(&ctrl_info->pci_dev->dev, "%s\n",
  1555. out_of_memory_msg);
  1556. rc = -ENOMEM;
  1557. goto out;
  1558. }
  1559. list_add_tail(&device->new_device_list_entry,
  1560. &new_device_list_head);
  1561. }
  1562. device = NULL;
  1563. num_valid_devices = 0;
  1564. for (i = 0; i < num_new_devices; i++) {
  1565. if (i < num_physicals) {
  1566. is_physical_device = true;
  1567. phys_lun_ext_entry = &physdev_list->lun_entries[i];
  1568. log_lun_ext_entry = NULL;
  1569. scsi3addr = phys_lun_ext_entry->lunid;
  1570. } else {
  1571. is_physical_device = false;
  1572. phys_lun_ext_entry = NULL;
  1573. log_lun_ext_entry =
  1574. &logdev_list->lun_entries[i - num_physicals];
  1575. scsi3addr = log_lun_ext_entry->lunid;
  1576. }
  1577. if (is_physical_device && pqi_skip_device(scsi3addr))
  1578. continue;
  1579. if (device)
  1580. device = list_next_entry(device, new_device_list_entry);
  1581. else
  1582. device = list_first_entry(&new_device_list_head,
  1583. struct pqi_scsi_dev, new_device_list_entry);
  1584. memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
  1585. device->is_physical_device = is_physical_device;
  1586. if (!is_physical_device)
  1587. device->is_external_raid_device =
  1588. pqi_is_external_raid_addr(scsi3addr);
  1589. /* Gather information about the device. */
  1590. rc = pqi_get_device_info(ctrl_info, device);
  1591. if (rc == -ENOMEM) {
  1592. dev_warn(&ctrl_info->pci_dev->dev, "%s\n",
  1593. out_of_memory_msg);
  1594. goto out;
  1595. }
  1596. if (rc) {
  1597. if (device->is_physical_device)
  1598. dev_warn(&ctrl_info->pci_dev->dev,
  1599. "obtaining device info failed, skipping physical device %016llx\n",
  1600. get_unaligned_be64(
  1601. &phys_lun_ext_entry->wwid));
  1602. else
  1603. dev_warn(&ctrl_info->pci_dev->dev,
  1604. "obtaining device info failed, skipping logical device %08x%08x\n",
  1605. *((u32 *)&device->scsi3addr),
  1606. *((u32 *)&device->scsi3addr[4]));
  1607. rc = 0;
  1608. continue;
  1609. }
  1610. if (!pqi_is_supported_device(device))
  1611. continue;
  1612. pqi_assign_bus_target_lun(device);
  1613. if (device->is_physical_device) {
  1614. device->wwid = phys_lun_ext_entry->wwid;
  1615. if ((phys_lun_ext_entry->device_flags &
  1616. REPORT_PHYS_LUN_DEV_FLAG_AIO_ENABLED) &&
  1617. phys_lun_ext_entry->aio_handle)
  1618. device->aio_enabled = true;
  1619. } else {
  1620. memcpy(device->volume_id, log_lun_ext_entry->volume_id,
  1621. sizeof(device->volume_id));
  1622. }
  1623. switch (device->devtype) {
  1624. case TYPE_DISK:
  1625. case TYPE_ZBC:
  1626. case TYPE_ENCLOSURE:
  1627. if (device->is_physical_device) {
  1628. device->sas_address =
  1629. get_unaligned_be64(&device->wwid);
  1630. if (device->devtype == TYPE_DISK ||
  1631. device->devtype == TYPE_ZBC) {
  1632. device->aio_handle =
  1633. phys_lun_ext_entry->aio_handle;
  1634. pqi_get_physical_disk_info(ctrl_info,
  1635. device, id_phys);
  1636. }
  1637. }
  1638. break;
  1639. }
  1640. new_device_list[num_valid_devices++] = device;
  1641. }
  1642. pqi_update_device_list(ctrl_info, new_device_list, num_valid_devices);
  1643. out:
  1644. list_for_each_entry_safe(device, next, &new_device_list_head,
  1645. new_device_list_entry) {
  1646. if (device->keep_device)
  1647. continue;
  1648. list_del(&device->new_device_list_entry);
  1649. pqi_free_device(device);
  1650. }
  1651. kfree(new_device_list);
  1652. kfree(physdev_list);
  1653. kfree(logdev_list);
  1654. kfree(id_phys);
  1655. return rc;
  1656. }
  1657. static void pqi_remove_all_scsi_devices(struct pqi_ctrl_info *ctrl_info)
  1658. {
  1659. unsigned long flags;
  1660. struct pqi_scsi_dev *device;
  1661. while (1) {
  1662. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  1663. device = list_first_entry_or_null(&ctrl_info->scsi_device_list,
  1664. struct pqi_scsi_dev, scsi_device_list_entry);
  1665. if (device)
  1666. list_del(&device->scsi_device_list_entry);
  1667. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock,
  1668. flags);
  1669. if (!device)
  1670. break;
  1671. if (device->sdev)
  1672. pqi_remove_device(ctrl_info, device);
  1673. pqi_free_device(device);
  1674. }
  1675. }
  1676. static int pqi_scan_scsi_devices(struct pqi_ctrl_info *ctrl_info)
  1677. {
  1678. int rc;
  1679. if (pqi_ctrl_offline(ctrl_info))
  1680. return -ENXIO;
  1681. mutex_lock(&ctrl_info->scan_mutex);
  1682. rc = pqi_update_scsi_devices(ctrl_info);
  1683. if (rc)
  1684. pqi_schedule_rescan_worker_delayed(ctrl_info);
  1685. mutex_unlock(&ctrl_info->scan_mutex);
  1686. return rc;
  1687. }
  1688. static void pqi_scan_start(struct Scsi_Host *shost)
  1689. {
  1690. pqi_scan_scsi_devices(shost_to_hba(shost));
  1691. }
  1692. /* Returns TRUE if scan is finished. */
  1693. static int pqi_scan_finished(struct Scsi_Host *shost,
  1694. unsigned long elapsed_time)
  1695. {
  1696. struct pqi_ctrl_info *ctrl_info;
  1697. ctrl_info = shost_priv(shost);
  1698. return !mutex_is_locked(&ctrl_info->scan_mutex);
  1699. }
  1700. static void pqi_wait_until_scan_finished(struct pqi_ctrl_info *ctrl_info)
  1701. {
  1702. mutex_lock(&ctrl_info->scan_mutex);
  1703. mutex_unlock(&ctrl_info->scan_mutex);
  1704. }
  1705. static void pqi_wait_until_lun_reset_finished(struct pqi_ctrl_info *ctrl_info)
  1706. {
  1707. mutex_lock(&ctrl_info->lun_reset_mutex);
  1708. mutex_unlock(&ctrl_info->lun_reset_mutex);
  1709. }
  1710. static inline void pqi_set_encryption_info(
  1711. struct pqi_encryption_info *encryption_info, struct raid_map *raid_map,
  1712. u64 first_block)
  1713. {
  1714. u32 volume_blk_size;
  1715. /*
  1716. * Set the encryption tweak values based on logical block address.
  1717. * If the block size is 512, the tweak value is equal to the LBA.
  1718. * For other block sizes, tweak value is (LBA * block size) / 512.
  1719. */
  1720. volume_blk_size = get_unaligned_le32(&raid_map->volume_blk_size);
  1721. if (volume_blk_size != 512)
  1722. first_block = (first_block * volume_blk_size) / 512;
  1723. encryption_info->data_encryption_key_index =
  1724. get_unaligned_le16(&raid_map->data_encryption_key_index);
  1725. encryption_info->encrypt_tweak_lower = lower_32_bits(first_block);
  1726. encryption_info->encrypt_tweak_upper = upper_32_bits(first_block);
  1727. }
  1728. /*
  1729. * Attempt to perform RAID bypass mapping for a logical volume I/O.
  1730. */
  1731. #define PQI_RAID_BYPASS_INELIGIBLE 1
  1732. static int pqi_raid_bypass_submit_scsi_cmd(struct pqi_ctrl_info *ctrl_info,
  1733. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  1734. struct pqi_queue_group *queue_group)
  1735. {
  1736. struct raid_map *raid_map;
  1737. bool is_write = false;
  1738. u32 map_index;
  1739. u64 first_block;
  1740. u64 last_block;
  1741. u32 block_cnt;
  1742. u32 blocks_per_row;
  1743. u64 first_row;
  1744. u64 last_row;
  1745. u32 first_row_offset;
  1746. u32 last_row_offset;
  1747. u32 first_column;
  1748. u32 last_column;
  1749. u64 r0_first_row;
  1750. u64 r0_last_row;
  1751. u32 r5or6_blocks_per_row;
  1752. u64 r5or6_first_row;
  1753. u64 r5or6_last_row;
  1754. u32 r5or6_first_row_offset;
  1755. u32 r5or6_last_row_offset;
  1756. u32 r5or6_first_column;
  1757. u32 r5or6_last_column;
  1758. u16 data_disks_per_row;
  1759. u32 total_disks_per_row;
  1760. u16 layout_map_count;
  1761. u32 stripesize;
  1762. u16 strip_size;
  1763. u32 first_group;
  1764. u32 last_group;
  1765. u32 current_group;
  1766. u32 map_row;
  1767. u32 aio_handle;
  1768. u64 disk_block;
  1769. u32 disk_block_cnt;
  1770. u8 cdb[16];
  1771. u8 cdb_length;
  1772. int offload_to_mirror;
  1773. struct pqi_encryption_info *encryption_info_ptr;
  1774. struct pqi_encryption_info encryption_info;
  1775. #if BITS_PER_LONG == 32
  1776. u64 tmpdiv;
  1777. #endif
  1778. /* Check for valid opcode, get LBA and block count. */
  1779. switch (scmd->cmnd[0]) {
  1780. case WRITE_6:
  1781. is_write = true;
  1782. /* fall through */
  1783. case READ_6:
  1784. first_block = (u64)(((scmd->cmnd[1] & 0x1f) << 16) |
  1785. (scmd->cmnd[2] << 8) | scmd->cmnd[3]);
  1786. block_cnt = (u32)scmd->cmnd[4];
  1787. if (block_cnt == 0)
  1788. block_cnt = 256;
  1789. break;
  1790. case WRITE_10:
  1791. is_write = true;
  1792. /* fall through */
  1793. case READ_10:
  1794. first_block = (u64)get_unaligned_be32(&scmd->cmnd[2]);
  1795. block_cnt = (u32)get_unaligned_be16(&scmd->cmnd[7]);
  1796. break;
  1797. case WRITE_12:
  1798. is_write = true;
  1799. /* fall through */
  1800. case READ_12:
  1801. first_block = (u64)get_unaligned_be32(&scmd->cmnd[2]);
  1802. block_cnt = get_unaligned_be32(&scmd->cmnd[6]);
  1803. break;
  1804. case WRITE_16:
  1805. is_write = true;
  1806. /* fall through */
  1807. case READ_16:
  1808. first_block = get_unaligned_be64(&scmd->cmnd[2]);
  1809. block_cnt = get_unaligned_be32(&scmd->cmnd[10]);
  1810. break;
  1811. default:
  1812. /* Process via normal I/O path. */
  1813. return PQI_RAID_BYPASS_INELIGIBLE;
  1814. }
  1815. /* Check for write to non-RAID-0. */
  1816. if (is_write && device->raid_level != SA_RAID_0)
  1817. return PQI_RAID_BYPASS_INELIGIBLE;
  1818. if (unlikely(block_cnt == 0))
  1819. return PQI_RAID_BYPASS_INELIGIBLE;
  1820. last_block = first_block + block_cnt - 1;
  1821. raid_map = device->raid_map;
  1822. /* Check for invalid block or wraparound. */
  1823. if (last_block >= get_unaligned_le64(&raid_map->volume_blk_cnt) ||
  1824. last_block < first_block)
  1825. return PQI_RAID_BYPASS_INELIGIBLE;
  1826. data_disks_per_row = get_unaligned_le16(&raid_map->data_disks_per_row);
  1827. strip_size = get_unaligned_le16(&raid_map->strip_size);
  1828. layout_map_count = get_unaligned_le16(&raid_map->layout_map_count);
  1829. /* Calculate stripe information for the request. */
  1830. blocks_per_row = data_disks_per_row * strip_size;
  1831. #if BITS_PER_LONG == 32
  1832. tmpdiv = first_block;
  1833. do_div(tmpdiv, blocks_per_row);
  1834. first_row = tmpdiv;
  1835. tmpdiv = last_block;
  1836. do_div(tmpdiv, blocks_per_row);
  1837. last_row = tmpdiv;
  1838. first_row_offset = (u32)(first_block - (first_row * blocks_per_row));
  1839. last_row_offset = (u32)(last_block - (last_row * blocks_per_row));
  1840. tmpdiv = first_row_offset;
  1841. do_div(tmpdiv, strip_size);
  1842. first_column = tmpdiv;
  1843. tmpdiv = last_row_offset;
  1844. do_div(tmpdiv, strip_size);
  1845. last_column = tmpdiv;
  1846. #else
  1847. first_row = first_block / blocks_per_row;
  1848. last_row = last_block / blocks_per_row;
  1849. first_row_offset = (u32)(first_block - (first_row * blocks_per_row));
  1850. last_row_offset = (u32)(last_block - (last_row * blocks_per_row));
  1851. first_column = first_row_offset / strip_size;
  1852. last_column = last_row_offset / strip_size;
  1853. #endif
  1854. /* If this isn't a single row/column then give to the controller. */
  1855. if (first_row != last_row || first_column != last_column)
  1856. return PQI_RAID_BYPASS_INELIGIBLE;
  1857. /* Proceeding with driver mapping. */
  1858. total_disks_per_row = data_disks_per_row +
  1859. get_unaligned_le16(&raid_map->metadata_disks_per_row);
  1860. map_row = ((u32)(first_row >> raid_map->parity_rotation_shift)) %
  1861. get_unaligned_le16(&raid_map->row_cnt);
  1862. map_index = (map_row * total_disks_per_row) + first_column;
  1863. /* RAID 1 */
  1864. if (device->raid_level == SA_RAID_1) {
  1865. if (device->offload_to_mirror)
  1866. map_index += data_disks_per_row;
  1867. device->offload_to_mirror = !device->offload_to_mirror;
  1868. } else if (device->raid_level == SA_RAID_ADM) {
  1869. /* RAID ADM */
  1870. /*
  1871. * Handles N-way mirrors (R1-ADM) and R10 with # of drives
  1872. * divisible by 3.
  1873. */
  1874. offload_to_mirror = device->offload_to_mirror;
  1875. if (offload_to_mirror == 0) {
  1876. /* use physical disk in the first mirrored group. */
  1877. map_index %= data_disks_per_row;
  1878. } else {
  1879. do {
  1880. /*
  1881. * Determine mirror group that map_index
  1882. * indicates.
  1883. */
  1884. current_group = map_index / data_disks_per_row;
  1885. if (offload_to_mirror != current_group) {
  1886. if (current_group <
  1887. layout_map_count - 1) {
  1888. /*
  1889. * Select raid index from
  1890. * next group.
  1891. */
  1892. map_index += data_disks_per_row;
  1893. current_group++;
  1894. } else {
  1895. /*
  1896. * Select raid index from first
  1897. * group.
  1898. */
  1899. map_index %= data_disks_per_row;
  1900. current_group = 0;
  1901. }
  1902. }
  1903. } while (offload_to_mirror != current_group);
  1904. }
  1905. /* Set mirror group to use next time. */
  1906. offload_to_mirror =
  1907. (offload_to_mirror >= layout_map_count - 1) ?
  1908. 0 : offload_to_mirror + 1;
  1909. WARN_ON(offload_to_mirror >= layout_map_count);
  1910. device->offload_to_mirror = offload_to_mirror;
  1911. /*
  1912. * Avoid direct use of device->offload_to_mirror within this
  1913. * function since multiple threads might simultaneously
  1914. * increment it beyond the range of device->layout_map_count -1.
  1915. */
  1916. } else if ((device->raid_level == SA_RAID_5 ||
  1917. device->raid_level == SA_RAID_6) && layout_map_count > 1) {
  1918. /* RAID 50/60 */
  1919. /* Verify first and last block are in same RAID group */
  1920. r5or6_blocks_per_row = strip_size * data_disks_per_row;
  1921. stripesize = r5or6_blocks_per_row * layout_map_count;
  1922. #if BITS_PER_LONG == 32
  1923. tmpdiv = first_block;
  1924. first_group = do_div(tmpdiv, stripesize);
  1925. tmpdiv = first_group;
  1926. do_div(tmpdiv, r5or6_blocks_per_row);
  1927. first_group = tmpdiv;
  1928. tmpdiv = last_block;
  1929. last_group = do_div(tmpdiv, stripesize);
  1930. tmpdiv = last_group;
  1931. do_div(tmpdiv, r5or6_blocks_per_row);
  1932. last_group = tmpdiv;
  1933. #else
  1934. first_group = (first_block % stripesize) / r5or6_blocks_per_row;
  1935. last_group = (last_block % stripesize) / r5or6_blocks_per_row;
  1936. #endif
  1937. if (first_group != last_group)
  1938. return PQI_RAID_BYPASS_INELIGIBLE;
  1939. /* Verify request is in a single row of RAID 5/6 */
  1940. #if BITS_PER_LONG == 32
  1941. tmpdiv = first_block;
  1942. do_div(tmpdiv, stripesize);
  1943. first_row = r5or6_first_row = r0_first_row = tmpdiv;
  1944. tmpdiv = last_block;
  1945. do_div(tmpdiv, stripesize);
  1946. r5or6_last_row = r0_last_row = tmpdiv;
  1947. #else
  1948. first_row = r5or6_first_row = r0_first_row =
  1949. first_block / stripesize;
  1950. r5or6_last_row = r0_last_row = last_block / stripesize;
  1951. #endif
  1952. if (r5or6_first_row != r5or6_last_row)
  1953. return PQI_RAID_BYPASS_INELIGIBLE;
  1954. /* Verify request is in a single column */
  1955. #if BITS_PER_LONG == 32
  1956. tmpdiv = first_block;
  1957. first_row_offset = do_div(tmpdiv, stripesize);
  1958. tmpdiv = first_row_offset;
  1959. first_row_offset = (u32)do_div(tmpdiv, r5or6_blocks_per_row);
  1960. r5or6_first_row_offset = first_row_offset;
  1961. tmpdiv = last_block;
  1962. r5or6_last_row_offset = do_div(tmpdiv, stripesize);
  1963. tmpdiv = r5or6_last_row_offset;
  1964. r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
  1965. tmpdiv = r5or6_first_row_offset;
  1966. do_div(tmpdiv, strip_size);
  1967. first_column = r5or6_first_column = tmpdiv;
  1968. tmpdiv = r5or6_last_row_offset;
  1969. do_div(tmpdiv, strip_size);
  1970. r5or6_last_column = tmpdiv;
  1971. #else
  1972. first_row_offset = r5or6_first_row_offset =
  1973. (u32)((first_block % stripesize) %
  1974. r5or6_blocks_per_row);
  1975. r5or6_last_row_offset =
  1976. (u32)((last_block % stripesize) %
  1977. r5or6_blocks_per_row);
  1978. first_column = r5or6_first_row_offset / strip_size;
  1979. r5or6_first_column = first_column;
  1980. r5or6_last_column = r5or6_last_row_offset / strip_size;
  1981. #endif
  1982. if (r5or6_first_column != r5or6_last_column)
  1983. return PQI_RAID_BYPASS_INELIGIBLE;
  1984. /* Request is eligible */
  1985. map_row =
  1986. ((u32)(first_row >> raid_map->parity_rotation_shift)) %
  1987. get_unaligned_le16(&raid_map->row_cnt);
  1988. map_index = (first_group *
  1989. (get_unaligned_le16(&raid_map->row_cnt) *
  1990. total_disks_per_row)) +
  1991. (map_row * total_disks_per_row) + first_column;
  1992. }
  1993. if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
  1994. return PQI_RAID_BYPASS_INELIGIBLE;
  1995. aio_handle = raid_map->disk_data[map_index].aio_handle;
  1996. disk_block = get_unaligned_le64(&raid_map->disk_starting_blk) +
  1997. first_row * strip_size +
  1998. (first_row_offset - first_column * strip_size);
  1999. disk_block_cnt = block_cnt;
  2000. /* Handle differing logical/physical block sizes. */
  2001. if (raid_map->phys_blk_shift) {
  2002. disk_block <<= raid_map->phys_blk_shift;
  2003. disk_block_cnt <<= raid_map->phys_blk_shift;
  2004. }
  2005. if (unlikely(disk_block_cnt > 0xffff))
  2006. return PQI_RAID_BYPASS_INELIGIBLE;
  2007. /* Build the new CDB for the physical disk I/O. */
  2008. if (disk_block > 0xffffffff) {
  2009. cdb[0] = is_write ? WRITE_16 : READ_16;
  2010. cdb[1] = 0;
  2011. put_unaligned_be64(disk_block, &cdb[2]);
  2012. put_unaligned_be32(disk_block_cnt, &cdb[10]);
  2013. cdb[14] = 0;
  2014. cdb[15] = 0;
  2015. cdb_length = 16;
  2016. } else {
  2017. cdb[0] = is_write ? WRITE_10 : READ_10;
  2018. cdb[1] = 0;
  2019. put_unaligned_be32((u32)disk_block, &cdb[2]);
  2020. cdb[6] = 0;
  2021. put_unaligned_be16((u16)disk_block_cnt, &cdb[7]);
  2022. cdb[9] = 0;
  2023. cdb_length = 10;
  2024. }
  2025. if (get_unaligned_le16(&raid_map->flags) &
  2026. RAID_MAP_ENCRYPTION_ENABLED) {
  2027. pqi_set_encryption_info(&encryption_info, raid_map,
  2028. first_block);
  2029. encryption_info_ptr = &encryption_info;
  2030. } else {
  2031. encryption_info_ptr = NULL;
  2032. }
  2033. return pqi_aio_submit_io(ctrl_info, scmd, aio_handle,
  2034. cdb, cdb_length, queue_group, encryption_info_ptr, true);
  2035. }
  2036. #define PQI_STATUS_IDLE 0x0
  2037. #define PQI_CREATE_ADMIN_QUEUE_PAIR 1
  2038. #define PQI_DELETE_ADMIN_QUEUE_PAIR 2
  2039. #define PQI_DEVICE_STATE_POWER_ON_AND_RESET 0x0
  2040. #define PQI_DEVICE_STATE_STATUS_AVAILABLE 0x1
  2041. #define PQI_DEVICE_STATE_ALL_REGISTERS_READY 0x2
  2042. #define PQI_DEVICE_STATE_ADMIN_QUEUE_PAIR_READY 0x3
  2043. #define PQI_DEVICE_STATE_ERROR 0x4
  2044. #define PQI_MODE_READY_TIMEOUT_SECS 30
  2045. #define PQI_MODE_READY_POLL_INTERVAL_MSECS 1
  2046. static int pqi_wait_for_pqi_mode_ready(struct pqi_ctrl_info *ctrl_info)
  2047. {
  2048. struct pqi_device_registers __iomem *pqi_registers;
  2049. unsigned long timeout;
  2050. u64 signature;
  2051. u8 status;
  2052. pqi_registers = ctrl_info->pqi_registers;
  2053. timeout = (PQI_MODE_READY_TIMEOUT_SECS * HZ) + jiffies;
  2054. while (1) {
  2055. signature = readq(&pqi_registers->signature);
  2056. if (memcmp(&signature, PQI_DEVICE_SIGNATURE,
  2057. sizeof(signature)) == 0)
  2058. break;
  2059. if (time_after(jiffies, timeout)) {
  2060. dev_err(&ctrl_info->pci_dev->dev,
  2061. "timed out waiting for PQI signature\n");
  2062. return -ETIMEDOUT;
  2063. }
  2064. msleep(PQI_MODE_READY_POLL_INTERVAL_MSECS);
  2065. }
  2066. while (1) {
  2067. status = readb(&pqi_registers->function_and_status_code);
  2068. if (status == PQI_STATUS_IDLE)
  2069. break;
  2070. if (time_after(jiffies, timeout)) {
  2071. dev_err(&ctrl_info->pci_dev->dev,
  2072. "timed out waiting for PQI IDLE\n");
  2073. return -ETIMEDOUT;
  2074. }
  2075. msleep(PQI_MODE_READY_POLL_INTERVAL_MSECS);
  2076. }
  2077. while (1) {
  2078. if (readl(&pqi_registers->device_status) ==
  2079. PQI_DEVICE_STATE_ALL_REGISTERS_READY)
  2080. break;
  2081. if (time_after(jiffies, timeout)) {
  2082. dev_err(&ctrl_info->pci_dev->dev,
  2083. "timed out waiting for PQI all registers ready\n");
  2084. return -ETIMEDOUT;
  2085. }
  2086. msleep(PQI_MODE_READY_POLL_INTERVAL_MSECS);
  2087. }
  2088. return 0;
  2089. }
  2090. static inline void pqi_aio_path_disabled(struct pqi_io_request *io_request)
  2091. {
  2092. struct pqi_scsi_dev *device;
  2093. device = io_request->scmd->device->hostdata;
  2094. device->raid_bypass_enabled = false;
  2095. device->aio_enabled = false;
  2096. }
  2097. static inline void pqi_take_device_offline(struct scsi_device *sdev, char *path)
  2098. {
  2099. struct pqi_ctrl_info *ctrl_info;
  2100. struct pqi_scsi_dev *device;
  2101. device = sdev->hostdata;
  2102. if (device->device_offline)
  2103. return;
  2104. device->device_offline = true;
  2105. scsi_device_set_state(sdev, SDEV_OFFLINE);
  2106. ctrl_info = shost_to_hba(sdev->host);
  2107. pqi_schedule_rescan_worker(ctrl_info);
  2108. dev_err(&ctrl_info->pci_dev->dev, "offlined %s scsi %d:%d:%d:%d\n",
  2109. path, ctrl_info->scsi_host->host_no, device->bus,
  2110. device->target, device->lun);
  2111. }
  2112. static void pqi_process_raid_io_error(struct pqi_io_request *io_request)
  2113. {
  2114. u8 scsi_status;
  2115. u8 host_byte;
  2116. struct scsi_cmnd *scmd;
  2117. struct pqi_raid_error_info *error_info;
  2118. size_t sense_data_length;
  2119. int residual_count;
  2120. int xfer_count;
  2121. struct scsi_sense_hdr sshdr;
  2122. scmd = io_request->scmd;
  2123. if (!scmd)
  2124. return;
  2125. error_info = io_request->error_info;
  2126. scsi_status = error_info->status;
  2127. host_byte = DID_OK;
  2128. switch (error_info->data_out_result) {
  2129. case PQI_DATA_IN_OUT_GOOD:
  2130. break;
  2131. case PQI_DATA_IN_OUT_UNDERFLOW:
  2132. xfer_count =
  2133. get_unaligned_le32(&error_info->data_out_transferred);
  2134. residual_count = scsi_bufflen(scmd) - xfer_count;
  2135. scsi_set_resid(scmd, residual_count);
  2136. if (xfer_count < scmd->underflow)
  2137. host_byte = DID_SOFT_ERROR;
  2138. break;
  2139. case PQI_DATA_IN_OUT_UNSOLICITED_ABORT:
  2140. case PQI_DATA_IN_OUT_ABORTED:
  2141. host_byte = DID_ABORT;
  2142. break;
  2143. case PQI_DATA_IN_OUT_TIMEOUT:
  2144. host_byte = DID_TIME_OUT;
  2145. break;
  2146. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW:
  2147. case PQI_DATA_IN_OUT_PROTOCOL_ERROR:
  2148. case PQI_DATA_IN_OUT_BUFFER_ERROR:
  2149. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA:
  2150. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE:
  2151. case PQI_DATA_IN_OUT_ERROR:
  2152. case PQI_DATA_IN_OUT_HARDWARE_ERROR:
  2153. case PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR:
  2154. case PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT:
  2155. case PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED:
  2156. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED:
  2157. case PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED:
  2158. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST:
  2159. case PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION:
  2160. case PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED:
  2161. case PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ:
  2162. default:
  2163. host_byte = DID_ERROR;
  2164. break;
  2165. }
  2166. sense_data_length = get_unaligned_le16(&error_info->sense_data_length);
  2167. if (sense_data_length == 0)
  2168. sense_data_length =
  2169. get_unaligned_le16(&error_info->response_data_length);
  2170. if (sense_data_length) {
  2171. if (sense_data_length > sizeof(error_info->data))
  2172. sense_data_length = sizeof(error_info->data);
  2173. if (scsi_status == SAM_STAT_CHECK_CONDITION &&
  2174. scsi_normalize_sense(error_info->data,
  2175. sense_data_length, &sshdr) &&
  2176. sshdr.sense_key == HARDWARE_ERROR &&
  2177. sshdr.asc == 0x3e &&
  2178. sshdr.ascq == 0x1) {
  2179. pqi_take_device_offline(scmd->device, "RAID");
  2180. host_byte = DID_NO_CONNECT;
  2181. }
  2182. if (sense_data_length > SCSI_SENSE_BUFFERSIZE)
  2183. sense_data_length = SCSI_SENSE_BUFFERSIZE;
  2184. memcpy(scmd->sense_buffer, error_info->data,
  2185. sense_data_length);
  2186. }
  2187. scmd->result = scsi_status;
  2188. set_host_byte(scmd, host_byte);
  2189. }
  2190. static void pqi_process_aio_io_error(struct pqi_io_request *io_request)
  2191. {
  2192. u8 scsi_status;
  2193. u8 host_byte;
  2194. struct scsi_cmnd *scmd;
  2195. struct pqi_aio_error_info *error_info;
  2196. size_t sense_data_length;
  2197. int residual_count;
  2198. int xfer_count;
  2199. bool device_offline;
  2200. scmd = io_request->scmd;
  2201. error_info = io_request->error_info;
  2202. host_byte = DID_OK;
  2203. sense_data_length = 0;
  2204. device_offline = false;
  2205. switch (error_info->service_response) {
  2206. case PQI_AIO_SERV_RESPONSE_COMPLETE:
  2207. scsi_status = error_info->status;
  2208. break;
  2209. case PQI_AIO_SERV_RESPONSE_FAILURE:
  2210. switch (error_info->status) {
  2211. case PQI_AIO_STATUS_IO_ABORTED:
  2212. scsi_status = SAM_STAT_TASK_ABORTED;
  2213. break;
  2214. case PQI_AIO_STATUS_UNDERRUN:
  2215. scsi_status = SAM_STAT_GOOD;
  2216. residual_count = get_unaligned_le32(
  2217. &error_info->residual_count);
  2218. scsi_set_resid(scmd, residual_count);
  2219. xfer_count = scsi_bufflen(scmd) - residual_count;
  2220. if (xfer_count < scmd->underflow)
  2221. host_byte = DID_SOFT_ERROR;
  2222. break;
  2223. case PQI_AIO_STATUS_OVERRUN:
  2224. scsi_status = SAM_STAT_GOOD;
  2225. break;
  2226. case PQI_AIO_STATUS_AIO_PATH_DISABLED:
  2227. pqi_aio_path_disabled(io_request);
  2228. scsi_status = SAM_STAT_GOOD;
  2229. io_request->status = -EAGAIN;
  2230. break;
  2231. case PQI_AIO_STATUS_NO_PATH_TO_DEVICE:
  2232. case PQI_AIO_STATUS_INVALID_DEVICE:
  2233. if (!io_request->raid_bypass) {
  2234. device_offline = true;
  2235. pqi_take_device_offline(scmd->device, "AIO");
  2236. host_byte = DID_NO_CONNECT;
  2237. }
  2238. scsi_status = SAM_STAT_CHECK_CONDITION;
  2239. break;
  2240. case PQI_AIO_STATUS_IO_ERROR:
  2241. default:
  2242. scsi_status = SAM_STAT_CHECK_CONDITION;
  2243. break;
  2244. }
  2245. break;
  2246. case PQI_AIO_SERV_RESPONSE_TMF_COMPLETE:
  2247. case PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED:
  2248. scsi_status = SAM_STAT_GOOD;
  2249. break;
  2250. case PQI_AIO_SERV_RESPONSE_TMF_REJECTED:
  2251. case PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN:
  2252. default:
  2253. scsi_status = SAM_STAT_CHECK_CONDITION;
  2254. break;
  2255. }
  2256. if (error_info->data_present) {
  2257. sense_data_length =
  2258. get_unaligned_le16(&error_info->data_length);
  2259. if (sense_data_length) {
  2260. if (sense_data_length > sizeof(error_info->data))
  2261. sense_data_length = sizeof(error_info->data);
  2262. if (sense_data_length > SCSI_SENSE_BUFFERSIZE)
  2263. sense_data_length = SCSI_SENSE_BUFFERSIZE;
  2264. memcpy(scmd->sense_buffer, error_info->data,
  2265. sense_data_length);
  2266. }
  2267. }
  2268. if (device_offline && sense_data_length == 0)
  2269. scsi_build_sense_buffer(0, scmd->sense_buffer, HARDWARE_ERROR,
  2270. 0x3e, 0x1);
  2271. scmd->result = scsi_status;
  2272. set_host_byte(scmd, host_byte);
  2273. }
  2274. static void pqi_process_io_error(unsigned int iu_type,
  2275. struct pqi_io_request *io_request)
  2276. {
  2277. switch (iu_type) {
  2278. case PQI_RESPONSE_IU_RAID_PATH_IO_ERROR:
  2279. pqi_process_raid_io_error(io_request);
  2280. break;
  2281. case PQI_RESPONSE_IU_AIO_PATH_IO_ERROR:
  2282. pqi_process_aio_io_error(io_request);
  2283. break;
  2284. }
  2285. }
  2286. static int pqi_interpret_task_management_response(
  2287. struct pqi_task_management_response *response)
  2288. {
  2289. int rc;
  2290. switch (response->response_code) {
  2291. case SOP_TMF_COMPLETE:
  2292. case SOP_TMF_FUNCTION_SUCCEEDED:
  2293. rc = 0;
  2294. break;
  2295. default:
  2296. rc = -EIO;
  2297. break;
  2298. }
  2299. return rc;
  2300. }
  2301. static unsigned int pqi_process_io_intr(struct pqi_ctrl_info *ctrl_info,
  2302. struct pqi_queue_group *queue_group)
  2303. {
  2304. unsigned int num_responses;
  2305. pqi_index_t oq_pi;
  2306. pqi_index_t oq_ci;
  2307. struct pqi_io_request *io_request;
  2308. struct pqi_io_response *response;
  2309. u16 request_id;
  2310. num_responses = 0;
  2311. oq_ci = queue_group->oq_ci_copy;
  2312. while (1) {
  2313. oq_pi = readl(queue_group->oq_pi);
  2314. if (oq_pi == oq_ci)
  2315. break;
  2316. num_responses++;
  2317. response = queue_group->oq_element_array +
  2318. (oq_ci * PQI_OPERATIONAL_OQ_ELEMENT_LENGTH);
  2319. request_id = get_unaligned_le16(&response->request_id);
  2320. WARN_ON(request_id >= ctrl_info->max_io_slots);
  2321. io_request = &ctrl_info->io_request_pool[request_id];
  2322. WARN_ON(atomic_read(&io_request->refcount) == 0);
  2323. switch (response->header.iu_type) {
  2324. case PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS:
  2325. case PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS:
  2326. if (io_request->scmd)
  2327. io_request->scmd->result = 0;
  2328. /* fall through */
  2329. case PQI_RESPONSE_IU_GENERAL_MANAGEMENT:
  2330. break;
  2331. case PQI_RESPONSE_IU_TASK_MANAGEMENT:
  2332. io_request->status =
  2333. pqi_interpret_task_management_response(
  2334. (void *)response);
  2335. break;
  2336. case PQI_RESPONSE_IU_AIO_PATH_DISABLED:
  2337. pqi_aio_path_disabled(io_request);
  2338. io_request->status = -EAGAIN;
  2339. break;
  2340. case PQI_RESPONSE_IU_RAID_PATH_IO_ERROR:
  2341. case PQI_RESPONSE_IU_AIO_PATH_IO_ERROR:
  2342. io_request->error_info = ctrl_info->error_buffer +
  2343. (get_unaligned_le16(&response->error_index) *
  2344. PQI_ERROR_BUFFER_ELEMENT_LENGTH);
  2345. pqi_process_io_error(response->header.iu_type,
  2346. io_request);
  2347. break;
  2348. default:
  2349. dev_err(&ctrl_info->pci_dev->dev,
  2350. "unexpected IU type: 0x%x\n",
  2351. response->header.iu_type);
  2352. break;
  2353. }
  2354. io_request->io_complete_callback(io_request,
  2355. io_request->context);
  2356. /*
  2357. * Note that the I/O request structure CANNOT BE TOUCHED after
  2358. * returning from the I/O completion callback!
  2359. */
  2360. oq_ci = (oq_ci + 1) % ctrl_info->num_elements_per_oq;
  2361. }
  2362. if (num_responses) {
  2363. queue_group->oq_ci_copy = oq_ci;
  2364. writel(oq_ci, queue_group->oq_ci);
  2365. }
  2366. return num_responses;
  2367. }
  2368. static inline unsigned int pqi_num_elements_free(unsigned int pi,
  2369. unsigned int ci, unsigned int elements_in_queue)
  2370. {
  2371. unsigned int num_elements_used;
  2372. if (pi >= ci)
  2373. num_elements_used = pi - ci;
  2374. else
  2375. num_elements_used = elements_in_queue - ci + pi;
  2376. return elements_in_queue - num_elements_used - 1;
  2377. }
  2378. static void pqi_send_event_ack(struct pqi_ctrl_info *ctrl_info,
  2379. struct pqi_event_acknowledge_request *iu, size_t iu_length)
  2380. {
  2381. pqi_index_t iq_pi;
  2382. pqi_index_t iq_ci;
  2383. unsigned long flags;
  2384. void *next_element;
  2385. struct pqi_queue_group *queue_group;
  2386. queue_group = &ctrl_info->queue_groups[PQI_DEFAULT_QUEUE_GROUP];
  2387. put_unaligned_le16(queue_group->oq_id, &iu->header.response_queue_id);
  2388. while (1) {
  2389. spin_lock_irqsave(&queue_group->submit_lock[RAID_PATH], flags);
  2390. iq_pi = queue_group->iq_pi_copy[RAID_PATH];
  2391. iq_ci = readl(queue_group->iq_ci[RAID_PATH]);
  2392. if (pqi_num_elements_free(iq_pi, iq_ci,
  2393. ctrl_info->num_elements_per_iq))
  2394. break;
  2395. spin_unlock_irqrestore(
  2396. &queue_group->submit_lock[RAID_PATH], flags);
  2397. if (pqi_ctrl_offline(ctrl_info))
  2398. return;
  2399. }
  2400. next_element = queue_group->iq_element_array[RAID_PATH] +
  2401. (iq_pi * PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  2402. memcpy(next_element, iu, iu_length);
  2403. iq_pi = (iq_pi + 1) % ctrl_info->num_elements_per_iq;
  2404. queue_group->iq_pi_copy[RAID_PATH] = iq_pi;
  2405. /*
  2406. * This write notifies the controller that an IU is available to be
  2407. * processed.
  2408. */
  2409. writel(iq_pi, queue_group->iq_pi[RAID_PATH]);
  2410. spin_unlock_irqrestore(&queue_group->submit_lock[RAID_PATH], flags);
  2411. }
  2412. static void pqi_acknowledge_event(struct pqi_ctrl_info *ctrl_info,
  2413. struct pqi_event *event)
  2414. {
  2415. struct pqi_event_acknowledge_request request;
  2416. memset(&request, 0, sizeof(request));
  2417. request.header.iu_type = PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT;
  2418. put_unaligned_le16(sizeof(request) - PQI_REQUEST_HEADER_LENGTH,
  2419. &request.header.iu_length);
  2420. request.event_type = event->event_type;
  2421. request.event_id = event->event_id;
  2422. request.additional_event_id = event->additional_event_id;
  2423. pqi_send_event_ack(ctrl_info, &request, sizeof(request));
  2424. }
  2425. static void pqi_event_worker(struct work_struct *work)
  2426. {
  2427. unsigned int i;
  2428. struct pqi_ctrl_info *ctrl_info;
  2429. struct pqi_event *event;
  2430. ctrl_info = container_of(work, struct pqi_ctrl_info, event_work);
  2431. pqi_ctrl_busy(ctrl_info);
  2432. pqi_wait_if_ctrl_blocked(ctrl_info, NO_TIMEOUT);
  2433. if (pqi_ctrl_offline(ctrl_info))
  2434. goto out;
  2435. pqi_schedule_rescan_worker_delayed(ctrl_info);
  2436. event = ctrl_info->events;
  2437. for (i = 0; i < PQI_NUM_SUPPORTED_EVENTS; i++) {
  2438. if (event->pending) {
  2439. event->pending = false;
  2440. pqi_acknowledge_event(ctrl_info, event);
  2441. }
  2442. event++;
  2443. }
  2444. out:
  2445. pqi_ctrl_unbusy(ctrl_info);
  2446. }
  2447. #define PQI_HEARTBEAT_TIMER_INTERVAL (10 * HZ)
  2448. static void pqi_heartbeat_timer_handler(struct timer_list *t)
  2449. {
  2450. int num_interrupts;
  2451. u32 heartbeat_count;
  2452. struct pqi_ctrl_info *ctrl_info = from_timer(ctrl_info, t,
  2453. heartbeat_timer);
  2454. pqi_check_ctrl_health(ctrl_info);
  2455. if (pqi_ctrl_offline(ctrl_info))
  2456. return;
  2457. num_interrupts = atomic_read(&ctrl_info->num_interrupts);
  2458. heartbeat_count = pqi_read_heartbeat_counter(ctrl_info);
  2459. if (num_interrupts == ctrl_info->previous_num_interrupts) {
  2460. if (heartbeat_count == ctrl_info->previous_heartbeat_count) {
  2461. dev_err(&ctrl_info->pci_dev->dev,
  2462. "no heartbeat detected - last heartbeat count: %u\n",
  2463. heartbeat_count);
  2464. pqi_take_ctrl_offline(ctrl_info);
  2465. return;
  2466. }
  2467. } else {
  2468. ctrl_info->previous_num_interrupts = num_interrupts;
  2469. }
  2470. ctrl_info->previous_heartbeat_count = heartbeat_count;
  2471. mod_timer(&ctrl_info->heartbeat_timer,
  2472. jiffies + PQI_HEARTBEAT_TIMER_INTERVAL);
  2473. }
  2474. static void pqi_start_heartbeat_timer(struct pqi_ctrl_info *ctrl_info)
  2475. {
  2476. if (!ctrl_info->heartbeat_counter)
  2477. return;
  2478. ctrl_info->previous_num_interrupts =
  2479. atomic_read(&ctrl_info->num_interrupts);
  2480. ctrl_info->previous_heartbeat_count =
  2481. pqi_read_heartbeat_counter(ctrl_info);
  2482. ctrl_info->heartbeat_timer.expires =
  2483. jiffies + PQI_HEARTBEAT_TIMER_INTERVAL;
  2484. add_timer(&ctrl_info->heartbeat_timer);
  2485. }
  2486. static inline void pqi_stop_heartbeat_timer(struct pqi_ctrl_info *ctrl_info)
  2487. {
  2488. del_timer_sync(&ctrl_info->heartbeat_timer);
  2489. }
  2490. static inline int pqi_event_type_to_event_index(unsigned int event_type)
  2491. {
  2492. int index;
  2493. for (index = 0; index < ARRAY_SIZE(pqi_supported_event_types); index++)
  2494. if (event_type == pqi_supported_event_types[index])
  2495. return index;
  2496. return -1;
  2497. }
  2498. static inline bool pqi_is_supported_event(unsigned int event_type)
  2499. {
  2500. return pqi_event_type_to_event_index(event_type) != -1;
  2501. }
  2502. static unsigned int pqi_process_event_intr(struct pqi_ctrl_info *ctrl_info)
  2503. {
  2504. unsigned int num_events;
  2505. pqi_index_t oq_pi;
  2506. pqi_index_t oq_ci;
  2507. struct pqi_event_queue *event_queue;
  2508. struct pqi_event_response *response;
  2509. struct pqi_event *event;
  2510. int event_index;
  2511. event_queue = &ctrl_info->event_queue;
  2512. num_events = 0;
  2513. oq_ci = event_queue->oq_ci_copy;
  2514. while (1) {
  2515. oq_pi = readl(event_queue->oq_pi);
  2516. if (oq_pi == oq_ci)
  2517. break;
  2518. num_events++;
  2519. response = event_queue->oq_element_array +
  2520. (oq_ci * PQI_EVENT_OQ_ELEMENT_LENGTH);
  2521. event_index =
  2522. pqi_event_type_to_event_index(response->event_type);
  2523. if (event_index >= 0) {
  2524. if (response->request_acknowlege) {
  2525. event = &ctrl_info->events[event_index];
  2526. event->pending = true;
  2527. event->event_type = response->event_type;
  2528. event->event_id = response->event_id;
  2529. event->additional_event_id =
  2530. response->additional_event_id;
  2531. }
  2532. }
  2533. oq_ci = (oq_ci + 1) % PQI_NUM_EVENT_QUEUE_ELEMENTS;
  2534. }
  2535. if (num_events) {
  2536. event_queue->oq_ci_copy = oq_ci;
  2537. writel(oq_ci, event_queue->oq_ci);
  2538. schedule_work(&ctrl_info->event_work);
  2539. }
  2540. return num_events;
  2541. }
  2542. #define PQI_LEGACY_INTX_MASK 0x1
  2543. static inline void pqi_configure_legacy_intx(struct pqi_ctrl_info *ctrl_info,
  2544. bool enable_intx)
  2545. {
  2546. u32 intx_mask;
  2547. struct pqi_device_registers __iomem *pqi_registers;
  2548. volatile void __iomem *register_addr;
  2549. pqi_registers = ctrl_info->pqi_registers;
  2550. if (enable_intx)
  2551. register_addr = &pqi_registers->legacy_intx_mask_clear;
  2552. else
  2553. register_addr = &pqi_registers->legacy_intx_mask_set;
  2554. intx_mask = readl(register_addr);
  2555. intx_mask |= PQI_LEGACY_INTX_MASK;
  2556. writel(intx_mask, register_addr);
  2557. }
  2558. static void pqi_change_irq_mode(struct pqi_ctrl_info *ctrl_info,
  2559. enum pqi_irq_mode new_mode)
  2560. {
  2561. switch (ctrl_info->irq_mode) {
  2562. case IRQ_MODE_MSIX:
  2563. switch (new_mode) {
  2564. case IRQ_MODE_MSIX:
  2565. break;
  2566. case IRQ_MODE_INTX:
  2567. pqi_configure_legacy_intx(ctrl_info, true);
  2568. sis_enable_intx(ctrl_info);
  2569. break;
  2570. case IRQ_MODE_NONE:
  2571. break;
  2572. }
  2573. break;
  2574. case IRQ_MODE_INTX:
  2575. switch (new_mode) {
  2576. case IRQ_MODE_MSIX:
  2577. pqi_configure_legacy_intx(ctrl_info, false);
  2578. sis_enable_msix(ctrl_info);
  2579. break;
  2580. case IRQ_MODE_INTX:
  2581. break;
  2582. case IRQ_MODE_NONE:
  2583. pqi_configure_legacy_intx(ctrl_info, false);
  2584. break;
  2585. }
  2586. break;
  2587. case IRQ_MODE_NONE:
  2588. switch (new_mode) {
  2589. case IRQ_MODE_MSIX:
  2590. sis_enable_msix(ctrl_info);
  2591. break;
  2592. case IRQ_MODE_INTX:
  2593. pqi_configure_legacy_intx(ctrl_info, true);
  2594. sis_enable_intx(ctrl_info);
  2595. break;
  2596. case IRQ_MODE_NONE:
  2597. break;
  2598. }
  2599. break;
  2600. }
  2601. ctrl_info->irq_mode = new_mode;
  2602. }
  2603. #define PQI_LEGACY_INTX_PENDING 0x1
  2604. static inline bool pqi_is_valid_irq(struct pqi_ctrl_info *ctrl_info)
  2605. {
  2606. bool valid_irq;
  2607. u32 intx_status;
  2608. switch (ctrl_info->irq_mode) {
  2609. case IRQ_MODE_MSIX:
  2610. valid_irq = true;
  2611. break;
  2612. case IRQ_MODE_INTX:
  2613. intx_status =
  2614. readl(&ctrl_info->pqi_registers->legacy_intx_status);
  2615. if (intx_status & PQI_LEGACY_INTX_PENDING)
  2616. valid_irq = true;
  2617. else
  2618. valid_irq = false;
  2619. break;
  2620. case IRQ_MODE_NONE:
  2621. default:
  2622. valid_irq = false;
  2623. break;
  2624. }
  2625. return valid_irq;
  2626. }
  2627. static irqreturn_t pqi_irq_handler(int irq, void *data)
  2628. {
  2629. struct pqi_ctrl_info *ctrl_info;
  2630. struct pqi_queue_group *queue_group;
  2631. unsigned int num_responses_handled;
  2632. queue_group = data;
  2633. ctrl_info = queue_group->ctrl_info;
  2634. if (!pqi_is_valid_irq(ctrl_info))
  2635. return IRQ_NONE;
  2636. num_responses_handled = pqi_process_io_intr(ctrl_info, queue_group);
  2637. if (irq == ctrl_info->event_irq)
  2638. num_responses_handled += pqi_process_event_intr(ctrl_info);
  2639. if (num_responses_handled)
  2640. atomic_inc(&ctrl_info->num_interrupts);
  2641. pqi_start_io(ctrl_info, queue_group, RAID_PATH, NULL);
  2642. pqi_start_io(ctrl_info, queue_group, AIO_PATH, NULL);
  2643. return IRQ_HANDLED;
  2644. }
  2645. static int pqi_request_irqs(struct pqi_ctrl_info *ctrl_info)
  2646. {
  2647. struct pci_dev *pci_dev = ctrl_info->pci_dev;
  2648. int i;
  2649. int rc;
  2650. ctrl_info->event_irq = pci_irq_vector(pci_dev, 0);
  2651. for (i = 0; i < ctrl_info->num_msix_vectors_enabled; i++) {
  2652. rc = request_irq(pci_irq_vector(pci_dev, i), pqi_irq_handler, 0,
  2653. DRIVER_NAME_SHORT, &ctrl_info->queue_groups[i]);
  2654. if (rc) {
  2655. dev_err(&pci_dev->dev,
  2656. "irq %u init failed with error %d\n",
  2657. pci_irq_vector(pci_dev, i), rc);
  2658. return rc;
  2659. }
  2660. ctrl_info->num_msix_vectors_initialized++;
  2661. }
  2662. return 0;
  2663. }
  2664. static void pqi_free_irqs(struct pqi_ctrl_info *ctrl_info)
  2665. {
  2666. int i;
  2667. for (i = 0; i < ctrl_info->num_msix_vectors_initialized; i++)
  2668. free_irq(pci_irq_vector(ctrl_info->pci_dev, i),
  2669. &ctrl_info->queue_groups[i]);
  2670. ctrl_info->num_msix_vectors_initialized = 0;
  2671. }
  2672. static int pqi_enable_msix_interrupts(struct pqi_ctrl_info *ctrl_info)
  2673. {
  2674. int num_vectors_enabled;
  2675. num_vectors_enabled = pci_alloc_irq_vectors(ctrl_info->pci_dev,
  2676. PQI_MIN_MSIX_VECTORS, ctrl_info->num_queue_groups,
  2677. PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
  2678. if (num_vectors_enabled < 0) {
  2679. dev_err(&ctrl_info->pci_dev->dev,
  2680. "MSI-X init failed with error %d\n",
  2681. num_vectors_enabled);
  2682. return num_vectors_enabled;
  2683. }
  2684. ctrl_info->num_msix_vectors_enabled = num_vectors_enabled;
  2685. ctrl_info->irq_mode = IRQ_MODE_MSIX;
  2686. return 0;
  2687. }
  2688. static void pqi_disable_msix_interrupts(struct pqi_ctrl_info *ctrl_info)
  2689. {
  2690. if (ctrl_info->num_msix_vectors_enabled) {
  2691. pci_free_irq_vectors(ctrl_info->pci_dev);
  2692. ctrl_info->num_msix_vectors_enabled = 0;
  2693. }
  2694. }
  2695. static int pqi_alloc_operational_queues(struct pqi_ctrl_info *ctrl_info)
  2696. {
  2697. unsigned int i;
  2698. size_t alloc_length;
  2699. size_t element_array_length_per_iq;
  2700. size_t element_array_length_per_oq;
  2701. void *element_array;
  2702. void __iomem *next_queue_index;
  2703. void *aligned_pointer;
  2704. unsigned int num_inbound_queues;
  2705. unsigned int num_outbound_queues;
  2706. unsigned int num_queue_indexes;
  2707. struct pqi_queue_group *queue_group;
  2708. element_array_length_per_iq =
  2709. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH *
  2710. ctrl_info->num_elements_per_iq;
  2711. element_array_length_per_oq =
  2712. PQI_OPERATIONAL_OQ_ELEMENT_LENGTH *
  2713. ctrl_info->num_elements_per_oq;
  2714. num_inbound_queues = ctrl_info->num_queue_groups * 2;
  2715. num_outbound_queues = ctrl_info->num_queue_groups;
  2716. num_queue_indexes = (ctrl_info->num_queue_groups * 3) + 1;
  2717. aligned_pointer = NULL;
  2718. for (i = 0; i < num_inbound_queues; i++) {
  2719. aligned_pointer = PTR_ALIGN(aligned_pointer,
  2720. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  2721. aligned_pointer += element_array_length_per_iq;
  2722. }
  2723. for (i = 0; i < num_outbound_queues; i++) {
  2724. aligned_pointer = PTR_ALIGN(aligned_pointer,
  2725. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  2726. aligned_pointer += element_array_length_per_oq;
  2727. }
  2728. aligned_pointer = PTR_ALIGN(aligned_pointer,
  2729. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  2730. aligned_pointer += PQI_NUM_EVENT_QUEUE_ELEMENTS *
  2731. PQI_EVENT_OQ_ELEMENT_LENGTH;
  2732. for (i = 0; i < num_queue_indexes; i++) {
  2733. aligned_pointer = PTR_ALIGN(aligned_pointer,
  2734. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  2735. aligned_pointer += sizeof(pqi_index_t);
  2736. }
  2737. alloc_length = (size_t)aligned_pointer +
  2738. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT;
  2739. alloc_length += PQI_EXTRA_SGL_MEMORY;
  2740. ctrl_info->queue_memory_base =
  2741. dma_zalloc_coherent(&ctrl_info->pci_dev->dev,
  2742. alloc_length,
  2743. &ctrl_info->queue_memory_base_dma_handle, GFP_KERNEL);
  2744. if (!ctrl_info->queue_memory_base)
  2745. return -ENOMEM;
  2746. ctrl_info->queue_memory_length = alloc_length;
  2747. element_array = PTR_ALIGN(ctrl_info->queue_memory_base,
  2748. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  2749. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  2750. queue_group = &ctrl_info->queue_groups[i];
  2751. queue_group->iq_element_array[RAID_PATH] = element_array;
  2752. queue_group->iq_element_array_bus_addr[RAID_PATH] =
  2753. ctrl_info->queue_memory_base_dma_handle +
  2754. (element_array - ctrl_info->queue_memory_base);
  2755. element_array += element_array_length_per_iq;
  2756. element_array = PTR_ALIGN(element_array,
  2757. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  2758. queue_group->iq_element_array[AIO_PATH] = element_array;
  2759. queue_group->iq_element_array_bus_addr[AIO_PATH] =
  2760. ctrl_info->queue_memory_base_dma_handle +
  2761. (element_array - ctrl_info->queue_memory_base);
  2762. element_array += element_array_length_per_iq;
  2763. element_array = PTR_ALIGN(element_array,
  2764. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  2765. }
  2766. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  2767. queue_group = &ctrl_info->queue_groups[i];
  2768. queue_group->oq_element_array = element_array;
  2769. queue_group->oq_element_array_bus_addr =
  2770. ctrl_info->queue_memory_base_dma_handle +
  2771. (element_array - ctrl_info->queue_memory_base);
  2772. element_array += element_array_length_per_oq;
  2773. element_array = PTR_ALIGN(element_array,
  2774. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  2775. }
  2776. ctrl_info->event_queue.oq_element_array = element_array;
  2777. ctrl_info->event_queue.oq_element_array_bus_addr =
  2778. ctrl_info->queue_memory_base_dma_handle +
  2779. (element_array - ctrl_info->queue_memory_base);
  2780. element_array += PQI_NUM_EVENT_QUEUE_ELEMENTS *
  2781. PQI_EVENT_OQ_ELEMENT_LENGTH;
  2782. next_queue_index = (void __iomem *)PTR_ALIGN(element_array,
  2783. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  2784. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  2785. queue_group = &ctrl_info->queue_groups[i];
  2786. queue_group->iq_ci[RAID_PATH] = next_queue_index;
  2787. queue_group->iq_ci_bus_addr[RAID_PATH] =
  2788. ctrl_info->queue_memory_base_dma_handle +
  2789. (next_queue_index -
  2790. (void __iomem *)ctrl_info->queue_memory_base);
  2791. next_queue_index += sizeof(pqi_index_t);
  2792. next_queue_index = PTR_ALIGN(next_queue_index,
  2793. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  2794. queue_group->iq_ci[AIO_PATH] = next_queue_index;
  2795. queue_group->iq_ci_bus_addr[AIO_PATH] =
  2796. ctrl_info->queue_memory_base_dma_handle +
  2797. (next_queue_index -
  2798. (void __iomem *)ctrl_info->queue_memory_base);
  2799. next_queue_index += sizeof(pqi_index_t);
  2800. next_queue_index = PTR_ALIGN(next_queue_index,
  2801. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  2802. queue_group->oq_pi = next_queue_index;
  2803. queue_group->oq_pi_bus_addr =
  2804. ctrl_info->queue_memory_base_dma_handle +
  2805. (next_queue_index -
  2806. (void __iomem *)ctrl_info->queue_memory_base);
  2807. next_queue_index += sizeof(pqi_index_t);
  2808. next_queue_index = PTR_ALIGN(next_queue_index,
  2809. PQI_OPERATIONAL_INDEX_ALIGNMENT);
  2810. }
  2811. ctrl_info->event_queue.oq_pi = next_queue_index;
  2812. ctrl_info->event_queue.oq_pi_bus_addr =
  2813. ctrl_info->queue_memory_base_dma_handle +
  2814. (next_queue_index -
  2815. (void __iomem *)ctrl_info->queue_memory_base);
  2816. return 0;
  2817. }
  2818. static void pqi_init_operational_queues(struct pqi_ctrl_info *ctrl_info)
  2819. {
  2820. unsigned int i;
  2821. u16 next_iq_id = PQI_MIN_OPERATIONAL_QUEUE_ID;
  2822. u16 next_oq_id = PQI_MIN_OPERATIONAL_QUEUE_ID;
  2823. /*
  2824. * Initialize the backpointers to the controller structure in
  2825. * each operational queue group structure.
  2826. */
  2827. for (i = 0; i < ctrl_info->num_queue_groups; i++)
  2828. ctrl_info->queue_groups[i].ctrl_info = ctrl_info;
  2829. /*
  2830. * Assign IDs to all operational queues. Note that the IDs
  2831. * assigned to operational IQs are independent of the IDs
  2832. * assigned to operational OQs.
  2833. */
  2834. ctrl_info->event_queue.oq_id = next_oq_id++;
  2835. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  2836. ctrl_info->queue_groups[i].iq_id[RAID_PATH] = next_iq_id++;
  2837. ctrl_info->queue_groups[i].iq_id[AIO_PATH] = next_iq_id++;
  2838. ctrl_info->queue_groups[i].oq_id = next_oq_id++;
  2839. }
  2840. /*
  2841. * Assign MSI-X table entry indexes to all queues. Note that the
  2842. * interrupt for the event queue is shared with the first queue group.
  2843. */
  2844. ctrl_info->event_queue.int_msg_num = 0;
  2845. for (i = 0; i < ctrl_info->num_queue_groups; i++)
  2846. ctrl_info->queue_groups[i].int_msg_num = i;
  2847. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  2848. spin_lock_init(&ctrl_info->queue_groups[i].submit_lock[0]);
  2849. spin_lock_init(&ctrl_info->queue_groups[i].submit_lock[1]);
  2850. INIT_LIST_HEAD(&ctrl_info->queue_groups[i].request_list[0]);
  2851. INIT_LIST_HEAD(&ctrl_info->queue_groups[i].request_list[1]);
  2852. }
  2853. }
  2854. static int pqi_alloc_admin_queues(struct pqi_ctrl_info *ctrl_info)
  2855. {
  2856. size_t alloc_length;
  2857. struct pqi_admin_queues_aligned *admin_queues_aligned;
  2858. struct pqi_admin_queues *admin_queues;
  2859. alloc_length = sizeof(struct pqi_admin_queues_aligned) +
  2860. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT;
  2861. ctrl_info->admin_queue_memory_base =
  2862. dma_zalloc_coherent(&ctrl_info->pci_dev->dev,
  2863. alloc_length,
  2864. &ctrl_info->admin_queue_memory_base_dma_handle,
  2865. GFP_KERNEL);
  2866. if (!ctrl_info->admin_queue_memory_base)
  2867. return -ENOMEM;
  2868. ctrl_info->admin_queue_memory_length = alloc_length;
  2869. admin_queues = &ctrl_info->admin_queues;
  2870. admin_queues_aligned = PTR_ALIGN(ctrl_info->admin_queue_memory_base,
  2871. PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT);
  2872. admin_queues->iq_element_array =
  2873. &admin_queues_aligned->iq_element_array;
  2874. admin_queues->oq_element_array =
  2875. &admin_queues_aligned->oq_element_array;
  2876. admin_queues->iq_ci = &admin_queues_aligned->iq_ci;
  2877. admin_queues->oq_pi =
  2878. (pqi_index_t __iomem *)&admin_queues_aligned->oq_pi;
  2879. admin_queues->iq_element_array_bus_addr =
  2880. ctrl_info->admin_queue_memory_base_dma_handle +
  2881. (admin_queues->iq_element_array -
  2882. ctrl_info->admin_queue_memory_base);
  2883. admin_queues->oq_element_array_bus_addr =
  2884. ctrl_info->admin_queue_memory_base_dma_handle +
  2885. (admin_queues->oq_element_array -
  2886. ctrl_info->admin_queue_memory_base);
  2887. admin_queues->iq_ci_bus_addr =
  2888. ctrl_info->admin_queue_memory_base_dma_handle +
  2889. ((void *)admin_queues->iq_ci -
  2890. ctrl_info->admin_queue_memory_base);
  2891. admin_queues->oq_pi_bus_addr =
  2892. ctrl_info->admin_queue_memory_base_dma_handle +
  2893. ((void __iomem *)admin_queues->oq_pi -
  2894. (void __iomem *)ctrl_info->admin_queue_memory_base);
  2895. return 0;
  2896. }
  2897. #define PQI_ADMIN_QUEUE_CREATE_TIMEOUT_JIFFIES HZ
  2898. #define PQI_ADMIN_QUEUE_CREATE_POLL_INTERVAL_MSECS 1
  2899. static int pqi_create_admin_queues(struct pqi_ctrl_info *ctrl_info)
  2900. {
  2901. struct pqi_device_registers __iomem *pqi_registers;
  2902. struct pqi_admin_queues *admin_queues;
  2903. unsigned long timeout;
  2904. u8 status;
  2905. u32 reg;
  2906. pqi_registers = ctrl_info->pqi_registers;
  2907. admin_queues = &ctrl_info->admin_queues;
  2908. writeq((u64)admin_queues->iq_element_array_bus_addr,
  2909. &pqi_registers->admin_iq_element_array_addr);
  2910. writeq((u64)admin_queues->oq_element_array_bus_addr,
  2911. &pqi_registers->admin_oq_element_array_addr);
  2912. writeq((u64)admin_queues->iq_ci_bus_addr,
  2913. &pqi_registers->admin_iq_ci_addr);
  2914. writeq((u64)admin_queues->oq_pi_bus_addr,
  2915. &pqi_registers->admin_oq_pi_addr);
  2916. reg = PQI_ADMIN_IQ_NUM_ELEMENTS |
  2917. (PQI_ADMIN_OQ_NUM_ELEMENTS) << 8 |
  2918. (admin_queues->int_msg_num << 16);
  2919. writel(reg, &pqi_registers->admin_iq_num_elements);
  2920. writel(PQI_CREATE_ADMIN_QUEUE_PAIR,
  2921. &pqi_registers->function_and_status_code);
  2922. timeout = PQI_ADMIN_QUEUE_CREATE_TIMEOUT_JIFFIES + jiffies;
  2923. while (1) {
  2924. status = readb(&pqi_registers->function_and_status_code);
  2925. if (status == PQI_STATUS_IDLE)
  2926. break;
  2927. if (time_after(jiffies, timeout))
  2928. return -ETIMEDOUT;
  2929. msleep(PQI_ADMIN_QUEUE_CREATE_POLL_INTERVAL_MSECS);
  2930. }
  2931. /*
  2932. * The offset registers are not initialized to the correct
  2933. * offsets until *after* the create admin queue pair command
  2934. * completes successfully.
  2935. */
  2936. admin_queues->iq_pi = ctrl_info->iomem_base +
  2937. PQI_DEVICE_REGISTERS_OFFSET +
  2938. readq(&pqi_registers->admin_iq_pi_offset);
  2939. admin_queues->oq_ci = ctrl_info->iomem_base +
  2940. PQI_DEVICE_REGISTERS_OFFSET +
  2941. readq(&pqi_registers->admin_oq_ci_offset);
  2942. return 0;
  2943. }
  2944. static void pqi_submit_admin_request(struct pqi_ctrl_info *ctrl_info,
  2945. struct pqi_general_admin_request *request)
  2946. {
  2947. struct pqi_admin_queues *admin_queues;
  2948. void *next_element;
  2949. pqi_index_t iq_pi;
  2950. admin_queues = &ctrl_info->admin_queues;
  2951. iq_pi = admin_queues->iq_pi_copy;
  2952. next_element = admin_queues->iq_element_array +
  2953. (iq_pi * PQI_ADMIN_IQ_ELEMENT_LENGTH);
  2954. memcpy(next_element, request, sizeof(*request));
  2955. iq_pi = (iq_pi + 1) % PQI_ADMIN_IQ_NUM_ELEMENTS;
  2956. admin_queues->iq_pi_copy = iq_pi;
  2957. /*
  2958. * This write notifies the controller that an IU is available to be
  2959. * processed.
  2960. */
  2961. writel(iq_pi, admin_queues->iq_pi);
  2962. }
  2963. #define PQI_ADMIN_REQUEST_TIMEOUT_SECS 60
  2964. static int pqi_poll_for_admin_response(struct pqi_ctrl_info *ctrl_info,
  2965. struct pqi_general_admin_response *response)
  2966. {
  2967. struct pqi_admin_queues *admin_queues;
  2968. pqi_index_t oq_pi;
  2969. pqi_index_t oq_ci;
  2970. unsigned long timeout;
  2971. admin_queues = &ctrl_info->admin_queues;
  2972. oq_ci = admin_queues->oq_ci_copy;
  2973. timeout = (PQI_ADMIN_REQUEST_TIMEOUT_SECS * HZ) + jiffies;
  2974. while (1) {
  2975. oq_pi = readl(admin_queues->oq_pi);
  2976. if (oq_pi != oq_ci)
  2977. break;
  2978. if (time_after(jiffies, timeout)) {
  2979. dev_err(&ctrl_info->pci_dev->dev,
  2980. "timed out waiting for admin response\n");
  2981. return -ETIMEDOUT;
  2982. }
  2983. if (!sis_is_firmware_running(ctrl_info))
  2984. return -ENXIO;
  2985. usleep_range(1000, 2000);
  2986. }
  2987. memcpy(response, admin_queues->oq_element_array +
  2988. (oq_ci * PQI_ADMIN_OQ_ELEMENT_LENGTH), sizeof(*response));
  2989. oq_ci = (oq_ci + 1) % PQI_ADMIN_OQ_NUM_ELEMENTS;
  2990. admin_queues->oq_ci_copy = oq_ci;
  2991. writel(oq_ci, admin_queues->oq_ci);
  2992. return 0;
  2993. }
  2994. static void pqi_start_io(struct pqi_ctrl_info *ctrl_info,
  2995. struct pqi_queue_group *queue_group, enum pqi_io_path path,
  2996. struct pqi_io_request *io_request)
  2997. {
  2998. struct pqi_io_request *next;
  2999. void *next_element;
  3000. pqi_index_t iq_pi;
  3001. pqi_index_t iq_ci;
  3002. size_t iu_length;
  3003. unsigned long flags;
  3004. unsigned int num_elements_needed;
  3005. unsigned int num_elements_to_end_of_queue;
  3006. size_t copy_count;
  3007. struct pqi_iu_header *request;
  3008. spin_lock_irqsave(&queue_group->submit_lock[path], flags);
  3009. if (io_request) {
  3010. io_request->queue_group = queue_group;
  3011. list_add_tail(&io_request->request_list_entry,
  3012. &queue_group->request_list[path]);
  3013. }
  3014. iq_pi = queue_group->iq_pi_copy[path];
  3015. list_for_each_entry_safe(io_request, next,
  3016. &queue_group->request_list[path], request_list_entry) {
  3017. request = io_request->iu;
  3018. iu_length = get_unaligned_le16(&request->iu_length) +
  3019. PQI_REQUEST_HEADER_LENGTH;
  3020. num_elements_needed =
  3021. DIV_ROUND_UP(iu_length,
  3022. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3023. iq_ci = readl(queue_group->iq_ci[path]);
  3024. if (num_elements_needed > pqi_num_elements_free(iq_pi, iq_ci,
  3025. ctrl_info->num_elements_per_iq))
  3026. break;
  3027. put_unaligned_le16(queue_group->oq_id,
  3028. &request->response_queue_id);
  3029. next_element = queue_group->iq_element_array[path] +
  3030. (iq_pi * PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3031. num_elements_to_end_of_queue =
  3032. ctrl_info->num_elements_per_iq - iq_pi;
  3033. if (num_elements_needed <= num_elements_to_end_of_queue) {
  3034. memcpy(next_element, request, iu_length);
  3035. } else {
  3036. copy_count = num_elements_to_end_of_queue *
  3037. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH;
  3038. memcpy(next_element, request, copy_count);
  3039. memcpy(queue_group->iq_element_array[path],
  3040. (u8 *)request + copy_count,
  3041. iu_length - copy_count);
  3042. }
  3043. iq_pi = (iq_pi + num_elements_needed) %
  3044. ctrl_info->num_elements_per_iq;
  3045. list_del(&io_request->request_list_entry);
  3046. }
  3047. if (iq_pi != queue_group->iq_pi_copy[path]) {
  3048. queue_group->iq_pi_copy[path] = iq_pi;
  3049. /*
  3050. * This write notifies the controller that one or more IUs are
  3051. * available to be processed.
  3052. */
  3053. writel(iq_pi, queue_group->iq_pi[path]);
  3054. }
  3055. spin_unlock_irqrestore(&queue_group->submit_lock[path], flags);
  3056. }
  3057. #define PQI_WAIT_FOR_COMPLETION_IO_TIMEOUT_SECS 10
  3058. static int pqi_wait_for_completion_io(struct pqi_ctrl_info *ctrl_info,
  3059. struct completion *wait)
  3060. {
  3061. int rc;
  3062. while (1) {
  3063. if (wait_for_completion_io_timeout(wait,
  3064. PQI_WAIT_FOR_COMPLETION_IO_TIMEOUT_SECS * HZ)) {
  3065. rc = 0;
  3066. break;
  3067. }
  3068. pqi_check_ctrl_health(ctrl_info);
  3069. if (pqi_ctrl_offline(ctrl_info)) {
  3070. rc = -ENXIO;
  3071. break;
  3072. }
  3073. }
  3074. return rc;
  3075. }
  3076. static void pqi_raid_synchronous_complete(struct pqi_io_request *io_request,
  3077. void *context)
  3078. {
  3079. struct completion *waiting = context;
  3080. complete(waiting);
  3081. }
  3082. static int pqi_process_raid_io_error_synchronous(struct pqi_raid_error_info
  3083. *error_info)
  3084. {
  3085. int rc = -EIO;
  3086. switch (error_info->data_out_result) {
  3087. case PQI_DATA_IN_OUT_GOOD:
  3088. if (error_info->status == SAM_STAT_GOOD)
  3089. rc = 0;
  3090. break;
  3091. case PQI_DATA_IN_OUT_UNDERFLOW:
  3092. if (error_info->status == SAM_STAT_GOOD ||
  3093. error_info->status == SAM_STAT_CHECK_CONDITION)
  3094. rc = 0;
  3095. break;
  3096. case PQI_DATA_IN_OUT_ABORTED:
  3097. rc = PQI_CMD_STATUS_ABORTED;
  3098. break;
  3099. }
  3100. return rc;
  3101. }
  3102. static int pqi_submit_raid_request_synchronous(struct pqi_ctrl_info *ctrl_info,
  3103. struct pqi_iu_header *request, unsigned int flags,
  3104. struct pqi_raid_error_info *error_info, unsigned long timeout_msecs)
  3105. {
  3106. int rc = 0;
  3107. struct pqi_io_request *io_request;
  3108. unsigned long start_jiffies;
  3109. unsigned long msecs_blocked;
  3110. size_t iu_length;
  3111. DECLARE_COMPLETION_ONSTACK(wait);
  3112. /*
  3113. * Note that specifying PQI_SYNC_FLAGS_INTERRUPTABLE and a timeout value
  3114. * are mutually exclusive.
  3115. */
  3116. if (flags & PQI_SYNC_FLAGS_INTERRUPTABLE) {
  3117. if (down_interruptible(&ctrl_info->sync_request_sem))
  3118. return -ERESTARTSYS;
  3119. } else {
  3120. if (timeout_msecs == NO_TIMEOUT) {
  3121. down(&ctrl_info->sync_request_sem);
  3122. } else {
  3123. start_jiffies = jiffies;
  3124. if (down_timeout(&ctrl_info->sync_request_sem,
  3125. msecs_to_jiffies(timeout_msecs)))
  3126. return -ETIMEDOUT;
  3127. msecs_blocked =
  3128. jiffies_to_msecs(jiffies - start_jiffies);
  3129. if (msecs_blocked >= timeout_msecs) {
  3130. rc = -ETIMEDOUT;
  3131. goto out;
  3132. }
  3133. timeout_msecs -= msecs_blocked;
  3134. }
  3135. }
  3136. pqi_ctrl_busy(ctrl_info);
  3137. timeout_msecs = pqi_wait_if_ctrl_blocked(ctrl_info, timeout_msecs);
  3138. if (timeout_msecs == 0) {
  3139. pqi_ctrl_unbusy(ctrl_info);
  3140. rc = -ETIMEDOUT;
  3141. goto out;
  3142. }
  3143. if (pqi_ctrl_offline(ctrl_info)) {
  3144. pqi_ctrl_unbusy(ctrl_info);
  3145. rc = -ENXIO;
  3146. goto out;
  3147. }
  3148. io_request = pqi_alloc_io_request(ctrl_info);
  3149. put_unaligned_le16(io_request->index,
  3150. &(((struct pqi_raid_path_request *)request)->request_id));
  3151. if (request->iu_type == PQI_REQUEST_IU_RAID_PATH_IO)
  3152. ((struct pqi_raid_path_request *)request)->error_index =
  3153. ((struct pqi_raid_path_request *)request)->request_id;
  3154. iu_length = get_unaligned_le16(&request->iu_length) +
  3155. PQI_REQUEST_HEADER_LENGTH;
  3156. memcpy(io_request->iu, request, iu_length);
  3157. io_request->io_complete_callback = pqi_raid_synchronous_complete;
  3158. io_request->context = &wait;
  3159. pqi_start_io(ctrl_info,
  3160. &ctrl_info->queue_groups[PQI_DEFAULT_QUEUE_GROUP], RAID_PATH,
  3161. io_request);
  3162. pqi_ctrl_unbusy(ctrl_info);
  3163. if (timeout_msecs == NO_TIMEOUT) {
  3164. pqi_wait_for_completion_io(ctrl_info, &wait);
  3165. } else {
  3166. if (!wait_for_completion_io_timeout(&wait,
  3167. msecs_to_jiffies(timeout_msecs))) {
  3168. dev_warn(&ctrl_info->pci_dev->dev,
  3169. "command timed out\n");
  3170. rc = -ETIMEDOUT;
  3171. }
  3172. }
  3173. if (error_info) {
  3174. if (io_request->error_info)
  3175. memcpy(error_info, io_request->error_info,
  3176. sizeof(*error_info));
  3177. else
  3178. memset(error_info, 0, sizeof(*error_info));
  3179. } else if (rc == 0 && io_request->error_info) {
  3180. rc = pqi_process_raid_io_error_synchronous(
  3181. io_request->error_info);
  3182. }
  3183. pqi_free_io_request(io_request);
  3184. out:
  3185. up(&ctrl_info->sync_request_sem);
  3186. return rc;
  3187. }
  3188. static int pqi_validate_admin_response(
  3189. struct pqi_general_admin_response *response, u8 expected_function_code)
  3190. {
  3191. if (response->header.iu_type != PQI_RESPONSE_IU_GENERAL_ADMIN)
  3192. return -EINVAL;
  3193. if (get_unaligned_le16(&response->header.iu_length) !=
  3194. PQI_GENERAL_ADMIN_IU_LENGTH)
  3195. return -EINVAL;
  3196. if (response->function_code != expected_function_code)
  3197. return -EINVAL;
  3198. if (response->status != PQI_GENERAL_ADMIN_STATUS_SUCCESS)
  3199. return -EINVAL;
  3200. return 0;
  3201. }
  3202. static int pqi_submit_admin_request_synchronous(
  3203. struct pqi_ctrl_info *ctrl_info,
  3204. struct pqi_general_admin_request *request,
  3205. struct pqi_general_admin_response *response)
  3206. {
  3207. int rc;
  3208. pqi_submit_admin_request(ctrl_info, request);
  3209. rc = pqi_poll_for_admin_response(ctrl_info, response);
  3210. if (rc == 0)
  3211. rc = pqi_validate_admin_response(response,
  3212. request->function_code);
  3213. return rc;
  3214. }
  3215. static int pqi_report_device_capability(struct pqi_ctrl_info *ctrl_info)
  3216. {
  3217. int rc;
  3218. struct pqi_general_admin_request request;
  3219. struct pqi_general_admin_response response;
  3220. struct pqi_device_capability *capability;
  3221. struct pqi_iu_layer_descriptor *sop_iu_layer_descriptor;
  3222. capability = kmalloc(sizeof(*capability), GFP_KERNEL);
  3223. if (!capability)
  3224. return -ENOMEM;
  3225. memset(&request, 0, sizeof(request));
  3226. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  3227. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  3228. &request.header.iu_length);
  3229. request.function_code =
  3230. PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY;
  3231. put_unaligned_le32(sizeof(*capability),
  3232. &request.data.report_device_capability.buffer_length);
  3233. rc = pqi_map_single(ctrl_info->pci_dev,
  3234. &request.data.report_device_capability.sg_descriptor,
  3235. capability, sizeof(*capability),
  3236. PCI_DMA_FROMDEVICE);
  3237. if (rc)
  3238. goto out;
  3239. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  3240. &response);
  3241. pqi_pci_unmap(ctrl_info->pci_dev,
  3242. &request.data.report_device_capability.sg_descriptor, 1,
  3243. PCI_DMA_FROMDEVICE);
  3244. if (rc)
  3245. goto out;
  3246. if (response.status != PQI_GENERAL_ADMIN_STATUS_SUCCESS) {
  3247. rc = -EIO;
  3248. goto out;
  3249. }
  3250. ctrl_info->max_inbound_queues =
  3251. get_unaligned_le16(&capability->max_inbound_queues);
  3252. ctrl_info->max_elements_per_iq =
  3253. get_unaligned_le16(&capability->max_elements_per_iq);
  3254. ctrl_info->max_iq_element_length =
  3255. get_unaligned_le16(&capability->max_iq_element_length)
  3256. * 16;
  3257. ctrl_info->max_outbound_queues =
  3258. get_unaligned_le16(&capability->max_outbound_queues);
  3259. ctrl_info->max_elements_per_oq =
  3260. get_unaligned_le16(&capability->max_elements_per_oq);
  3261. ctrl_info->max_oq_element_length =
  3262. get_unaligned_le16(&capability->max_oq_element_length)
  3263. * 16;
  3264. sop_iu_layer_descriptor =
  3265. &capability->iu_layer_descriptors[PQI_PROTOCOL_SOP];
  3266. ctrl_info->max_inbound_iu_length_per_firmware =
  3267. get_unaligned_le16(
  3268. &sop_iu_layer_descriptor->max_inbound_iu_length);
  3269. ctrl_info->inbound_spanning_supported =
  3270. sop_iu_layer_descriptor->inbound_spanning_supported;
  3271. ctrl_info->outbound_spanning_supported =
  3272. sop_iu_layer_descriptor->outbound_spanning_supported;
  3273. out:
  3274. kfree(capability);
  3275. return rc;
  3276. }
  3277. static int pqi_validate_device_capability(struct pqi_ctrl_info *ctrl_info)
  3278. {
  3279. if (ctrl_info->max_iq_element_length <
  3280. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) {
  3281. dev_err(&ctrl_info->pci_dev->dev,
  3282. "max. inbound queue element length of %d is less than the required length of %d\n",
  3283. ctrl_info->max_iq_element_length,
  3284. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3285. return -EINVAL;
  3286. }
  3287. if (ctrl_info->max_oq_element_length <
  3288. PQI_OPERATIONAL_OQ_ELEMENT_LENGTH) {
  3289. dev_err(&ctrl_info->pci_dev->dev,
  3290. "max. outbound queue element length of %d is less than the required length of %d\n",
  3291. ctrl_info->max_oq_element_length,
  3292. PQI_OPERATIONAL_OQ_ELEMENT_LENGTH);
  3293. return -EINVAL;
  3294. }
  3295. if (ctrl_info->max_inbound_iu_length_per_firmware <
  3296. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) {
  3297. dev_err(&ctrl_info->pci_dev->dev,
  3298. "max. inbound IU length of %u is less than the min. required length of %d\n",
  3299. ctrl_info->max_inbound_iu_length_per_firmware,
  3300. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3301. return -EINVAL;
  3302. }
  3303. if (!ctrl_info->inbound_spanning_supported) {
  3304. dev_err(&ctrl_info->pci_dev->dev,
  3305. "the controller does not support inbound spanning\n");
  3306. return -EINVAL;
  3307. }
  3308. if (ctrl_info->outbound_spanning_supported) {
  3309. dev_err(&ctrl_info->pci_dev->dev,
  3310. "the controller supports outbound spanning but this driver does not\n");
  3311. return -EINVAL;
  3312. }
  3313. return 0;
  3314. }
  3315. static int pqi_create_event_queue(struct pqi_ctrl_info *ctrl_info)
  3316. {
  3317. int rc;
  3318. struct pqi_event_queue *event_queue;
  3319. struct pqi_general_admin_request request;
  3320. struct pqi_general_admin_response response;
  3321. event_queue = &ctrl_info->event_queue;
  3322. /*
  3323. * Create OQ (Outbound Queue - device to host queue) to dedicate
  3324. * to events.
  3325. */
  3326. memset(&request, 0, sizeof(request));
  3327. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  3328. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  3329. &request.header.iu_length);
  3330. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ;
  3331. put_unaligned_le16(event_queue->oq_id,
  3332. &request.data.create_operational_oq.queue_id);
  3333. put_unaligned_le64((u64)event_queue->oq_element_array_bus_addr,
  3334. &request.data.create_operational_oq.element_array_addr);
  3335. put_unaligned_le64((u64)event_queue->oq_pi_bus_addr,
  3336. &request.data.create_operational_oq.pi_addr);
  3337. put_unaligned_le16(PQI_NUM_EVENT_QUEUE_ELEMENTS,
  3338. &request.data.create_operational_oq.num_elements);
  3339. put_unaligned_le16(PQI_EVENT_OQ_ELEMENT_LENGTH / 16,
  3340. &request.data.create_operational_oq.element_length);
  3341. request.data.create_operational_oq.queue_protocol = PQI_PROTOCOL_SOP;
  3342. put_unaligned_le16(event_queue->int_msg_num,
  3343. &request.data.create_operational_oq.int_msg_num);
  3344. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  3345. &response);
  3346. if (rc)
  3347. return rc;
  3348. event_queue->oq_ci = ctrl_info->iomem_base +
  3349. PQI_DEVICE_REGISTERS_OFFSET +
  3350. get_unaligned_le64(
  3351. &response.data.create_operational_oq.oq_ci_offset);
  3352. return 0;
  3353. }
  3354. static int pqi_create_queue_group(struct pqi_ctrl_info *ctrl_info,
  3355. unsigned int group_number)
  3356. {
  3357. int rc;
  3358. struct pqi_queue_group *queue_group;
  3359. struct pqi_general_admin_request request;
  3360. struct pqi_general_admin_response response;
  3361. queue_group = &ctrl_info->queue_groups[group_number];
  3362. /*
  3363. * Create IQ (Inbound Queue - host to device queue) for
  3364. * RAID path.
  3365. */
  3366. memset(&request, 0, sizeof(request));
  3367. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  3368. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  3369. &request.header.iu_length);
  3370. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ;
  3371. put_unaligned_le16(queue_group->iq_id[RAID_PATH],
  3372. &request.data.create_operational_iq.queue_id);
  3373. put_unaligned_le64(
  3374. (u64)queue_group->iq_element_array_bus_addr[RAID_PATH],
  3375. &request.data.create_operational_iq.element_array_addr);
  3376. put_unaligned_le64((u64)queue_group->iq_ci_bus_addr[RAID_PATH],
  3377. &request.data.create_operational_iq.ci_addr);
  3378. put_unaligned_le16(ctrl_info->num_elements_per_iq,
  3379. &request.data.create_operational_iq.num_elements);
  3380. put_unaligned_le16(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH / 16,
  3381. &request.data.create_operational_iq.element_length);
  3382. request.data.create_operational_iq.queue_protocol = PQI_PROTOCOL_SOP;
  3383. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  3384. &response);
  3385. if (rc) {
  3386. dev_err(&ctrl_info->pci_dev->dev,
  3387. "error creating inbound RAID queue\n");
  3388. return rc;
  3389. }
  3390. queue_group->iq_pi[RAID_PATH] = ctrl_info->iomem_base +
  3391. PQI_DEVICE_REGISTERS_OFFSET +
  3392. get_unaligned_le64(
  3393. &response.data.create_operational_iq.iq_pi_offset);
  3394. /*
  3395. * Create IQ (Inbound Queue - host to device queue) for
  3396. * Advanced I/O (AIO) path.
  3397. */
  3398. memset(&request, 0, sizeof(request));
  3399. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  3400. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  3401. &request.header.iu_length);
  3402. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ;
  3403. put_unaligned_le16(queue_group->iq_id[AIO_PATH],
  3404. &request.data.create_operational_iq.queue_id);
  3405. put_unaligned_le64((u64)queue_group->
  3406. iq_element_array_bus_addr[AIO_PATH],
  3407. &request.data.create_operational_iq.element_array_addr);
  3408. put_unaligned_le64((u64)queue_group->iq_ci_bus_addr[AIO_PATH],
  3409. &request.data.create_operational_iq.ci_addr);
  3410. put_unaligned_le16(ctrl_info->num_elements_per_iq,
  3411. &request.data.create_operational_iq.num_elements);
  3412. put_unaligned_le16(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH / 16,
  3413. &request.data.create_operational_iq.element_length);
  3414. request.data.create_operational_iq.queue_protocol = PQI_PROTOCOL_SOP;
  3415. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  3416. &response);
  3417. if (rc) {
  3418. dev_err(&ctrl_info->pci_dev->dev,
  3419. "error creating inbound AIO queue\n");
  3420. return rc;
  3421. }
  3422. queue_group->iq_pi[AIO_PATH] = ctrl_info->iomem_base +
  3423. PQI_DEVICE_REGISTERS_OFFSET +
  3424. get_unaligned_le64(
  3425. &response.data.create_operational_iq.iq_pi_offset);
  3426. /*
  3427. * Designate the 2nd IQ as the AIO path. By default, all IQs are
  3428. * assumed to be for RAID path I/O unless we change the queue's
  3429. * property.
  3430. */
  3431. memset(&request, 0, sizeof(request));
  3432. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  3433. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  3434. &request.header.iu_length);
  3435. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY;
  3436. put_unaligned_le16(queue_group->iq_id[AIO_PATH],
  3437. &request.data.change_operational_iq_properties.queue_id);
  3438. put_unaligned_le32(PQI_IQ_PROPERTY_IS_AIO_QUEUE,
  3439. &request.data.change_operational_iq_properties.vendor_specific);
  3440. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  3441. &response);
  3442. if (rc) {
  3443. dev_err(&ctrl_info->pci_dev->dev,
  3444. "error changing queue property\n");
  3445. return rc;
  3446. }
  3447. /*
  3448. * Create OQ (Outbound Queue - device to host queue).
  3449. */
  3450. memset(&request, 0, sizeof(request));
  3451. request.header.iu_type = PQI_REQUEST_IU_GENERAL_ADMIN;
  3452. put_unaligned_le16(PQI_GENERAL_ADMIN_IU_LENGTH,
  3453. &request.header.iu_length);
  3454. request.function_code = PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ;
  3455. put_unaligned_le16(queue_group->oq_id,
  3456. &request.data.create_operational_oq.queue_id);
  3457. put_unaligned_le64((u64)queue_group->oq_element_array_bus_addr,
  3458. &request.data.create_operational_oq.element_array_addr);
  3459. put_unaligned_le64((u64)queue_group->oq_pi_bus_addr,
  3460. &request.data.create_operational_oq.pi_addr);
  3461. put_unaligned_le16(ctrl_info->num_elements_per_oq,
  3462. &request.data.create_operational_oq.num_elements);
  3463. put_unaligned_le16(PQI_OPERATIONAL_OQ_ELEMENT_LENGTH / 16,
  3464. &request.data.create_operational_oq.element_length);
  3465. request.data.create_operational_oq.queue_protocol = PQI_PROTOCOL_SOP;
  3466. put_unaligned_le16(queue_group->int_msg_num,
  3467. &request.data.create_operational_oq.int_msg_num);
  3468. rc = pqi_submit_admin_request_synchronous(ctrl_info, &request,
  3469. &response);
  3470. if (rc) {
  3471. dev_err(&ctrl_info->pci_dev->dev,
  3472. "error creating outbound queue\n");
  3473. return rc;
  3474. }
  3475. queue_group->oq_ci = ctrl_info->iomem_base +
  3476. PQI_DEVICE_REGISTERS_OFFSET +
  3477. get_unaligned_le64(
  3478. &response.data.create_operational_oq.oq_ci_offset);
  3479. return 0;
  3480. }
  3481. static int pqi_create_queues(struct pqi_ctrl_info *ctrl_info)
  3482. {
  3483. int rc;
  3484. unsigned int i;
  3485. rc = pqi_create_event_queue(ctrl_info);
  3486. if (rc) {
  3487. dev_err(&ctrl_info->pci_dev->dev,
  3488. "error creating event queue\n");
  3489. return rc;
  3490. }
  3491. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  3492. rc = pqi_create_queue_group(ctrl_info, i);
  3493. if (rc) {
  3494. dev_err(&ctrl_info->pci_dev->dev,
  3495. "error creating queue group number %u/%u\n",
  3496. i, ctrl_info->num_queue_groups);
  3497. return rc;
  3498. }
  3499. }
  3500. return 0;
  3501. }
  3502. #define PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH \
  3503. (offsetof(struct pqi_event_config, descriptors) + \
  3504. (PQI_MAX_EVENT_DESCRIPTORS * sizeof(struct pqi_event_descriptor)))
  3505. static int pqi_configure_events(struct pqi_ctrl_info *ctrl_info,
  3506. bool enable_events)
  3507. {
  3508. int rc;
  3509. unsigned int i;
  3510. struct pqi_event_config *event_config;
  3511. struct pqi_event_descriptor *event_descriptor;
  3512. struct pqi_general_management_request request;
  3513. event_config = kmalloc(PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  3514. GFP_KERNEL);
  3515. if (!event_config)
  3516. return -ENOMEM;
  3517. memset(&request, 0, sizeof(request));
  3518. request.header.iu_type = PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG;
  3519. put_unaligned_le16(offsetof(struct pqi_general_management_request,
  3520. data.report_event_configuration.sg_descriptors[1]) -
  3521. PQI_REQUEST_HEADER_LENGTH, &request.header.iu_length);
  3522. put_unaligned_le32(PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  3523. &request.data.report_event_configuration.buffer_length);
  3524. rc = pqi_map_single(ctrl_info->pci_dev,
  3525. request.data.report_event_configuration.sg_descriptors,
  3526. event_config, PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  3527. PCI_DMA_FROMDEVICE);
  3528. if (rc)
  3529. goto out;
  3530. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header,
  3531. 0, NULL, NO_TIMEOUT);
  3532. pqi_pci_unmap(ctrl_info->pci_dev,
  3533. request.data.report_event_configuration.sg_descriptors, 1,
  3534. PCI_DMA_FROMDEVICE);
  3535. if (rc)
  3536. goto out;
  3537. for (i = 0; i < event_config->num_event_descriptors; i++) {
  3538. event_descriptor = &event_config->descriptors[i];
  3539. if (enable_events &&
  3540. pqi_is_supported_event(event_descriptor->event_type))
  3541. put_unaligned_le16(ctrl_info->event_queue.oq_id,
  3542. &event_descriptor->oq_id);
  3543. else
  3544. put_unaligned_le16(0, &event_descriptor->oq_id);
  3545. }
  3546. memset(&request, 0, sizeof(request));
  3547. request.header.iu_type = PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG;
  3548. put_unaligned_le16(offsetof(struct pqi_general_management_request,
  3549. data.report_event_configuration.sg_descriptors[1]) -
  3550. PQI_REQUEST_HEADER_LENGTH, &request.header.iu_length);
  3551. put_unaligned_le32(PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  3552. &request.data.report_event_configuration.buffer_length);
  3553. rc = pqi_map_single(ctrl_info->pci_dev,
  3554. request.data.report_event_configuration.sg_descriptors,
  3555. event_config, PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH,
  3556. PCI_DMA_TODEVICE);
  3557. if (rc)
  3558. goto out;
  3559. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header, 0,
  3560. NULL, NO_TIMEOUT);
  3561. pqi_pci_unmap(ctrl_info->pci_dev,
  3562. request.data.report_event_configuration.sg_descriptors, 1,
  3563. PCI_DMA_TODEVICE);
  3564. out:
  3565. kfree(event_config);
  3566. return rc;
  3567. }
  3568. static inline int pqi_enable_events(struct pqi_ctrl_info *ctrl_info)
  3569. {
  3570. return pqi_configure_events(ctrl_info, true);
  3571. }
  3572. static inline int pqi_disable_events(struct pqi_ctrl_info *ctrl_info)
  3573. {
  3574. return pqi_configure_events(ctrl_info, false);
  3575. }
  3576. static void pqi_free_all_io_requests(struct pqi_ctrl_info *ctrl_info)
  3577. {
  3578. unsigned int i;
  3579. struct device *dev;
  3580. size_t sg_chain_buffer_length;
  3581. struct pqi_io_request *io_request;
  3582. if (!ctrl_info->io_request_pool)
  3583. return;
  3584. dev = &ctrl_info->pci_dev->dev;
  3585. sg_chain_buffer_length = ctrl_info->sg_chain_buffer_length;
  3586. io_request = ctrl_info->io_request_pool;
  3587. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  3588. kfree(io_request->iu);
  3589. if (!io_request->sg_chain_buffer)
  3590. break;
  3591. dma_free_coherent(dev, sg_chain_buffer_length,
  3592. io_request->sg_chain_buffer,
  3593. io_request->sg_chain_buffer_dma_handle);
  3594. io_request++;
  3595. }
  3596. kfree(ctrl_info->io_request_pool);
  3597. ctrl_info->io_request_pool = NULL;
  3598. }
  3599. static inline int pqi_alloc_error_buffer(struct pqi_ctrl_info *ctrl_info)
  3600. {
  3601. ctrl_info->error_buffer = dma_zalloc_coherent(&ctrl_info->pci_dev->dev,
  3602. ctrl_info->error_buffer_length,
  3603. &ctrl_info->error_buffer_dma_handle, GFP_KERNEL);
  3604. if (!ctrl_info->error_buffer)
  3605. return -ENOMEM;
  3606. return 0;
  3607. }
  3608. static int pqi_alloc_io_resources(struct pqi_ctrl_info *ctrl_info)
  3609. {
  3610. unsigned int i;
  3611. void *sg_chain_buffer;
  3612. size_t sg_chain_buffer_length;
  3613. dma_addr_t sg_chain_buffer_dma_handle;
  3614. struct device *dev;
  3615. struct pqi_io_request *io_request;
  3616. ctrl_info->io_request_pool =
  3617. kcalloc(ctrl_info->max_io_slots,
  3618. sizeof(ctrl_info->io_request_pool[0]), GFP_KERNEL);
  3619. if (!ctrl_info->io_request_pool) {
  3620. dev_err(&ctrl_info->pci_dev->dev,
  3621. "failed to allocate I/O request pool\n");
  3622. goto error;
  3623. }
  3624. dev = &ctrl_info->pci_dev->dev;
  3625. sg_chain_buffer_length = ctrl_info->sg_chain_buffer_length;
  3626. io_request = ctrl_info->io_request_pool;
  3627. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  3628. io_request->iu =
  3629. kmalloc(ctrl_info->max_inbound_iu_length, GFP_KERNEL);
  3630. if (!io_request->iu) {
  3631. dev_err(&ctrl_info->pci_dev->dev,
  3632. "failed to allocate IU buffers\n");
  3633. goto error;
  3634. }
  3635. sg_chain_buffer = dma_alloc_coherent(dev,
  3636. sg_chain_buffer_length, &sg_chain_buffer_dma_handle,
  3637. GFP_KERNEL);
  3638. if (!sg_chain_buffer) {
  3639. dev_err(&ctrl_info->pci_dev->dev,
  3640. "failed to allocate PQI scatter-gather chain buffers\n");
  3641. goto error;
  3642. }
  3643. io_request->index = i;
  3644. io_request->sg_chain_buffer = sg_chain_buffer;
  3645. io_request->sg_chain_buffer_dma_handle =
  3646. sg_chain_buffer_dma_handle;
  3647. io_request++;
  3648. }
  3649. return 0;
  3650. error:
  3651. pqi_free_all_io_requests(ctrl_info);
  3652. return -ENOMEM;
  3653. }
  3654. /*
  3655. * Calculate required resources that are sized based on max. outstanding
  3656. * requests and max. transfer size.
  3657. */
  3658. static void pqi_calculate_io_resources(struct pqi_ctrl_info *ctrl_info)
  3659. {
  3660. u32 max_transfer_size;
  3661. u32 max_sg_entries;
  3662. ctrl_info->scsi_ml_can_queue =
  3663. ctrl_info->max_outstanding_requests - PQI_RESERVED_IO_SLOTS;
  3664. ctrl_info->max_io_slots = ctrl_info->max_outstanding_requests;
  3665. ctrl_info->error_buffer_length =
  3666. ctrl_info->max_io_slots * PQI_ERROR_BUFFER_ELEMENT_LENGTH;
  3667. if (reset_devices)
  3668. max_transfer_size = min(ctrl_info->max_transfer_size,
  3669. PQI_MAX_TRANSFER_SIZE_KDUMP);
  3670. else
  3671. max_transfer_size = min(ctrl_info->max_transfer_size,
  3672. PQI_MAX_TRANSFER_SIZE);
  3673. max_sg_entries = max_transfer_size / PAGE_SIZE;
  3674. /* +1 to cover when the buffer is not page-aligned. */
  3675. max_sg_entries++;
  3676. max_sg_entries = min(ctrl_info->max_sg_entries, max_sg_entries);
  3677. max_transfer_size = (max_sg_entries - 1) * PAGE_SIZE;
  3678. ctrl_info->sg_chain_buffer_length =
  3679. (max_sg_entries * sizeof(struct pqi_sg_descriptor)) +
  3680. PQI_EXTRA_SGL_MEMORY;
  3681. ctrl_info->sg_tablesize = max_sg_entries;
  3682. ctrl_info->max_sectors = max_transfer_size / 512;
  3683. }
  3684. static void pqi_calculate_queue_resources(struct pqi_ctrl_info *ctrl_info)
  3685. {
  3686. int num_queue_groups;
  3687. u16 num_elements_per_iq;
  3688. u16 num_elements_per_oq;
  3689. if (reset_devices) {
  3690. num_queue_groups = 1;
  3691. } else {
  3692. int num_cpus;
  3693. int max_queue_groups;
  3694. max_queue_groups = min(ctrl_info->max_inbound_queues / 2,
  3695. ctrl_info->max_outbound_queues - 1);
  3696. max_queue_groups = min(max_queue_groups, PQI_MAX_QUEUE_GROUPS);
  3697. num_cpus = num_online_cpus();
  3698. num_queue_groups = min(num_cpus, ctrl_info->max_msix_vectors);
  3699. num_queue_groups = min(num_queue_groups, max_queue_groups);
  3700. }
  3701. ctrl_info->num_queue_groups = num_queue_groups;
  3702. ctrl_info->max_hw_queue_index = num_queue_groups - 1;
  3703. /*
  3704. * Make sure that the max. inbound IU length is an even multiple
  3705. * of our inbound element length.
  3706. */
  3707. ctrl_info->max_inbound_iu_length =
  3708. (ctrl_info->max_inbound_iu_length_per_firmware /
  3709. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) *
  3710. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH;
  3711. num_elements_per_iq =
  3712. (ctrl_info->max_inbound_iu_length /
  3713. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  3714. /* Add one because one element in each queue is unusable. */
  3715. num_elements_per_iq++;
  3716. num_elements_per_iq = min(num_elements_per_iq,
  3717. ctrl_info->max_elements_per_iq);
  3718. num_elements_per_oq = ((num_elements_per_iq - 1) * 2) + 1;
  3719. num_elements_per_oq = min(num_elements_per_oq,
  3720. ctrl_info->max_elements_per_oq);
  3721. ctrl_info->num_elements_per_iq = num_elements_per_iq;
  3722. ctrl_info->num_elements_per_oq = num_elements_per_oq;
  3723. ctrl_info->max_sg_per_iu =
  3724. ((ctrl_info->max_inbound_iu_length -
  3725. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH) /
  3726. sizeof(struct pqi_sg_descriptor)) +
  3727. PQI_MAX_EMBEDDED_SG_DESCRIPTORS;
  3728. }
  3729. static inline void pqi_set_sg_descriptor(
  3730. struct pqi_sg_descriptor *sg_descriptor, struct scatterlist *sg)
  3731. {
  3732. u64 address = (u64)sg_dma_address(sg);
  3733. unsigned int length = sg_dma_len(sg);
  3734. put_unaligned_le64(address, &sg_descriptor->address);
  3735. put_unaligned_le32(length, &sg_descriptor->length);
  3736. put_unaligned_le32(0, &sg_descriptor->flags);
  3737. }
  3738. static int pqi_build_raid_sg_list(struct pqi_ctrl_info *ctrl_info,
  3739. struct pqi_raid_path_request *request, struct scsi_cmnd *scmd,
  3740. struct pqi_io_request *io_request)
  3741. {
  3742. int i;
  3743. u16 iu_length;
  3744. int sg_count;
  3745. bool chained;
  3746. unsigned int num_sg_in_iu;
  3747. unsigned int max_sg_per_iu;
  3748. struct scatterlist *sg;
  3749. struct pqi_sg_descriptor *sg_descriptor;
  3750. sg_count = scsi_dma_map(scmd);
  3751. if (sg_count < 0)
  3752. return sg_count;
  3753. iu_length = offsetof(struct pqi_raid_path_request, sg_descriptors) -
  3754. PQI_REQUEST_HEADER_LENGTH;
  3755. if (sg_count == 0)
  3756. goto out;
  3757. sg = scsi_sglist(scmd);
  3758. sg_descriptor = request->sg_descriptors;
  3759. max_sg_per_iu = ctrl_info->max_sg_per_iu - 1;
  3760. chained = false;
  3761. num_sg_in_iu = 0;
  3762. i = 0;
  3763. while (1) {
  3764. pqi_set_sg_descriptor(sg_descriptor, sg);
  3765. if (!chained)
  3766. num_sg_in_iu++;
  3767. i++;
  3768. if (i == sg_count)
  3769. break;
  3770. sg_descriptor++;
  3771. if (i == max_sg_per_iu) {
  3772. put_unaligned_le64(
  3773. (u64)io_request->sg_chain_buffer_dma_handle,
  3774. &sg_descriptor->address);
  3775. put_unaligned_le32((sg_count - num_sg_in_iu)
  3776. * sizeof(*sg_descriptor),
  3777. &sg_descriptor->length);
  3778. put_unaligned_le32(CISS_SG_CHAIN,
  3779. &sg_descriptor->flags);
  3780. chained = true;
  3781. num_sg_in_iu++;
  3782. sg_descriptor = io_request->sg_chain_buffer;
  3783. }
  3784. sg = sg_next(sg);
  3785. }
  3786. put_unaligned_le32(CISS_SG_LAST, &sg_descriptor->flags);
  3787. request->partial = chained;
  3788. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  3789. out:
  3790. put_unaligned_le16(iu_length, &request->header.iu_length);
  3791. return 0;
  3792. }
  3793. static int pqi_build_aio_sg_list(struct pqi_ctrl_info *ctrl_info,
  3794. struct pqi_aio_path_request *request, struct scsi_cmnd *scmd,
  3795. struct pqi_io_request *io_request)
  3796. {
  3797. int i;
  3798. u16 iu_length;
  3799. int sg_count;
  3800. bool chained;
  3801. unsigned int num_sg_in_iu;
  3802. unsigned int max_sg_per_iu;
  3803. struct scatterlist *sg;
  3804. struct pqi_sg_descriptor *sg_descriptor;
  3805. sg_count = scsi_dma_map(scmd);
  3806. if (sg_count < 0)
  3807. return sg_count;
  3808. iu_length = offsetof(struct pqi_aio_path_request, sg_descriptors) -
  3809. PQI_REQUEST_HEADER_LENGTH;
  3810. num_sg_in_iu = 0;
  3811. if (sg_count == 0)
  3812. goto out;
  3813. sg = scsi_sglist(scmd);
  3814. sg_descriptor = request->sg_descriptors;
  3815. max_sg_per_iu = ctrl_info->max_sg_per_iu - 1;
  3816. chained = false;
  3817. i = 0;
  3818. while (1) {
  3819. pqi_set_sg_descriptor(sg_descriptor, sg);
  3820. if (!chained)
  3821. num_sg_in_iu++;
  3822. i++;
  3823. if (i == sg_count)
  3824. break;
  3825. sg_descriptor++;
  3826. if (i == max_sg_per_iu) {
  3827. put_unaligned_le64(
  3828. (u64)io_request->sg_chain_buffer_dma_handle,
  3829. &sg_descriptor->address);
  3830. put_unaligned_le32((sg_count - num_sg_in_iu)
  3831. * sizeof(*sg_descriptor),
  3832. &sg_descriptor->length);
  3833. put_unaligned_le32(CISS_SG_CHAIN,
  3834. &sg_descriptor->flags);
  3835. chained = true;
  3836. num_sg_in_iu++;
  3837. sg_descriptor = io_request->sg_chain_buffer;
  3838. }
  3839. sg = sg_next(sg);
  3840. }
  3841. put_unaligned_le32(CISS_SG_LAST, &sg_descriptor->flags);
  3842. request->partial = chained;
  3843. iu_length += num_sg_in_iu * sizeof(*sg_descriptor);
  3844. out:
  3845. put_unaligned_le16(iu_length, &request->header.iu_length);
  3846. request->num_sg_descriptors = num_sg_in_iu;
  3847. return 0;
  3848. }
  3849. static void pqi_raid_io_complete(struct pqi_io_request *io_request,
  3850. void *context)
  3851. {
  3852. struct scsi_cmnd *scmd;
  3853. scmd = io_request->scmd;
  3854. pqi_free_io_request(io_request);
  3855. scsi_dma_unmap(scmd);
  3856. pqi_scsi_done(scmd);
  3857. }
  3858. static int pqi_raid_submit_scsi_cmd_with_io_request(
  3859. struct pqi_ctrl_info *ctrl_info, struct pqi_io_request *io_request,
  3860. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  3861. struct pqi_queue_group *queue_group)
  3862. {
  3863. int rc;
  3864. size_t cdb_length;
  3865. struct pqi_raid_path_request *request;
  3866. io_request->io_complete_callback = pqi_raid_io_complete;
  3867. io_request->scmd = scmd;
  3868. request = io_request->iu;
  3869. memset(request, 0,
  3870. offsetof(struct pqi_raid_path_request, sg_descriptors));
  3871. request->header.iu_type = PQI_REQUEST_IU_RAID_PATH_IO;
  3872. put_unaligned_le32(scsi_bufflen(scmd), &request->buffer_length);
  3873. request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  3874. put_unaligned_le16(io_request->index, &request->request_id);
  3875. request->error_index = request->request_id;
  3876. memcpy(request->lun_number, device->scsi3addr,
  3877. sizeof(request->lun_number));
  3878. cdb_length = min_t(size_t, scmd->cmd_len, sizeof(request->cdb));
  3879. memcpy(request->cdb, scmd->cmnd, cdb_length);
  3880. switch (cdb_length) {
  3881. case 6:
  3882. case 10:
  3883. case 12:
  3884. case 16:
  3885. /* No bytes in the Additional CDB bytes field */
  3886. request->additional_cdb_bytes_usage =
  3887. SOP_ADDITIONAL_CDB_BYTES_0;
  3888. break;
  3889. case 20:
  3890. /* 4 bytes in the Additional cdb field */
  3891. request->additional_cdb_bytes_usage =
  3892. SOP_ADDITIONAL_CDB_BYTES_4;
  3893. break;
  3894. case 24:
  3895. /* 8 bytes in the Additional cdb field */
  3896. request->additional_cdb_bytes_usage =
  3897. SOP_ADDITIONAL_CDB_BYTES_8;
  3898. break;
  3899. case 28:
  3900. /* 12 bytes in the Additional cdb field */
  3901. request->additional_cdb_bytes_usage =
  3902. SOP_ADDITIONAL_CDB_BYTES_12;
  3903. break;
  3904. case 32:
  3905. default:
  3906. /* 16 bytes in the Additional cdb field */
  3907. request->additional_cdb_bytes_usage =
  3908. SOP_ADDITIONAL_CDB_BYTES_16;
  3909. break;
  3910. }
  3911. switch (scmd->sc_data_direction) {
  3912. case DMA_TO_DEVICE:
  3913. request->data_direction = SOP_READ_FLAG;
  3914. break;
  3915. case DMA_FROM_DEVICE:
  3916. request->data_direction = SOP_WRITE_FLAG;
  3917. break;
  3918. case DMA_NONE:
  3919. request->data_direction = SOP_NO_DIRECTION_FLAG;
  3920. break;
  3921. case DMA_BIDIRECTIONAL:
  3922. request->data_direction = SOP_BIDIRECTIONAL;
  3923. break;
  3924. default:
  3925. dev_err(&ctrl_info->pci_dev->dev,
  3926. "unknown data direction: %d\n",
  3927. scmd->sc_data_direction);
  3928. break;
  3929. }
  3930. rc = pqi_build_raid_sg_list(ctrl_info, request, scmd, io_request);
  3931. if (rc) {
  3932. pqi_free_io_request(io_request);
  3933. return SCSI_MLQUEUE_HOST_BUSY;
  3934. }
  3935. pqi_start_io(ctrl_info, queue_group, RAID_PATH, io_request);
  3936. return 0;
  3937. }
  3938. static inline int pqi_raid_submit_scsi_cmd(struct pqi_ctrl_info *ctrl_info,
  3939. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  3940. struct pqi_queue_group *queue_group)
  3941. {
  3942. struct pqi_io_request *io_request;
  3943. io_request = pqi_alloc_io_request(ctrl_info);
  3944. return pqi_raid_submit_scsi_cmd_with_io_request(ctrl_info, io_request,
  3945. device, scmd, queue_group);
  3946. }
  3947. static inline void pqi_schedule_bypass_retry(struct pqi_ctrl_info *ctrl_info)
  3948. {
  3949. if (!pqi_ctrl_blocked(ctrl_info))
  3950. schedule_work(&ctrl_info->raid_bypass_retry_work);
  3951. }
  3952. static bool pqi_raid_bypass_retry_needed(struct pqi_io_request *io_request)
  3953. {
  3954. struct scsi_cmnd *scmd;
  3955. struct pqi_scsi_dev *device;
  3956. struct pqi_ctrl_info *ctrl_info;
  3957. if (!io_request->raid_bypass)
  3958. return false;
  3959. scmd = io_request->scmd;
  3960. if ((scmd->result & 0xff) == SAM_STAT_GOOD)
  3961. return false;
  3962. if (host_byte(scmd->result) == DID_NO_CONNECT)
  3963. return false;
  3964. device = scmd->device->hostdata;
  3965. if (pqi_device_offline(device))
  3966. return false;
  3967. ctrl_info = shost_to_hba(scmd->device->host);
  3968. if (pqi_ctrl_offline(ctrl_info))
  3969. return false;
  3970. return true;
  3971. }
  3972. static inline void pqi_add_to_raid_bypass_retry_list(
  3973. struct pqi_ctrl_info *ctrl_info,
  3974. struct pqi_io_request *io_request, bool at_head)
  3975. {
  3976. unsigned long flags;
  3977. spin_lock_irqsave(&ctrl_info->raid_bypass_retry_list_lock, flags);
  3978. if (at_head)
  3979. list_add(&io_request->request_list_entry,
  3980. &ctrl_info->raid_bypass_retry_list);
  3981. else
  3982. list_add_tail(&io_request->request_list_entry,
  3983. &ctrl_info->raid_bypass_retry_list);
  3984. spin_unlock_irqrestore(&ctrl_info->raid_bypass_retry_list_lock, flags);
  3985. }
  3986. static void pqi_queued_raid_bypass_complete(struct pqi_io_request *io_request,
  3987. void *context)
  3988. {
  3989. struct scsi_cmnd *scmd;
  3990. scmd = io_request->scmd;
  3991. pqi_free_io_request(io_request);
  3992. pqi_scsi_done(scmd);
  3993. }
  3994. static void pqi_queue_raid_bypass_retry(struct pqi_io_request *io_request)
  3995. {
  3996. struct scsi_cmnd *scmd;
  3997. struct pqi_ctrl_info *ctrl_info;
  3998. io_request->io_complete_callback = pqi_queued_raid_bypass_complete;
  3999. scmd = io_request->scmd;
  4000. scmd->result = 0;
  4001. ctrl_info = shost_to_hba(scmd->device->host);
  4002. pqi_add_to_raid_bypass_retry_list(ctrl_info, io_request, false);
  4003. pqi_schedule_bypass_retry(ctrl_info);
  4004. }
  4005. static int pqi_retry_raid_bypass(struct pqi_io_request *io_request)
  4006. {
  4007. struct scsi_cmnd *scmd;
  4008. struct pqi_scsi_dev *device;
  4009. struct pqi_ctrl_info *ctrl_info;
  4010. struct pqi_queue_group *queue_group;
  4011. scmd = io_request->scmd;
  4012. device = scmd->device->hostdata;
  4013. if (pqi_device_in_reset(device)) {
  4014. pqi_free_io_request(io_request);
  4015. set_host_byte(scmd, DID_RESET);
  4016. pqi_scsi_done(scmd);
  4017. return 0;
  4018. }
  4019. ctrl_info = shost_to_hba(scmd->device->host);
  4020. queue_group = io_request->queue_group;
  4021. pqi_reinit_io_request(io_request);
  4022. return pqi_raid_submit_scsi_cmd_with_io_request(ctrl_info, io_request,
  4023. device, scmd, queue_group);
  4024. }
  4025. static inline struct pqi_io_request *pqi_next_queued_raid_bypass_request(
  4026. struct pqi_ctrl_info *ctrl_info)
  4027. {
  4028. unsigned long flags;
  4029. struct pqi_io_request *io_request;
  4030. spin_lock_irqsave(&ctrl_info->raid_bypass_retry_list_lock, flags);
  4031. io_request = list_first_entry_or_null(
  4032. &ctrl_info->raid_bypass_retry_list,
  4033. struct pqi_io_request, request_list_entry);
  4034. if (io_request)
  4035. list_del(&io_request->request_list_entry);
  4036. spin_unlock_irqrestore(&ctrl_info->raid_bypass_retry_list_lock, flags);
  4037. return io_request;
  4038. }
  4039. static void pqi_retry_raid_bypass_requests(struct pqi_ctrl_info *ctrl_info)
  4040. {
  4041. int rc;
  4042. struct pqi_io_request *io_request;
  4043. pqi_ctrl_busy(ctrl_info);
  4044. while (1) {
  4045. if (pqi_ctrl_blocked(ctrl_info))
  4046. break;
  4047. io_request = pqi_next_queued_raid_bypass_request(ctrl_info);
  4048. if (!io_request)
  4049. break;
  4050. rc = pqi_retry_raid_bypass(io_request);
  4051. if (rc) {
  4052. pqi_add_to_raid_bypass_retry_list(ctrl_info, io_request,
  4053. true);
  4054. pqi_schedule_bypass_retry(ctrl_info);
  4055. break;
  4056. }
  4057. }
  4058. pqi_ctrl_unbusy(ctrl_info);
  4059. }
  4060. static void pqi_raid_bypass_retry_worker(struct work_struct *work)
  4061. {
  4062. struct pqi_ctrl_info *ctrl_info;
  4063. ctrl_info = container_of(work, struct pqi_ctrl_info,
  4064. raid_bypass_retry_work);
  4065. pqi_retry_raid_bypass_requests(ctrl_info);
  4066. }
  4067. static void pqi_clear_all_queued_raid_bypass_retries(
  4068. struct pqi_ctrl_info *ctrl_info)
  4069. {
  4070. unsigned long flags;
  4071. spin_lock_irqsave(&ctrl_info->raid_bypass_retry_list_lock, flags);
  4072. INIT_LIST_HEAD(&ctrl_info->raid_bypass_retry_list);
  4073. spin_unlock_irqrestore(&ctrl_info->raid_bypass_retry_list_lock, flags);
  4074. }
  4075. static void pqi_aio_io_complete(struct pqi_io_request *io_request,
  4076. void *context)
  4077. {
  4078. struct scsi_cmnd *scmd;
  4079. scmd = io_request->scmd;
  4080. scsi_dma_unmap(scmd);
  4081. if (io_request->status == -EAGAIN)
  4082. set_host_byte(scmd, DID_IMM_RETRY);
  4083. else if (pqi_raid_bypass_retry_needed(io_request)) {
  4084. pqi_queue_raid_bypass_retry(io_request);
  4085. return;
  4086. }
  4087. pqi_free_io_request(io_request);
  4088. pqi_scsi_done(scmd);
  4089. }
  4090. static inline int pqi_aio_submit_scsi_cmd(struct pqi_ctrl_info *ctrl_info,
  4091. struct pqi_scsi_dev *device, struct scsi_cmnd *scmd,
  4092. struct pqi_queue_group *queue_group)
  4093. {
  4094. return pqi_aio_submit_io(ctrl_info, scmd, device->aio_handle,
  4095. scmd->cmnd, scmd->cmd_len, queue_group, NULL, false);
  4096. }
  4097. static int pqi_aio_submit_io(struct pqi_ctrl_info *ctrl_info,
  4098. struct scsi_cmnd *scmd, u32 aio_handle, u8 *cdb,
  4099. unsigned int cdb_length, struct pqi_queue_group *queue_group,
  4100. struct pqi_encryption_info *encryption_info, bool raid_bypass)
  4101. {
  4102. int rc;
  4103. struct pqi_io_request *io_request;
  4104. struct pqi_aio_path_request *request;
  4105. io_request = pqi_alloc_io_request(ctrl_info);
  4106. io_request->io_complete_callback = pqi_aio_io_complete;
  4107. io_request->scmd = scmd;
  4108. io_request->raid_bypass = raid_bypass;
  4109. request = io_request->iu;
  4110. memset(request, 0,
  4111. offsetof(struct pqi_raid_path_request, sg_descriptors));
  4112. request->header.iu_type = PQI_REQUEST_IU_AIO_PATH_IO;
  4113. put_unaligned_le32(aio_handle, &request->nexus_id);
  4114. put_unaligned_le32(scsi_bufflen(scmd), &request->buffer_length);
  4115. request->task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4116. put_unaligned_le16(io_request->index, &request->request_id);
  4117. request->error_index = request->request_id;
  4118. if (cdb_length > sizeof(request->cdb))
  4119. cdb_length = sizeof(request->cdb);
  4120. request->cdb_length = cdb_length;
  4121. memcpy(request->cdb, cdb, cdb_length);
  4122. switch (scmd->sc_data_direction) {
  4123. case DMA_TO_DEVICE:
  4124. request->data_direction = SOP_READ_FLAG;
  4125. break;
  4126. case DMA_FROM_DEVICE:
  4127. request->data_direction = SOP_WRITE_FLAG;
  4128. break;
  4129. case DMA_NONE:
  4130. request->data_direction = SOP_NO_DIRECTION_FLAG;
  4131. break;
  4132. case DMA_BIDIRECTIONAL:
  4133. request->data_direction = SOP_BIDIRECTIONAL;
  4134. break;
  4135. default:
  4136. dev_err(&ctrl_info->pci_dev->dev,
  4137. "unknown data direction: %d\n",
  4138. scmd->sc_data_direction);
  4139. break;
  4140. }
  4141. if (encryption_info) {
  4142. request->encryption_enable = true;
  4143. put_unaligned_le16(encryption_info->data_encryption_key_index,
  4144. &request->data_encryption_key_index);
  4145. put_unaligned_le32(encryption_info->encrypt_tweak_lower,
  4146. &request->encrypt_tweak_lower);
  4147. put_unaligned_le32(encryption_info->encrypt_tweak_upper,
  4148. &request->encrypt_tweak_upper);
  4149. }
  4150. rc = pqi_build_aio_sg_list(ctrl_info, request, scmd, io_request);
  4151. if (rc) {
  4152. pqi_free_io_request(io_request);
  4153. return SCSI_MLQUEUE_HOST_BUSY;
  4154. }
  4155. pqi_start_io(ctrl_info, queue_group, AIO_PATH, io_request);
  4156. return 0;
  4157. }
  4158. static inline u16 pqi_get_hw_queue(struct pqi_ctrl_info *ctrl_info,
  4159. struct scsi_cmnd *scmd)
  4160. {
  4161. u16 hw_queue;
  4162. hw_queue = blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(scmd->request));
  4163. if (hw_queue > ctrl_info->max_hw_queue_index)
  4164. hw_queue = 0;
  4165. return hw_queue;
  4166. }
  4167. /*
  4168. * This function gets called just before we hand the completed SCSI request
  4169. * back to the SML.
  4170. */
  4171. void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd)
  4172. {
  4173. struct pqi_scsi_dev *device;
  4174. device = scmd->device->hostdata;
  4175. atomic_dec(&device->scsi_cmds_outstanding);
  4176. }
  4177. static int pqi_scsi_queue_command(struct Scsi_Host *shost,
  4178. struct scsi_cmnd *scmd)
  4179. {
  4180. int rc;
  4181. struct pqi_ctrl_info *ctrl_info;
  4182. struct pqi_scsi_dev *device;
  4183. u16 hw_queue;
  4184. struct pqi_queue_group *queue_group;
  4185. bool raid_bypassed;
  4186. device = scmd->device->hostdata;
  4187. ctrl_info = shost_to_hba(shost);
  4188. atomic_inc(&device->scsi_cmds_outstanding);
  4189. if (pqi_ctrl_offline(ctrl_info)) {
  4190. set_host_byte(scmd, DID_NO_CONNECT);
  4191. pqi_scsi_done(scmd);
  4192. return 0;
  4193. }
  4194. pqi_ctrl_busy(ctrl_info);
  4195. if (pqi_ctrl_blocked(ctrl_info) || pqi_device_in_reset(device)) {
  4196. rc = SCSI_MLQUEUE_HOST_BUSY;
  4197. goto out;
  4198. }
  4199. /*
  4200. * This is necessary because the SML doesn't zero out this field during
  4201. * error recovery.
  4202. */
  4203. scmd->result = 0;
  4204. hw_queue = pqi_get_hw_queue(ctrl_info, scmd);
  4205. queue_group = &ctrl_info->queue_groups[hw_queue];
  4206. if (pqi_is_logical_device(device)) {
  4207. raid_bypassed = false;
  4208. if (device->raid_bypass_enabled &&
  4209. !blk_rq_is_passthrough(scmd->request)) {
  4210. rc = pqi_raid_bypass_submit_scsi_cmd(ctrl_info, device,
  4211. scmd, queue_group);
  4212. if (rc == 0 || rc == SCSI_MLQUEUE_HOST_BUSY)
  4213. raid_bypassed = true;
  4214. }
  4215. if (!raid_bypassed)
  4216. rc = pqi_raid_submit_scsi_cmd(ctrl_info, device, scmd,
  4217. queue_group);
  4218. } else {
  4219. if (device->aio_enabled)
  4220. rc = pqi_aio_submit_scsi_cmd(ctrl_info, device, scmd,
  4221. queue_group);
  4222. else
  4223. rc = pqi_raid_submit_scsi_cmd(ctrl_info, device, scmd,
  4224. queue_group);
  4225. }
  4226. out:
  4227. pqi_ctrl_unbusy(ctrl_info);
  4228. if (rc)
  4229. atomic_dec(&device->scsi_cmds_outstanding);
  4230. return rc;
  4231. }
  4232. static int pqi_wait_until_queued_io_drained(struct pqi_ctrl_info *ctrl_info,
  4233. struct pqi_queue_group *queue_group)
  4234. {
  4235. unsigned int path;
  4236. unsigned long flags;
  4237. bool list_is_empty;
  4238. for (path = 0; path < 2; path++) {
  4239. while (1) {
  4240. spin_lock_irqsave(
  4241. &queue_group->submit_lock[path], flags);
  4242. list_is_empty =
  4243. list_empty(&queue_group->request_list[path]);
  4244. spin_unlock_irqrestore(
  4245. &queue_group->submit_lock[path], flags);
  4246. if (list_is_empty)
  4247. break;
  4248. pqi_check_ctrl_health(ctrl_info);
  4249. if (pqi_ctrl_offline(ctrl_info))
  4250. return -ENXIO;
  4251. usleep_range(1000, 2000);
  4252. }
  4253. }
  4254. return 0;
  4255. }
  4256. static int pqi_wait_until_inbound_queues_empty(struct pqi_ctrl_info *ctrl_info)
  4257. {
  4258. int rc;
  4259. unsigned int i;
  4260. unsigned int path;
  4261. struct pqi_queue_group *queue_group;
  4262. pqi_index_t iq_pi;
  4263. pqi_index_t iq_ci;
  4264. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  4265. queue_group = &ctrl_info->queue_groups[i];
  4266. rc = pqi_wait_until_queued_io_drained(ctrl_info, queue_group);
  4267. if (rc)
  4268. return rc;
  4269. for (path = 0; path < 2; path++) {
  4270. iq_pi = queue_group->iq_pi_copy[path];
  4271. while (1) {
  4272. iq_ci = readl(queue_group->iq_ci[path]);
  4273. if (iq_ci == iq_pi)
  4274. break;
  4275. pqi_check_ctrl_health(ctrl_info);
  4276. if (pqi_ctrl_offline(ctrl_info))
  4277. return -ENXIO;
  4278. usleep_range(1000, 2000);
  4279. }
  4280. }
  4281. }
  4282. return 0;
  4283. }
  4284. static void pqi_fail_io_queued_for_device(struct pqi_ctrl_info *ctrl_info,
  4285. struct pqi_scsi_dev *device)
  4286. {
  4287. unsigned int i;
  4288. unsigned int path;
  4289. struct pqi_queue_group *queue_group;
  4290. unsigned long flags;
  4291. struct pqi_io_request *io_request;
  4292. struct pqi_io_request *next;
  4293. struct scsi_cmnd *scmd;
  4294. struct pqi_scsi_dev *scsi_device;
  4295. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  4296. queue_group = &ctrl_info->queue_groups[i];
  4297. for (path = 0; path < 2; path++) {
  4298. spin_lock_irqsave(
  4299. &queue_group->submit_lock[path], flags);
  4300. list_for_each_entry_safe(io_request, next,
  4301. &queue_group->request_list[path],
  4302. request_list_entry) {
  4303. scmd = io_request->scmd;
  4304. if (!scmd)
  4305. continue;
  4306. scsi_device = scmd->device->hostdata;
  4307. if (scsi_device != device)
  4308. continue;
  4309. list_del(&io_request->request_list_entry);
  4310. set_host_byte(scmd, DID_RESET);
  4311. pqi_scsi_done(scmd);
  4312. }
  4313. spin_unlock_irqrestore(
  4314. &queue_group->submit_lock[path], flags);
  4315. }
  4316. }
  4317. }
  4318. static int pqi_device_wait_for_pending_io(struct pqi_ctrl_info *ctrl_info,
  4319. struct pqi_scsi_dev *device)
  4320. {
  4321. while (atomic_read(&device->scsi_cmds_outstanding)) {
  4322. pqi_check_ctrl_health(ctrl_info);
  4323. if (pqi_ctrl_offline(ctrl_info))
  4324. return -ENXIO;
  4325. usleep_range(1000, 2000);
  4326. }
  4327. return 0;
  4328. }
  4329. static int pqi_ctrl_wait_for_pending_io(struct pqi_ctrl_info *ctrl_info)
  4330. {
  4331. bool io_pending;
  4332. unsigned long flags;
  4333. struct pqi_scsi_dev *device;
  4334. while (1) {
  4335. io_pending = false;
  4336. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  4337. list_for_each_entry(device, &ctrl_info->scsi_device_list,
  4338. scsi_device_list_entry) {
  4339. if (atomic_read(&device->scsi_cmds_outstanding)) {
  4340. io_pending = true;
  4341. break;
  4342. }
  4343. }
  4344. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock,
  4345. flags);
  4346. if (!io_pending)
  4347. break;
  4348. pqi_check_ctrl_health(ctrl_info);
  4349. if (pqi_ctrl_offline(ctrl_info))
  4350. return -ENXIO;
  4351. usleep_range(1000, 2000);
  4352. }
  4353. return 0;
  4354. }
  4355. static void pqi_lun_reset_complete(struct pqi_io_request *io_request,
  4356. void *context)
  4357. {
  4358. struct completion *waiting = context;
  4359. complete(waiting);
  4360. }
  4361. #define PQI_LUN_RESET_TIMEOUT_SECS 10
  4362. static int pqi_wait_for_lun_reset_completion(struct pqi_ctrl_info *ctrl_info,
  4363. struct pqi_scsi_dev *device, struct completion *wait)
  4364. {
  4365. int rc;
  4366. while (1) {
  4367. if (wait_for_completion_io_timeout(wait,
  4368. PQI_LUN_RESET_TIMEOUT_SECS * HZ)) {
  4369. rc = 0;
  4370. break;
  4371. }
  4372. pqi_check_ctrl_health(ctrl_info);
  4373. if (pqi_ctrl_offline(ctrl_info)) {
  4374. rc = -ENXIO;
  4375. break;
  4376. }
  4377. }
  4378. return rc;
  4379. }
  4380. static int pqi_lun_reset(struct pqi_ctrl_info *ctrl_info,
  4381. struct pqi_scsi_dev *device)
  4382. {
  4383. int rc;
  4384. struct pqi_io_request *io_request;
  4385. DECLARE_COMPLETION_ONSTACK(wait);
  4386. struct pqi_task_management_request *request;
  4387. io_request = pqi_alloc_io_request(ctrl_info);
  4388. io_request->io_complete_callback = pqi_lun_reset_complete;
  4389. io_request->context = &wait;
  4390. request = io_request->iu;
  4391. memset(request, 0, sizeof(*request));
  4392. request->header.iu_type = PQI_REQUEST_IU_TASK_MANAGEMENT;
  4393. put_unaligned_le16(sizeof(*request) - PQI_REQUEST_HEADER_LENGTH,
  4394. &request->header.iu_length);
  4395. put_unaligned_le16(io_request->index, &request->request_id);
  4396. memcpy(request->lun_number, device->scsi3addr,
  4397. sizeof(request->lun_number));
  4398. request->task_management_function = SOP_TASK_MANAGEMENT_LUN_RESET;
  4399. pqi_start_io(ctrl_info,
  4400. &ctrl_info->queue_groups[PQI_DEFAULT_QUEUE_GROUP], RAID_PATH,
  4401. io_request);
  4402. rc = pqi_wait_for_lun_reset_completion(ctrl_info, device, &wait);
  4403. if (rc == 0)
  4404. rc = io_request->status;
  4405. pqi_free_io_request(io_request);
  4406. return rc;
  4407. }
  4408. /* Performs a reset at the LUN level. */
  4409. static int pqi_device_reset(struct pqi_ctrl_info *ctrl_info,
  4410. struct pqi_scsi_dev *device)
  4411. {
  4412. int rc;
  4413. rc = pqi_lun_reset(ctrl_info, device);
  4414. if (rc == 0)
  4415. rc = pqi_device_wait_for_pending_io(ctrl_info, device);
  4416. return rc == 0 ? SUCCESS : FAILED;
  4417. }
  4418. static int pqi_eh_device_reset_handler(struct scsi_cmnd *scmd)
  4419. {
  4420. int rc;
  4421. struct Scsi_Host *shost;
  4422. struct pqi_ctrl_info *ctrl_info;
  4423. struct pqi_scsi_dev *device;
  4424. shost = scmd->device->host;
  4425. ctrl_info = shost_to_hba(shost);
  4426. device = scmd->device->hostdata;
  4427. dev_err(&ctrl_info->pci_dev->dev,
  4428. "resetting scsi %d:%d:%d:%d\n",
  4429. shost->host_no, device->bus, device->target, device->lun);
  4430. pqi_check_ctrl_health(ctrl_info);
  4431. if (pqi_ctrl_offline(ctrl_info)) {
  4432. rc = FAILED;
  4433. goto out;
  4434. }
  4435. mutex_lock(&ctrl_info->lun_reset_mutex);
  4436. pqi_ctrl_block_requests(ctrl_info);
  4437. pqi_ctrl_wait_until_quiesced(ctrl_info);
  4438. pqi_fail_io_queued_for_device(ctrl_info, device);
  4439. rc = pqi_wait_until_inbound_queues_empty(ctrl_info);
  4440. pqi_device_reset_start(device);
  4441. pqi_ctrl_unblock_requests(ctrl_info);
  4442. if (rc)
  4443. rc = FAILED;
  4444. else
  4445. rc = pqi_device_reset(ctrl_info, device);
  4446. pqi_device_reset_done(device);
  4447. mutex_unlock(&ctrl_info->lun_reset_mutex);
  4448. out:
  4449. dev_err(&ctrl_info->pci_dev->dev,
  4450. "reset of scsi %d:%d:%d:%d: %s\n",
  4451. shost->host_no, device->bus, device->target, device->lun,
  4452. rc == SUCCESS ? "SUCCESS" : "FAILED");
  4453. return rc;
  4454. }
  4455. static int pqi_slave_alloc(struct scsi_device *sdev)
  4456. {
  4457. struct pqi_scsi_dev *device;
  4458. unsigned long flags;
  4459. struct pqi_ctrl_info *ctrl_info;
  4460. struct scsi_target *starget;
  4461. struct sas_rphy *rphy;
  4462. ctrl_info = shost_to_hba(sdev->host);
  4463. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  4464. if (sdev_channel(sdev) == PQI_PHYSICAL_DEVICE_BUS) {
  4465. starget = scsi_target(sdev);
  4466. rphy = target_to_rphy(starget);
  4467. device = pqi_find_device_by_sas_rphy(ctrl_info, rphy);
  4468. if (device) {
  4469. device->target = sdev_id(sdev);
  4470. device->lun = sdev->lun;
  4471. device->target_lun_valid = true;
  4472. }
  4473. } else {
  4474. device = pqi_find_scsi_dev(ctrl_info, sdev_channel(sdev),
  4475. sdev_id(sdev), sdev->lun);
  4476. }
  4477. if (device) {
  4478. sdev->hostdata = device;
  4479. device->sdev = sdev;
  4480. if (device->queue_depth) {
  4481. device->advertised_queue_depth = device->queue_depth;
  4482. scsi_change_queue_depth(sdev,
  4483. device->advertised_queue_depth);
  4484. }
  4485. }
  4486. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  4487. return 0;
  4488. }
  4489. static int pqi_map_queues(struct Scsi_Host *shost)
  4490. {
  4491. struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
  4492. return blk_mq_pci_map_queues(&shost->tag_set, ctrl_info->pci_dev, 0);
  4493. }
  4494. static int pqi_getpciinfo_ioctl(struct pqi_ctrl_info *ctrl_info,
  4495. void __user *arg)
  4496. {
  4497. struct pci_dev *pci_dev;
  4498. u32 subsystem_vendor;
  4499. u32 subsystem_device;
  4500. cciss_pci_info_struct pciinfo;
  4501. if (!arg)
  4502. return -EINVAL;
  4503. pci_dev = ctrl_info->pci_dev;
  4504. pciinfo.domain = pci_domain_nr(pci_dev->bus);
  4505. pciinfo.bus = pci_dev->bus->number;
  4506. pciinfo.dev_fn = pci_dev->devfn;
  4507. subsystem_vendor = pci_dev->subsystem_vendor;
  4508. subsystem_device = pci_dev->subsystem_device;
  4509. pciinfo.board_id = ((subsystem_device << 16) & 0xffff0000) |
  4510. subsystem_vendor;
  4511. if (copy_to_user(arg, &pciinfo, sizeof(pciinfo)))
  4512. return -EFAULT;
  4513. return 0;
  4514. }
  4515. static int pqi_getdrivver_ioctl(void __user *arg)
  4516. {
  4517. u32 version;
  4518. if (!arg)
  4519. return -EINVAL;
  4520. version = (DRIVER_MAJOR << 28) | (DRIVER_MINOR << 24) |
  4521. (DRIVER_RELEASE << 16) | DRIVER_REVISION;
  4522. if (copy_to_user(arg, &version, sizeof(version)))
  4523. return -EFAULT;
  4524. return 0;
  4525. }
  4526. struct ciss_error_info {
  4527. u8 scsi_status;
  4528. int command_status;
  4529. size_t sense_data_length;
  4530. };
  4531. static void pqi_error_info_to_ciss(struct pqi_raid_error_info *pqi_error_info,
  4532. struct ciss_error_info *ciss_error_info)
  4533. {
  4534. int ciss_cmd_status;
  4535. size_t sense_data_length;
  4536. switch (pqi_error_info->data_out_result) {
  4537. case PQI_DATA_IN_OUT_GOOD:
  4538. ciss_cmd_status = CISS_CMD_STATUS_SUCCESS;
  4539. break;
  4540. case PQI_DATA_IN_OUT_UNDERFLOW:
  4541. ciss_cmd_status = CISS_CMD_STATUS_DATA_UNDERRUN;
  4542. break;
  4543. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW:
  4544. ciss_cmd_status = CISS_CMD_STATUS_DATA_OVERRUN;
  4545. break;
  4546. case PQI_DATA_IN_OUT_PROTOCOL_ERROR:
  4547. case PQI_DATA_IN_OUT_BUFFER_ERROR:
  4548. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA:
  4549. case PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE:
  4550. case PQI_DATA_IN_OUT_ERROR:
  4551. ciss_cmd_status = CISS_CMD_STATUS_PROTOCOL_ERROR;
  4552. break;
  4553. case PQI_DATA_IN_OUT_HARDWARE_ERROR:
  4554. case PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR:
  4555. case PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT:
  4556. case PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED:
  4557. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED:
  4558. case PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED:
  4559. case PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST:
  4560. case PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION:
  4561. case PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED:
  4562. case PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ:
  4563. ciss_cmd_status = CISS_CMD_STATUS_HARDWARE_ERROR;
  4564. break;
  4565. case PQI_DATA_IN_OUT_UNSOLICITED_ABORT:
  4566. ciss_cmd_status = CISS_CMD_STATUS_UNSOLICITED_ABORT;
  4567. break;
  4568. case PQI_DATA_IN_OUT_ABORTED:
  4569. ciss_cmd_status = CISS_CMD_STATUS_ABORTED;
  4570. break;
  4571. case PQI_DATA_IN_OUT_TIMEOUT:
  4572. ciss_cmd_status = CISS_CMD_STATUS_TIMEOUT;
  4573. break;
  4574. default:
  4575. ciss_cmd_status = CISS_CMD_STATUS_TARGET_STATUS;
  4576. break;
  4577. }
  4578. sense_data_length =
  4579. get_unaligned_le16(&pqi_error_info->sense_data_length);
  4580. if (sense_data_length == 0)
  4581. sense_data_length =
  4582. get_unaligned_le16(&pqi_error_info->response_data_length);
  4583. if (sense_data_length)
  4584. if (sense_data_length > sizeof(pqi_error_info->data))
  4585. sense_data_length = sizeof(pqi_error_info->data);
  4586. ciss_error_info->scsi_status = pqi_error_info->status;
  4587. ciss_error_info->command_status = ciss_cmd_status;
  4588. ciss_error_info->sense_data_length = sense_data_length;
  4589. }
  4590. static int pqi_passthru_ioctl(struct pqi_ctrl_info *ctrl_info, void __user *arg)
  4591. {
  4592. int rc;
  4593. char *kernel_buffer = NULL;
  4594. u16 iu_length;
  4595. size_t sense_data_length;
  4596. IOCTL_Command_struct iocommand;
  4597. struct pqi_raid_path_request request;
  4598. struct pqi_raid_error_info pqi_error_info;
  4599. struct ciss_error_info ciss_error_info;
  4600. if (pqi_ctrl_offline(ctrl_info))
  4601. return -ENXIO;
  4602. if (!arg)
  4603. return -EINVAL;
  4604. if (!capable(CAP_SYS_RAWIO))
  4605. return -EPERM;
  4606. if (copy_from_user(&iocommand, arg, sizeof(iocommand)))
  4607. return -EFAULT;
  4608. if (iocommand.buf_size < 1 &&
  4609. iocommand.Request.Type.Direction != XFER_NONE)
  4610. return -EINVAL;
  4611. if (iocommand.Request.CDBLen > sizeof(request.cdb))
  4612. return -EINVAL;
  4613. if (iocommand.Request.Type.Type != TYPE_CMD)
  4614. return -EINVAL;
  4615. switch (iocommand.Request.Type.Direction) {
  4616. case XFER_NONE:
  4617. case XFER_WRITE:
  4618. case XFER_READ:
  4619. case XFER_READ | XFER_WRITE:
  4620. break;
  4621. default:
  4622. return -EINVAL;
  4623. }
  4624. if (iocommand.buf_size > 0) {
  4625. kernel_buffer = kmalloc(iocommand.buf_size, GFP_KERNEL);
  4626. if (!kernel_buffer)
  4627. return -ENOMEM;
  4628. if (iocommand.Request.Type.Direction & XFER_WRITE) {
  4629. if (copy_from_user(kernel_buffer, iocommand.buf,
  4630. iocommand.buf_size)) {
  4631. rc = -EFAULT;
  4632. goto out;
  4633. }
  4634. } else {
  4635. memset(kernel_buffer, 0, iocommand.buf_size);
  4636. }
  4637. }
  4638. memset(&request, 0, sizeof(request));
  4639. request.header.iu_type = PQI_REQUEST_IU_RAID_PATH_IO;
  4640. iu_length = offsetof(struct pqi_raid_path_request, sg_descriptors) -
  4641. PQI_REQUEST_HEADER_LENGTH;
  4642. memcpy(request.lun_number, iocommand.LUN_info.LunAddrBytes,
  4643. sizeof(request.lun_number));
  4644. memcpy(request.cdb, iocommand.Request.CDB, iocommand.Request.CDBLen);
  4645. request.additional_cdb_bytes_usage = SOP_ADDITIONAL_CDB_BYTES_0;
  4646. switch (iocommand.Request.Type.Direction) {
  4647. case XFER_NONE:
  4648. request.data_direction = SOP_NO_DIRECTION_FLAG;
  4649. break;
  4650. case XFER_WRITE:
  4651. request.data_direction = SOP_WRITE_FLAG;
  4652. break;
  4653. case XFER_READ:
  4654. request.data_direction = SOP_READ_FLAG;
  4655. break;
  4656. case XFER_READ | XFER_WRITE:
  4657. request.data_direction = SOP_BIDIRECTIONAL;
  4658. break;
  4659. }
  4660. request.task_attribute = SOP_TASK_ATTRIBUTE_SIMPLE;
  4661. if (iocommand.buf_size > 0) {
  4662. put_unaligned_le32(iocommand.buf_size, &request.buffer_length);
  4663. rc = pqi_map_single(ctrl_info->pci_dev,
  4664. &request.sg_descriptors[0], kernel_buffer,
  4665. iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
  4666. if (rc)
  4667. goto out;
  4668. iu_length += sizeof(request.sg_descriptors[0]);
  4669. }
  4670. put_unaligned_le16(iu_length, &request.header.iu_length);
  4671. rc = pqi_submit_raid_request_synchronous(ctrl_info, &request.header,
  4672. PQI_SYNC_FLAGS_INTERRUPTABLE, &pqi_error_info, NO_TIMEOUT);
  4673. if (iocommand.buf_size > 0)
  4674. pqi_pci_unmap(ctrl_info->pci_dev, request.sg_descriptors, 1,
  4675. PCI_DMA_BIDIRECTIONAL);
  4676. memset(&iocommand.error_info, 0, sizeof(iocommand.error_info));
  4677. if (rc == 0) {
  4678. pqi_error_info_to_ciss(&pqi_error_info, &ciss_error_info);
  4679. iocommand.error_info.ScsiStatus = ciss_error_info.scsi_status;
  4680. iocommand.error_info.CommandStatus =
  4681. ciss_error_info.command_status;
  4682. sense_data_length = ciss_error_info.sense_data_length;
  4683. if (sense_data_length) {
  4684. if (sense_data_length >
  4685. sizeof(iocommand.error_info.SenseInfo))
  4686. sense_data_length =
  4687. sizeof(iocommand.error_info.SenseInfo);
  4688. memcpy(iocommand.error_info.SenseInfo,
  4689. pqi_error_info.data, sense_data_length);
  4690. iocommand.error_info.SenseLen = sense_data_length;
  4691. }
  4692. }
  4693. if (copy_to_user(arg, &iocommand, sizeof(iocommand))) {
  4694. rc = -EFAULT;
  4695. goto out;
  4696. }
  4697. if (rc == 0 && iocommand.buf_size > 0 &&
  4698. (iocommand.Request.Type.Direction & XFER_READ)) {
  4699. if (copy_to_user(iocommand.buf, kernel_buffer,
  4700. iocommand.buf_size)) {
  4701. rc = -EFAULT;
  4702. }
  4703. }
  4704. out:
  4705. kfree(kernel_buffer);
  4706. return rc;
  4707. }
  4708. static int pqi_ioctl(struct scsi_device *sdev, int cmd, void __user *arg)
  4709. {
  4710. int rc;
  4711. struct pqi_ctrl_info *ctrl_info;
  4712. ctrl_info = shost_to_hba(sdev->host);
  4713. switch (cmd) {
  4714. case CCISS_DEREGDISK:
  4715. case CCISS_REGNEWDISK:
  4716. case CCISS_REGNEWD:
  4717. rc = pqi_scan_scsi_devices(ctrl_info);
  4718. break;
  4719. case CCISS_GETPCIINFO:
  4720. rc = pqi_getpciinfo_ioctl(ctrl_info, arg);
  4721. break;
  4722. case CCISS_GETDRIVVER:
  4723. rc = pqi_getdrivver_ioctl(arg);
  4724. break;
  4725. case CCISS_PASSTHRU:
  4726. rc = pqi_passthru_ioctl(ctrl_info, arg);
  4727. break;
  4728. default:
  4729. rc = -EINVAL;
  4730. break;
  4731. }
  4732. return rc;
  4733. }
  4734. static ssize_t pqi_version_show(struct device *dev,
  4735. struct device_attribute *attr, char *buffer)
  4736. {
  4737. ssize_t count = 0;
  4738. struct Scsi_Host *shost;
  4739. struct pqi_ctrl_info *ctrl_info;
  4740. shost = class_to_shost(dev);
  4741. ctrl_info = shost_to_hba(shost);
  4742. count += snprintf(buffer + count, PAGE_SIZE - count,
  4743. " driver: %s\n", DRIVER_VERSION BUILD_TIMESTAMP);
  4744. count += snprintf(buffer + count, PAGE_SIZE - count,
  4745. "firmware: %s\n", ctrl_info->firmware_version);
  4746. return count;
  4747. }
  4748. static ssize_t pqi_host_rescan_store(struct device *dev,
  4749. struct device_attribute *attr, const char *buffer, size_t count)
  4750. {
  4751. struct Scsi_Host *shost = class_to_shost(dev);
  4752. pqi_scan_start(shost);
  4753. return count;
  4754. }
  4755. static ssize_t pqi_lockup_action_show(struct device *dev,
  4756. struct device_attribute *attr, char *buffer)
  4757. {
  4758. int count = 0;
  4759. unsigned int i;
  4760. for (i = 0; i < ARRAY_SIZE(pqi_lockup_actions); i++) {
  4761. if (pqi_lockup_actions[i].action == pqi_lockup_action)
  4762. count += snprintf(buffer + count, PAGE_SIZE - count,
  4763. "[%s] ", pqi_lockup_actions[i].name);
  4764. else
  4765. count += snprintf(buffer + count, PAGE_SIZE - count,
  4766. "%s ", pqi_lockup_actions[i].name);
  4767. }
  4768. count += snprintf(buffer + count, PAGE_SIZE - count, "\n");
  4769. return count;
  4770. }
  4771. static ssize_t pqi_lockup_action_store(struct device *dev,
  4772. struct device_attribute *attr, const char *buffer, size_t count)
  4773. {
  4774. unsigned int i;
  4775. char *action_name;
  4776. char action_name_buffer[32];
  4777. strlcpy(action_name_buffer, buffer, sizeof(action_name_buffer));
  4778. action_name = strstrip(action_name_buffer);
  4779. for (i = 0; i < ARRAY_SIZE(pqi_lockup_actions); i++) {
  4780. if (strcmp(action_name, pqi_lockup_actions[i].name) == 0) {
  4781. pqi_lockup_action = pqi_lockup_actions[i].action;
  4782. return count;
  4783. }
  4784. }
  4785. return -EINVAL;
  4786. }
  4787. static DEVICE_ATTR(version, 0444, pqi_version_show, NULL);
  4788. static DEVICE_ATTR(rescan, 0200, NULL, pqi_host_rescan_store);
  4789. static DEVICE_ATTR(lockup_action, 0644,
  4790. pqi_lockup_action_show, pqi_lockup_action_store);
  4791. static struct device_attribute *pqi_shost_attrs[] = {
  4792. &dev_attr_version,
  4793. &dev_attr_rescan,
  4794. &dev_attr_lockup_action,
  4795. NULL
  4796. };
  4797. static ssize_t pqi_sas_address_show(struct device *dev,
  4798. struct device_attribute *attr, char *buffer)
  4799. {
  4800. struct pqi_ctrl_info *ctrl_info;
  4801. struct scsi_device *sdev;
  4802. struct pqi_scsi_dev *device;
  4803. unsigned long flags;
  4804. u64 sas_address;
  4805. sdev = to_scsi_device(dev);
  4806. ctrl_info = shost_to_hba(sdev->host);
  4807. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  4808. device = sdev->hostdata;
  4809. if (pqi_is_logical_device(device)) {
  4810. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock,
  4811. flags);
  4812. return -ENODEV;
  4813. }
  4814. sas_address = device->sas_address;
  4815. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  4816. return snprintf(buffer, PAGE_SIZE, "0x%016llx\n", sas_address);
  4817. }
  4818. static ssize_t pqi_ssd_smart_path_enabled_show(struct device *dev,
  4819. struct device_attribute *attr, char *buffer)
  4820. {
  4821. struct pqi_ctrl_info *ctrl_info;
  4822. struct scsi_device *sdev;
  4823. struct pqi_scsi_dev *device;
  4824. unsigned long flags;
  4825. sdev = to_scsi_device(dev);
  4826. ctrl_info = shost_to_hba(sdev->host);
  4827. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  4828. device = sdev->hostdata;
  4829. buffer[0] = device->raid_bypass_enabled ? '1' : '0';
  4830. buffer[1] = '\n';
  4831. buffer[2] = '\0';
  4832. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  4833. return 2;
  4834. }
  4835. static ssize_t pqi_raid_level_show(struct device *dev,
  4836. struct device_attribute *attr, char *buffer)
  4837. {
  4838. struct pqi_ctrl_info *ctrl_info;
  4839. struct scsi_device *sdev;
  4840. struct pqi_scsi_dev *device;
  4841. unsigned long flags;
  4842. char *raid_level;
  4843. sdev = to_scsi_device(dev);
  4844. ctrl_info = shost_to_hba(sdev->host);
  4845. spin_lock_irqsave(&ctrl_info->scsi_device_list_lock, flags);
  4846. device = sdev->hostdata;
  4847. if (pqi_is_logical_device(device))
  4848. raid_level = pqi_raid_level_to_string(device->raid_level);
  4849. else
  4850. raid_level = "N/A";
  4851. spin_unlock_irqrestore(&ctrl_info->scsi_device_list_lock, flags);
  4852. return snprintf(buffer, PAGE_SIZE, "%s\n", raid_level);
  4853. }
  4854. static DEVICE_ATTR(sas_address, 0444, pqi_sas_address_show, NULL);
  4855. static DEVICE_ATTR(ssd_smart_path_enabled, 0444,
  4856. pqi_ssd_smart_path_enabled_show, NULL);
  4857. static DEVICE_ATTR(raid_level, 0444, pqi_raid_level_show, NULL);
  4858. static struct device_attribute *pqi_sdev_attrs[] = {
  4859. &dev_attr_sas_address,
  4860. &dev_attr_ssd_smart_path_enabled,
  4861. &dev_attr_raid_level,
  4862. NULL
  4863. };
  4864. static struct scsi_host_template pqi_driver_template = {
  4865. .module = THIS_MODULE,
  4866. .name = DRIVER_NAME_SHORT,
  4867. .proc_name = DRIVER_NAME_SHORT,
  4868. .queuecommand = pqi_scsi_queue_command,
  4869. .scan_start = pqi_scan_start,
  4870. .scan_finished = pqi_scan_finished,
  4871. .this_id = -1,
  4872. .use_clustering = ENABLE_CLUSTERING,
  4873. .eh_device_reset_handler = pqi_eh_device_reset_handler,
  4874. .ioctl = pqi_ioctl,
  4875. .slave_alloc = pqi_slave_alloc,
  4876. .map_queues = pqi_map_queues,
  4877. .sdev_attrs = pqi_sdev_attrs,
  4878. .shost_attrs = pqi_shost_attrs,
  4879. };
  4880. static int pqi_register_scsi(struct pqi_ctrl_info *ctrl_info)
  4881. {
  4882. int rc;
  4883. struct Scsi_Host *shost;
  4884. shost = scsi_host_alloc(&pqi_driver_template, sizeof(ctrl_info));
  4885. if (!shost) {
  4886. dev_err(&ctrl_info->pci_dev->dev,
  4887. "scsi_host_alloc failed for controller %u\n",
  4888. ctrl_info->ctrl_id);
  4889. return -ENOMEM;
  4890. }
  4891. shost->io_port = 0;
  4892. shost->n_io_port = 0;
  4893. shost->this_id = -1;
  4894. shost->max_channel = PQI_MAX_BUS;
  4895. shost->max_cmd_len = MAX_COMMAND_SIZE;
  4896. shost->max_lun = ~0;
  4897. shost->max_id = ~0;
  4898. shost->max_sectors = ctrl_info->max_sectors;
  4899. shost->can_queue = ctrl_info->scsi_ml_can_queue;
  4900. shost->cmd_per_lun = shost->can_queue;
  4901. shost->sg_tablesize = ctrl_info->sg_tablesize;
  4902. shost->transportt = pqi_sas_transport_template;
  4903. shost->irq = pci_irq_vector(ctrl_info->pci_dev, 0);
  4904. shost->unique_id = shost->irq;
  4905. shost->nr_hw_queues = ctrl_info->num_queue_groups;
  4906. shost->hostdata[0] = (unsigned long)ctrl_info;
  4907. rc = scsi_add_host(shost, &ctrl_info->pci_dev->dev);
  4908. if (rc) {
  4909. dev_err(&ctrl_info->pci_dev->dev,
  4910. "scsi_add_host failed for controller %u\n",
  4911. ctrl_info->ctrl_id);
  4912. goto free_host;
  4913. }
  4914. rc = pqi_add_sas_host(shost, ctrl_info);
  4915. if (rc) {
  4916. dev_err(&ctrl_info->pci_dev->dev,
  4917. "add SAS host failed for controller %u\n",
  4918. ctrl_info->ctrl_id);
  4919. goto remove_host;
  4920. }
  4921. ctrl_info->scsi_host = shost;
  4922. return 0;
  4923. remove_host:
  4924. scsi_remove_host(shost);
  4925. free_host:
  4926. scsi_host_put(shost);
  4927. return rc;
  4928. }
  4929. static void pqi_unregister_scsi(struct pqi_ctrl_info *ctrl_info)
  4930. {
  4931. struct Scsi_Host *shost;
  4932. pqi_delete_sas_host(ctrl_info);
  4933. shost = ctrl_info->scsi_host;
  4934. if (!shost)
  4935. return;
  4936. scsi_remove_host(shost);
  4937. scsi_host_put(shost);
  4938. }
  4939. static int pqi_wait_for_pqi_reset_completion(struct pqi_ctrl_info *ctrl_info)
  4940. {
  4941. int rc = 0;
  4942. struct pqi_device_registers __iomem *pqi_registers;
  4943. unsigned long timeout;
  4944. unsigned int timeout_msecs;
  4945. union pqi_reset_register reset_reg;
  4946. pqi_registers = ctrl_info->pqi_registers;
  4947. timeout_msecs = readw(&pqi_registers->max_reset_timeout) * 100;
  4948. timeout = msecs_to_jiffies(timeout_msecs) + jiffies;
  4949. while (1) {
  4950. msleep(PQI_RESET_POLL_INTERVAL_MSECS);
  4951. reset_reg.all_bits = readl(&pqi_registers->device_reset);
  4952. if (reset_reg.bits.reset_action == PQI_RESET_ACTION_COMPLETED)
  4953. break;
  4954. pqi_check_ctrl_health(ctrl_info);
  4955. if (pqi_ctrl_offline(ctrl_info)) {
  4956. rc = -ENXIO;
  4957. break;
  4958. }
  4959. if (time_after(jiffies, timeout)) {
  4960. rc = -ETIMEDOUT;
  4961. break;
  4962. }
  4963. }
  4964. return rc;
  4965. }
  4966. static int pqi_reset(struct pqi_ctrl_info *ctrl_info)
  4967. {
  4968. int rc;
  4969. union pqi_reset_register reset_reg;
  4970. if (ctrl_info->pqi_reset_quiesce_supported) {
  4971. rc = sis_pqi_reset_quiesce(ctrl_info);
  4972. if (rc) {
  4973. dev_err(&ctrl_info->pci_dev->dev,
  4974. "PQI reset failed during quiesce with error %d\n",
  4975. rc);
  4976. return rc;
  4977. }
  4978. }
  4979. reset_reg.all_bits = 0;
  4980. reset_reg.bits.reset_type = PQI_RESET_TYPE_HARD_RESET;
  4981. reset_reg.bits.reset_action = PQI_RESET_ACTION_RESET;
  4982. writel(reset_reg.all_bits, &ctrl_info->pqi_registers->device_reset);
  4983. rc = pqi_wait_for_pqi_reset_completion(ctrl_info);
  4984. if (rc)
  4985. dev_err(&ctrl_info->pci_dev->dev,
  4986. "PQI reset failed with error %d\n", rc);
  4987. return rc;
  4988. }
  4989. static int pqi_get_ctrl_firmware_version(struct pqi_ctrl_info *ctrl_info)
  4990. {
  4991. int rc;
  4992. struct bmic_identify_controller *identify;
  4993. identify = kmalloc(sizeof(*identify), GFP_KERNEL);
  4994. if (!identify)
  4995. return -ENOMEM;
  4996. rc = pqi_identify_controller(ctrl_info, identify);
  4997. if (rc)
  4998. goto out;
  4999. memcpy(ctrl_info->firmware_version, identify->firmware_version,
  5000. sizeof(identify->firmware_version));
  5001. ctrl_info->firmware_version[sizeof(identify->firmware_version)] = '\0';
  5002. snprintf(ctrl_info->firmware_version +
  5003. strlen(ctrl_info->firmware_version),
  5004. sizeof(ctrl_info->firmware_version),
  5005. "-%u", get_unaligned_le16(&identify->firmware_build_number));
  5006. out:
  5007. kfree(identify);
  5008. return rc;
  5009. }
  5010. static int pqi_process_config_table(struct pqi_ctrl_info *ctrl_info)
  5011. {
  5012. u32 table_length;
  5013. u32 section_offset;
  5014. void __iomem *table_iomem_addr;
  5015. struct pqi_config_table *config_table;
  5016. struct pqi_config_table_section_header *section;
  5017. table_length = ctrl_info->config_table_length;
  5018. config_table = kmalloc(table_length, GFP_KERNEL);
  5019. if (!config_table) {
  5020. dev_err(&ctrl_info->pci_dev->dev,
  5021. "failed to allocate memory for PQI configuration table\n");
  5022. return -ENOMEM;
  5023. }
  5024. /*
  5025. * Copy the config table contents from I/O memory space into the
  5026. * temporary buffer.
  5027. */
  5028. table_iomem_addr = ctrl_info->iomem_base +
  5029. ctrl_info->config_table_offset;
  5030. memcpy_fromio(config_table, table_iomem_addr, table_length);
  5031. section_offset =
  5032. get_unaligned_le32(&config_table->first_section_offset);
  5033. while (section_offset) {
  5034. section = (void *)config_table + section_offset;
  5035. switch (get_unaligned_le16(&section->section_id)) {
  5036. case PQI_CONFIG_TABLE_SECTION_HEARTBEAT:
  5037. if (pqi_disable_heartbeat)
  5038. dev_warn(&ctrl_info->pci_dev->dev,
  5039. "heartbeat disabled by module parameter\n");
  5040. else
  5041. ctrl_info->heartbeat_counter =
  5042. table_iomem_addr +
  5043. section_offset +
  5044. offsetof(
  5045. struct pqi_config_table_heartbeat,
  5046. heartbeat_counter);
  5047. break;
  5048. }
  5049. section_offset =
  5050. get_unaligned_le16(&section->next_section_offset);
  5051. }
  5052. kfree(config_table);
  5053. return 0;
  5054. }
  5055. /* Switches the controller from PQI mode back into SIS mode. */
  5056. static int pqi_revert_to_sis_mode(struct pqi_ctrl_info *ctrl_info)
  5057. {
  5058. int rc;
  5059. pqi_change_irq_mode(ctrl_info, IRQ_MODE_NONE);
  5060. rc = pqi_reset(ctrl_info);
  5061. if (rc)
  5062. return rc;
  5063. rc = sis_reenable_sis_mode(ctrl_info);
  5064. if (rc) {
  5065. dev_err(&ctrl_info->pci_dev->dev,
  5066. "re-enabling SIS mode failed with error %d\n", rc);
  5067. return rc;
  5068. }
  5069. pqi_save_ctrl_mode(ctrl_info, SIS_MODE);
  5070. return 0;
  5071. }
  5072. /*
  5073. * If the controller isn't already in SIS mode, this function forces it into
  5074. * SIS mode.
  5075. */
  5076. static int pqi_force_sis_mode(struct pqi_ctrl_info *ctrl_info)
  5077. {
  5078. if (!sis_is_firmware_running(ctrl_info))
  5079. return -ENXIO;
  5080. if (pqi_get_ctrl_mode(ctrl_info) == SIS_MODE)
  5081. return 0;
  5082. if (sis_is_kernel_up(ctrl_info)) {
  5083. pqi_save_ctrl_mode(ctrl_info, SIS_MODE);
  5084. return 0;
  5085. }
  5086. return pqi_revert_to_sis_mode(ctrl_info);
  5087. }
  5088. static int pqi_ctrl_init(struct pqi_ctrl_info *ctrl_info)
  5089. {
  5090. int rc;
  5091. rc = pqi_force_sis_mode(ctrl_info);
  5092. if (rc)
  5093. return rc;
  5094. /*
  5095. * Wait until the controller is ready to start accepting SIS
  5096. * commands.
  5097. */
  5098. rc = sis_wait_for_ctrl_ready(ctrl_info);
  5099. if (rc)
  5100. return rc;
  5101. /*
  5102. * Get the controller properties. This allows us to determine
  5103. * whether or not it supports PQI mode.
  5104. */
  5105. rc = sis_get_ctrl_properties(ctrl_info);
  5106. if (rc) {
  5107. dev_err(&ctrl_info->pci_dev->dev,
  5108. "error obtaining controller properties\n");
  5109. return rc;
  5110. }
  5111. rc = sis_get_pqi_capabilities(ctrl_info);
  5112. if (rc) {
  5113. dev_err(&ctrl_info->pci_dev->dev,
  5114. "error obtaining controller capabilities\n");
  5115. return rc;
  5116. }
  5117. if (reset_devices) {
  5118. if (ctrl_info->max_outstanding_requests >
  5119. PQI_MAX_OUTSTANDING_REQUESTS_KDUMP)
  5120. ctrl_info->max_outstanding_requests =
  5121. PQI_MAX_OUTSTANDING_REQUESTS_KDUMP;
  5122. } else {
  5123. if (ctrl_info->max_outstanding_requests >
  5124. PQI_MAX_OUTSTANDING_REQUESTS)
  5125. ctrl_info->max_outstanding_requests =
  5126. PQI_MAX_OUTSTANDING_REQUESTS;
  5127. }
  5128. pqi_calculate_io_resources(ctrl_info);
  5129. rc = pqi_alloc_error_buffer(ctrl_info);
  5130. if (rc) {
  5131. dev_err(&ctrl_info->pci_dev->dev,
  5132. "failed to allocate PQI error buffer\n");
  5133. return rc;
  5134. }
  5135. /*
  5136. * If the function we are about to call succeeds, the
  5137. * controller will transition from legacy SIS mode
  5138. * into PQI mode.
  5139. */
  5140. rc = sis_init_base_struct_addr(ctrl_info);
  5141. if (rc) {
  5142. dev_err(&ctrl_info->pci_dev->dev,
  5143. "error initializing PQI mode\n");
  5144. return rc;
  5145. }
  5146. /* Wait for the controller to complete the SIS -> PQI transition. */
  5147. rc = pqi_wait_for_pqi_mode_ready(ctrl_info);
  5148. if (rc) {
  5149. dev_err(&ctrl_info->pci_dev->dev,
  5150. "transition to PQI mode failed\n");
  5151. return rc;
  5152. }
  5153. /* From here on, we are running in PQI mode. */
  5154. ctrl_info->pqi_mode_enabled = true;
  5155. pqi_save_ctrl_mode(ctrl_info, PQI_MODE);
  5156. rc = pqi_process_config_table(ctrl_info);
  5157. if (rc)
  5158. return rc;
  5159. rc = pqi_alloc_admin_queues(ctrl_info);
  5160. if (rc) {
  5161. dev_err(&ctrl_info->pci_dev->dev,
  5162. "failed to allocate admin queues\n");
  5163. return rc;
  5164. }
  5165. rc = pqi_create_admin_queues(ctrl_info);
  5166. if (rc) {
  5167. dev_err(&ctrl_info->pci_dev->dev,
  5168. "error creating admin queues\n");
  5169. return rc;
  5170. }
  5171. rc = pqi_report_device_capability(ctrl_info);
  5172. if (rc) {
  5173. dev_err(&ctrl_info->pci_dev->dev,
  5174. "obtaining device capability failed\n");
  5175. return rc;
  5176. }
  5177. rc = pqi_validate_device_capability(ctrl_info);
  5178. if (rc)
  5179. return rc;
  5180. pqi_calculate_queue_resources(ctrl_info);
  5181. rc = pqi_enable_msix_interrupts(ctrl_info);
  5182. if (rc)
  5183. return rc;
  5184. if (ctrl_info->num_msix_vectors_enabled < ctrl_info->num_queue_groups) {
  5185. ctrl_info->max_msix_vectors =
  5186. ctrl_info->num_msix_vectors_enabled;
  5187. pqi_calculate_queue_resources(ctrl_info);
  5188. }
  5189. rc = pqi_alloc_io_resources(ctrl_info);
  5190. if (rc)
  5191. return rc;
  5192. rc = pqi_alloc_operational_queues(ctrl_info);
  5193. if (rc) {
  5194. dev_err(&ctrl_info->pci_dev->dev,
  5195. "failed to allocate operational queues\n");
  5196. return rc;
  5197. }
  5198. pqi_init_operational_queues(ctrl_info);
  5199. rc = pqi_request_irqs(ctrl_info);
  5200. if (rc)
  5201. return rc;
  5202. rc = pqi_create_queues(ctrl_info);
  5203. if (rc)
  5204. return rc;
  5205. pqi_change_irq_mode(ctrl_info, IRQ_MODE_MSIX);
  5206. ctrl_info->controller_online = true;
  5207. pqi_start_heartbeat_timer(ctrl_info);
  5208. rc = pqi_enable_events(ctrl_info);
  5209. if (rc) {
  5210. dev_err(&ctrl_info->pci_dev->dev,
  5211. "error enabling events\n");
  5212. return rc;
  5213. }
  5214. /* Register with the SCSI subsystem. */
  5215. rc = pqi_register_scsi(ctrl_info);
  5216. if (rc)
  5217. return rc;
  5218. rc = pqi_get_ctrl_firmware_version(ctrl_info);
  5219. if (rc) {
  5220. dev_err(&ctrl_info->pci_dev->dev,
  5221. "error obtaining firmware version\n");
  5222. return rc;
  5223. }
  5224. rc = pqi_write_driver_version_to_host_wellness(ctrl_info);
  5225. if (rc) {
  5226. dev_err(&ctrl_info->pci_dev->dev,
  5227. "error updating host wellness\n");
  5228. return rc;
  5229. }
  5230. pqi_schedule_update_time_worker(ctrl_info);
  5231. pqi_scan_scsi_devices(ctrl_info);
  5232. return 0;
  5233. }
  5234. static void pqi_reinit_queues(struct pqi_ctrl_info *ctrl_info)
  5235. {
  5236. unsigned int i;
  5237. struct pqi_admin_queues *admin_queues;
  5238. struct pqi_event_queue *event_queue;
  5239. admin_queues = &ctrl_info->admin_queues;
  5240. admin_queues->iq_pi_copy = 0;
  5241. admin_queues->oq_ci_copy = 0;
  5242. writel(0, admin_queues->oq_pi);
  5243. for (i = 0; i < ctrl_info->num_queue_groups; i++) {
  5244. ctrl_info->queue_groups[i].iq_pi_copy[RAID_PATH] = 0;
  5245. ctrl_info->queue_groups[i].iq_pi_copy[AIO_PATH] = 0;
  5246. ctrl_info->queue_groups[i].oq_ci_copy = 0;
  5247. writel(0, ctrl_info->queue_groups[i].iq_ci[RAID_PATH]);
  5248. writel(0, ctrl_info->queue_groups[i].iq_ci[AIO_PATH]);
  5249. writel(0, ctrl_info->queue_groups[i].oq_pi);
  5250. }
  5251. event_queue = &ctrl_info->event_queue;
  5252. writel(0, event_queue->oq_pi);
  5253. event_queue->oq_ci_copy = 0;
  5254. }
  5255. static int pqi_ctrl_init_resume(struct pqi_ctrl_info *ctrl_info)
  5256. {
  5257. int rc;
  5258. rc = pqi_force_sis_mode(ctrl_info);
  5259. if (rc)
  5260. return rc;
  5261. /*
  5262. * Wait until the controller is ready to start accepting SIS
  5263. * commands.
  5264. */
  5265. rc = sis_wait_for_ctrl_ready_resume(ctrl_info);
  5266. if (rc)
  5267. return rc;
  5268. /*
  5269. * If the function we are about to call succeeds, the
  5270. * controller will transition from legacy SIS mode
  5271. * into PQI mode.
  5272. */
  5273. rc = sis_init_base_struct_addr(ctrl_info);
  5274. if (rc) {
  5275. dev_err(&ctrl_info->pci_dev->dev,
  5276. "error initializing PQI mode\n");
  5277. return rc;
  5278. }
  5279. /* Wait for the controller to complete the SIS -> PQI transition. */
  5280. rc = pqi_wait_for_pqi_mode_ready(ctrl_info);
  5281. if (rc) {
  5282. dev_err(&ctrl_info->pci_dev->dev,
  5283. "transition to PQI mode failed\n");
  5284. return rc;
  5285. }
  5286. /* From here on, we are running in PQI mode. */
  5287. ctrl_info->pqi_mode_enabled = true;
  5288. pqi_save_ctrl_mode(ctrl_info, PQI_MODE);
  5289. pqi_reinit_queues(ctrl_info);
  5290. rc = pqi_create_admin_queues(ctrl_info);
  5291. if (rc) {
  5292. dev_err(&ctrl_info->pci_dev->dev,
  5293. "error creating admin queues\n");
  5294. return rc;
  5295. }
  5296. rc = pqi_create_queues(ctrl_info);
  5297. if (rc)
  5298. return rc;
  5299. pqi_change_irq_mode(ctrl_info, IRQ_MODE_MSIX);
  5300. ctrl_info->controller_online = true;
  5301. pqi_start_heartbeat_timer(ctrl_info);
  5302. pqi_ctrl_unblock_requests(ctrl_info);
  5303. rc = pqi_enable_events(ctrl_info);
  5304. if (rc) {
  5305. dev_err(&ctrl_info->pci_dev->dev,
  5306. "error enabling events\n");
  5307. return rc;
  5308. }
  5309. rc = pqi_write_driver_version_to_host_wellness(ctrl_info);
  5310. if (rc) {
  5311. dev_err(&ctrl_info->pci_dev->dev,
  5312. "error updating host wellness\n");
  5313. return rc;
  5314. }
  5315. pqi_schedule_update_time_worker(ctrl_info);
  5316. pqi_scan_scsi_devices(ctrl_info);
  5317. return 0;
  5318. }
  5319. static inline int pqi_set_pcie_completion_timeout(struct pci_dev *pci_dev,
  5320. u16 timeout)
  5321. {
  5322. return pcie_capability_clear_and_set_word(pci_dev, PCI_EXP_DEVCTL2,
  5323. PCI_EXP_DEVCTL2_COMP_TIMEOUT, timeout);
  5324. }
  5325. static int pqi_pci_init(struct pqi_ctrl_info *ctrl_info)
  5326. {
  5327. int rc;
  5328. u64 mask;
  5329. rc = pci_enable_device(ctrl_info->pci_dev);
  5330. if (rc) {
  5331. dev_err(&ctrl_info->pci_dev->dev,
  5332. "failed to enable PCI device\n");
  5333. return rc;
  5334. }
  5335. if (sizeof(dma_addr_t) > 4)
  5336. mask = DMA_BIT_MASK(64);
  5337. else
  5338. mask = DMA_BIT_MASK(32);
  5339. rc = dma_set_mask_and_coherent(&ctrl_info->pci_dev->dev, mask);
  5340. if (rc) {
  5341. dev_err(&ctrl_info->pci_dev->dev, "failed to set DMA mask\n");
  5342. goto disable_device;
  5343. }
  5344. rc = pci_request_regions(ctrl_info->pci_dev, DRIVER_NAME_SHORT);
  5345. if (rc) {
  5346. dev_err(&ctrl_info->pci_dev->dev,
  5347. "failed to obtain PCI resources\n");
  5348. goto disable_device;
  5349. }
  5350. ctrl_info->iomem_base = ioremap_nocache(pci_resource_start(
  5351. ctrl_info->pci_dev, 0),
  5352. sizeof(struct pqi_ctrl_registers));
  5353. if (!ctrl_info->iomem_base) {
  5354. dev_err(&ctrl_info->pci_dev->dev,
  5355. "failed to map memory for controller registers\n");
  5356. rc = -ENOMEM;
  5357. goto release_regions;
  5358. }
  5359. #define PCI_EXP_COMP_TIMEOUT_65_TO_210_MS 0x6
  5360. /* Increase the PCIe completion timeout. */
  5361. rc = pqi_set_pcie_completion_timeout(ctrl_info->pci_dev,
  5362. PCI_EXP_COMP_TIMEOUT_65_TO_210_MS);
  5363. if (rc) {
  5364. dev_err(&ctrl_info->pci_dev->dev,
  5365. "failed to set PCIe completion timeout\n");
  5366. goto release_regions;
  5367. }
  5368. /* Enable bus mastering. */
  5369. pci_set_master(ctrl_info->pci_dev);
  5370. ctrl_info->registers = ctrl_info->iomem_base;
  5371. ctrl_info->pqi_registers = &ctrl_info->registers->pqi_registers;
  5372. pci_set_drvdata(ctrl_info->pci_dev, ctrl_info);
  5373. return 0;
  5374. release_regions:
  5375. pci_release_regions(ctrl_info->pci_dev);
  5376. disable_device:
  5377. pci_disable_device(ctrl_info->pci_dev);
  5378. return rc;
  5379. }
  5380. static void pqi_cleanup_pci_init(struct pqi_ctrl_info *ctrl_info)
  5381. {
  5382. iounmap(ctrl_info->iomem_base);
  5383. pci_release_regions(ctrl_info->pci_dev);
  5384. if (pci_is_enabled(ctrl_info->pci_dev))
  5385. pci_disable_device(ctrl_info->pci_dev);
  5386. pci_set_drvdata(ctrl_info->pci_dev, NULL);
  5387. }
  5388. static struct pqi_ctrl_info *pqi_alloc_ctrl_info(int numa_node)
  5389. {
  5390. struct pqi_ctrl_info *ctrl_info;
  5391. ctrl_info = kzalloc_node(sizeof(struct pqi_ctrl_info),
  5392. GFP_KERNEL, numa_node);
  5393. if (!ctrl_info)
  5394. return NULL;
  5395. mutex_init(&ctrl_info->scan_mutex);
  5396. mutex_init(&ctrl_info->lun_reset_mutex);
  5397. INIT_LIST_HEAD(&ctrl_info->scsi_device_list);
  5398. spin_lock_init(&ctrl_info->scsi_device_list_lock);
  5399. INIT_WORK(&ctrl_info->event_work, pqi_event_worker);
  5400. atomic_set(&ctrl_info->num_interrupts, 0);
  5401. INIT_DELAYED_WORK(&ctrl_info->rescan_work, pqi_rescan_worker);
  5402. INIT_DELAYED_WORK(&ctrl_info->update_time_work, pqi_update_time_worker);
  5403. timer_setup(&ctrl_info->heartbeat_timer, pqi_heartbeat_timer_handler, 0);
  5404. INIT_WORK(&ctrl_info->ctrl_offline_work, pqi_ctrl_offline_worker);
  5405. sema_init(&ctrl_info->sync_request_sem,
  5406. PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS);
  5407. init_waitqueue_head(&ctrl_info->block_requests_wait);
  5408. INIT_LIST_HEAD(&ctrl_info->raid_bypass_retry_list);
  5409. spin_lock_init(&ctrl_info->raid_bypass_retry_list_lock);
  5410. INIT_WORK(&ctrl_info->raid_bypass_retry_work,
  5411. pqi_raid_bypass_retry_worker);
  5412. ctrl_info->ctrl_id = atomic_inc_return(&pqi_controller_count) - 1;
  5413. ctrl_info->irq_mode = IRQ_MODE_NONE;
  5414. ctrl_info->max_msix_vectors = PQI_MAX_MSIX_VECTORS;
  5415. return ctrl_info;
  5416. }
  5417. static inline void pqi_free_ctrl_info(struct pqi_ctrl_info *ctrl_info)
  5418. {
  5419. kfree(ctrl_info);
  5420. }
  5421. static void pqi_free_interrupts(struct pqi_ctrl_info *ctrl_info)
  5422. {
  5423. pqi_free_irqs(ctrl_info);
  5424. pqi_disable_msix_interrupts(ctrl_info);
  5425. }
  5426. static void pqi_free_ctrl_resources(struct pqi_ctrl_info *ctrl_info)
  5427. {
  5428. pqi_stop_heartbeat_timer(ctrl_info);
  5429. pqi_free_interrupts(ctrl_info);
  5430. if (ctrl_info->queue_memory_base)
  5431. dma_free_coherent(&ctrl_info->pci_dev->dev,
  5432. ctrl_info->queue_memory_length,
  5433. ctrl_info->queue_memory_base,
  5434. ctrl_info->queue_memory_base_dma_handle);
  5435. if (ctrl_info->admin_queue_memory_base)
  5436. dma_free_coherent(&ctrl_info->pci_dev->dev,
  5437. ctrl_info->admin_queue_memory_length,
  5438. ctrl_info->admin_queue_memory_base,
  5439. ctrl_info->admin_queue_memory_base_dma_handle);
  5440. pqi_free_all_io_requests(ctrl_info);
  5441. if (ctrl_info->error_buffer)
  5442. dma_free_coherent(&ctrl_info->pci_dev->dev,
  5443. ctrl_info->error_buffer_length,
  5444. ctrl_info->error_buffer,
  5445. ctrl_info->error_buffer_dma_handle);
  5446. if (ctrl_info->iomem_base)
  5447. pqi_cleanup_pci_init(ctrl_info);
  5448. pqi_free_ctrl_info(ctrl_info);
  5449. }
  5450. static void pqi_remove_ctrl(struct pqi_ctrl_info *ctrl_info)
  5451. {
  5452. pqi_cancel_rescan_worker(ctrl_info);
  5453. pqi_cancel_update_time_worker(ctrl_info);
  5454. pqi_remove_all_scsi_devices(ctrl_info);
  5455. pqi_unregister_scsi(ctrl_info);
  5456. if (ctrl_info->pqi_mode_enabled)
  5457. pqi_revert_to_sis_mode(ctrl_info);
  5458. pqi_free_ctrl_resources(ctrl_info);
  5459. }
  5460. static void pqi_perform_lockup_action(void)
  5461. {
  5462. switch (pqi_lockup_action) {
  5463. case PANIC:
  5464. panic("FATAL: Smart Family Controller lockup detected");
  5465. break;
  5466. case REBOOT:
  5467. emergency_restart();
  5468. break;
  5469. case NONE:
  5470. default:
  5471. break;
  5472. }
  5473. }
  5474. static struct pqi_raid_error_info pqi_ctrl_offline_raid_error_info = {
  5475. .data_out_result = PQI_DATA_IN_OUT_HARDWARE_ERROR,
  5476. .status = SAM_STAT_CHECK_CONDITION,
  5477. };
  5478. static void pqi_fail_all_outstanding_requests(struct pqi_ctrl_info *ctrl_info)
  5479. {
  5480. unsigned int i;
  5481. struct pqi_io_request *io_request;
  5482. struct scsi_cmnd *scmd;
  5483. for (i = 0; i < ctrl_info->max_io_slots; i++) {
  5484. io_request = &ctrl_info->io_request_pool[i];
  5485. if (atomic_read(&io_request->refcount) == 0)
  5486. continue;
  5487. scmd = io_request->scmd;
  5488. if (scmd) {
  5489. set_host_byte(scmd, DID_NO_CONNECT);
  5490. } else {
  5491. io_request->status = -ENXIO;
  5492. io_request->error_info =
  5493. &pqi_ctrl_offline_raid_error_info;
  5494. }
  5495. io_request->io_complete_callback(io_request,
  5496. io_request->context);
  5497. }
  5498. }
  5499. static void pqi_take_ctrl_offline_deferred(struct pqi_ctrl_info *ctrl_info)
  5500. {
  5501. pqi_perform_lockup_action();
  5502. pqi_stop_heartbeat_timer(ctrl_info);
  5503. pqi_free_interrupts(ctrl_info);
  5504. pqi_cancel_rescan_worker(ctrl_info);
  5505. pqi_cancel_update_time_worker(ctrl_info);
  5506. pqi_ctrl_wait_until_quiesced(ctrl_info);
  5507. pqi_fail_all_outstanding_requests(ctrl_info);
  5508. pqi_clear_all_queued_raid_bypass_retries(ctrl_info);
  5509. pqi_ctrl_unblock_requests(ctrl_info);
  5510. }
  5511. static void pqi_ctrl_offline_worker(struct work_struct *work)
  5512. {
  5513. struct pqi_ctrl_info *ctrl_info;
  5514. ctrl_info = container_of(work, struct pqi_ctrl_info, ctrl_offline_work);
  5515. pqi_take_ctrl_offline_deferred(ctrl_info);
  5516. }
  5517. static void pqi_take_ctrl_offline(struct pqi_ctrl_info *ctrl_info)
  5518. {
  5519. if (!ctrl_info->controller_online)
  5520. return;
  5521. ctrl_info->controller_online = false;
  5522. ctrl_info->pqi_mode_enabled = false;
  5523. pqi_ctrl_block_requests(ctrl_info);
  5524. if (!pqi_disable_ctrl_shutdown)
  5525. sis_shutdown_ctrl(ctrl_info);
  5526. pci_disable_device(ctrl_info->pci_dev);
  5527. dev_err(&ctrl_info->pci_dev->dev, "controller offline\n");
  5528. schedule_work(&ctrl_info->ctrl_offline_work);
  5529. }
  5530. static void pqi_print_ctrl_info(struct pci_dev *pci_dev,
  5531. const struct pci_device_id *id)
  5532. {
  5533. char *ctrl_description;
  5534. if (id->driver_data)
  5535. ctrl_description = (char *)id->driver_data;
  5536. else
  5537. ctrl_description = "Microsemi Smart Family Controller";
  5538. dev_info(&pci_dev->dev, "%s found\n", ctrl_description);
  5539. }
  5540. static int pqi_pci_probe(struct pci_dev *pci_dev,
  5541. const struct pci_device_id *id)
  5542. {
  5543. int rc;
  5544. int node;
  5545. struct pqi_ctrl_info *ctrl_info;
  5546. pqi_print_ctrl_info(pci_dev, id);
  5547. if (pqi_disable_device_id_wildcards &&
  5548. id->subvendor == PCI_ANY_ID &&
  5549. id->subdevice == PCI_ANY_ID) {
  5550. dev_warn(&pci_dev->dev,
  5551. "controller not probed because device ID wildcards are disabled\n");
  5552. return -ENODEV;
  5553. }
  5554. if (id->subvendor == PCI_ANY_ID || id->subdevice == PCI_ANY_ID)
  5555. dev_warn(&pci_dev->dev,
  5556. "controller device ID matched using wildcards\n");
  5557. node = dev_to_node(&pci_dev->dev);
  5558. if (node == NUMA_NO_NODE)
  5559. set_dev_node(&pci_dev->dev, 0);
  5560. ctrl_info = pqi_alloc_ctrl_info(node);
  5561. if (!ctrl_info) {
  5562. dev_err(&pci_dev->dev,
  5563. "failed to allocate controller info block\n");
  5564. return -ENOMEM;
  5565. }
  5566. ctrl_info->pci_dev = pci_dev;
  5567. rc = pqi_pci_init(ctrl_info);
  5568. if (rc)
  5569. goto error;
  5570. rc = pqi_ctrl_init(ctrl_info);
  5571. if (rc)
  5572. goto error;
  5573. return 0;
  5574. error:
  5575. pqi_remove_ctrl(ctrl_info);
  5576. return rc;
  5577. }
  5578. static void pqi_pci_remove(struct pci_dev *pci_dev)
  5579. {
  5580. struct pqi_ctrl_info *ctrl_info;
  5581. ctrl_info = pci_get_drvdata(pci_dev);
  5582. if (!ctrl_info)
  5583. return;
  5584. pqi_remove_ctrl(ctrl_info);
  5585. }
  5586. static void pqi_shutdown(struct pci_dev *pci_dev)
  5587. {
  5588. int rc;
  5589. struct pqi_ctrl_info *ctrl_info;
  5590. ctrl_info = pci_get_drvdata(pci_dev);
  5591. if (!ctrl_info)
  5592. goto error;
  5593. /*
  5594. * Write all data in the controller's battery-backed cache to
  5595. * storage.
  5596. */
  5597. rc = pqi_flush_cache(ctrl_info, SHUTDOWN);
  5598. pqi_free_interrupts(ctrl_info);
  5599. pqi_reset(ctrl_info);
  5600. if (rc == 0)
  5601. return;
  5602. error:
  5603. dev_warn(&pci_dev->dev,
  5604. "unable to flush controller cache\n");
  5605. }
  5606. static void pqi_process_lockup_action_param(void)
  5607. {
  5608. unsigned int i;
  5609. if (!pqi_lockup_action_param)
  5610. return;
  5611. for (i = 0; i < ARRAY_SIZE(pqi_lockup_actions); i++) {
  5612. if (strcmp(pqi_lockup_action_param,
  5613. pqi_lockup_actions[i].name) == 0) {
  5614. pqi_lockup_action = pqi_lockup_actions[i].action;
  5615. return;
  5616. }
  5617. }
  5618. pr_warn("%s: invalid lockup action setting \"%s\" - supported settings: none, reboot, panic\n",
  5619. DRIVER_NAME_SHORT, pqi_lockup_action_param);
  5620. }
  5621. static void pqi_process_module_params(void)
  5622. {
  5623. pqi_process_lockup_action_param();
  5624. }
  5625. static __maybe_unused int pqi_suspend(struct pci_dev *pci_dev, pm_message_t state)
  5626. {
  5627. struct pqi_ctrl_info *ctrl_info;
  5628. ctrl_info = pci_get_drvdata(pci_dev);
  5629. pqi_disable_events(ctrl_info);
  5630. pqi_cancel_update_time_worker(ctrl_info);
  5631. pqi_cancel_rescan_worker(ctrl_info);
  5632. pqi_wait_until_scan_finished(ctrl_info);
  5633. pqi_wait_until_lun_reset_finished(ctrl_info);
  5634. pqi_flush_cache(ctrl_info, SUSPEND);
  5635. pqi_ctrl_block_requests(ctrl_info);
  5636. pqi_ctrl_wait_until_quiesced(ctrl_info);
  5637. pqi_wait_until_inbound_queues_empty(ctrl_info);
  5638. pqi_ctrl_wait_for_pending_io(ctrl_info);
  5639. pqi_stop_heartbeat_timer(ctrl_info);
  5640. if (state.event == PM_EVENT_FREEZE)
  5641. return 0;
  5642. pci_save_state(pci_dev);
  5643. pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
  5644. ctrl_info->controller_online = false;
  5645. ctrl_info->pqi_mode_enabled = false;
  5646. return 0;
  5647. }
  5648. static __maybe_unused int pqi_resume(struct pci_dev *pci_dev)
  5649. {
  5650. int rc;
  5651. struct pqi_ctrl_info *ctrl_info;
  5652. ctrl_info = pci_get_drvdata(pci_dev);
  5653. if (pci_dev->current_state != PCI_D0) {
  5654. ctrl_info->max_hw_queue_index = 0;
  5655. pqi_free_interrupts(ctrl_info);
  5656. pqi_change_irq_mode(ctrl_info, IRQ_MODE_INTX);
  5657. rc = request_irq(pci_irq_vector(pci_dev, 0), pqi_irq_handler,
  5658. IRQF_SHARED, DRIVER_NAME_SHORT,
  5659. &ctrl_info->queue_groups[0]);
  5660. if (rc) {
  5661. dev_err(&ctrl_info->pci_dev->dev,
  5662. "irq %u init failed with error %d\n",
  5663. pci_dev->irq, rc);
  5664. return rc;
  5665. }
  5666. pqi_start_heartbeat_timer(ctrl_info);
  5667. pqi_ctrl_unblock_requests(ctrl_info);
  5668. return 0;
  5669. }
  5670. pci_set_power_state(pci_dev, PCI_D0);
  5671. pci_restore_state(pci_dev);
  5672. return pqi_ctrl_init_resume(ctrl_info);
  5673. }
  5674. /* Define the PCI IDs for the controllers that we support. */
  5675. static const struct pci_device_id pqi_pci_id_table[] = {
  5676. {
  5677. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5678. 0x105b, 0x1211)
  5679. },
  5680. {
  5681. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5682. 0x105b, 0x1321)
  5683. },
  5684. {
  5685. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5686. 0x152d, 0x8a22)
  5687. },
  5688. {
  5689. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5690. 0x152d, 0x8a23)
  5691. },
  5692. {
  5693. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5694. 0x152d, 0x8a24)
  5695. },
  5696. {
  5697. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5698. 0x152d, 0x8a36)
  5699. },
  5700. {
  5701. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5702. 0x152d, 0x8a37)
  5703. },
  5704. {
  5705. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5706. 0x193d, 0x8460)
  5707. },
  5708. {
  5709. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5710. 0x193d, 0x8461)
  5711. },
  5712. {
  5713. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5714. 0x193d, 0xf460)
  5715. },
  5716. {
  5717. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5718. 0x193d, 0xf461)
  5719. },
  5720. {
  5721. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5722. 0x1bd4, 0x0045)
  5723. },
  5724. {
  5725. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5726. 0x1bd4, 0x0046)
  5727. },
  5728. {
  5729. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5730. 0x1bd4, 0x0047)
  5731. },
  5732. {
  5733. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5734. 0x1bd4, 0x0048)
  5735. },
  5736. {
  5737. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5738. 0x1bd4, 0x004a)
  5739. },
  5740. {
  5741. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5742. 0x1bd4, 0x004b)
  5743. },
  5744. {
  5745. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5746. 0x1bd4, 0x004c)
  5747. },
  5748. {
  5749. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5750. PCI_VENDOR_ID_ADAPTEC2, 0x0110)
  5751. },
  5752. {
  5753. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5754. PCI_VENDOR_ID_ADAPTEC2, 0x0608)
  5755. },
  5756. {
  5757. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5758. PCI_VENDOR_ID_ADAPTEC2, 0x0800)
  5759. },
  5760. {
  5761. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5762. PCI_VENDOR_ID_ADAPTEC2, 0x0801)
  5763. },
  5764. {
  5765. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5766. PCI_VENDOR_ID_ADAPTEC2, 0x0802)
  5767. },
  5768. {
  5769. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5770. PCI_VENDOR_ID_ADAPTEC2, 0x0803)
  5771. },
  5772. {
  5773. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5774. PCI_VENDOR_ID_ADAPTEC2, 0x0804)
  5775. },
  5776. {
  5777. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5778. PCI_VENDOR_ID_ADAPTEC2, 0x0805)
  5779. },
  5780. {
  5781. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5782. PCI_VENDOR_ID_ADAPTEC2, 0x0806)
  5783. },
  5784. {
  5785. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5786. PCI_VENDOR_ID_ADAPTEC2, 0x0807)
  5787. },
  5788. {
  5789. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5790. PCI_VENDOR_ID_ADAPTEC2, 0x0900)
  5791. },
  5792. {
  5793. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5794. PCI_VENDOR_ID_ADAPTEC2, 0x0901)
  5795. },
  5796. {
  5797. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5798. PCI_VENDOR_ID_ADAPTEC2, 0x0902)
  5799. },
  5800. {
  5801. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5802. PCI_VENDOR_ID_ADAPTEC2, 0x0903)
  5803. },
  5804. {
  5805. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5806. PCI_VENDOR_ID_ADAPTEC2, 0x0904)
  5807. },
  5808. {
  5809. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5810. PCI_VENDOR_ID_ADAPTEC2, 0x0905)
  5811. },
  5812. {
  5813. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5814. PCI_VENDOR_ID_ADAPTEC2, 0x0906)
  5815. },
  5816. {
  5817. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5818. PCI_VENDOR_ID_ADAPTEC2, 0x0907)
  5819. },
  5820. {
  5821. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5822. PCI_VENDOR_ID_ADAPTEC2, 0x0908)
  5823. },
  5824. {
  5825. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5826. PCI_VENDOR_ID_ADAPTEC2, 0x090a)
  5827. },
  5828. {
  5829. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5830. PCI_VENDOR_ID_ADAPTEC2, 0x1200)
  5831. },
  5832. {
  5833. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5834. PCI_VENDOR_ID_ADAPTEC2, 0x1201)
  5835. },
  5836. {
  5837. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5838. PCI_VENDOR_ID_ADAPTEC2, 0x1202)
  5839. },
  5840. {
  5841. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5842. PCI_VENDOR_ID_ADAPTEC2, 0x1280)
  5843. },
  5844. {
  5845. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5846. PCI_VENDOR_ID_ADAPTEC2, 0x1281)
  5847. },
  5848. {
  5849. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5850. PCI_VENDOR_ID_ADAPTEC2, 0x1282)
  5851. },
  5852. {
  5853. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5854. PCI_VENDOR_ID_ADAPTEC2, 0x1300)
  5855. },
  5856. {
  5857. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5858. PCI_VENDOR_ID_ADAPTEC2, 0x1301)
  5859. },
  5860. {
  5861. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5862. PCI_VENDOR_ID_ADAPTEC2, 0x1302)
  5863. },
  5864. {
  5865. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5866. PCI_VENDOR_ID_ADAPTEC2, 0x1303)
  5867. },
  5868. {
  5869. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5870. PCI_VENDOR_ID_ADAPTEC2, 0x1380)
  5871. },
  5872. {
  5873. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5874. PCI_VENDOR_ID_ADVANTECH, 0x8312)
  5875. },
  5876. {
  5877. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5878. PCI_VENDOR_ID_DELL, 0x1fe0)
  5879. },
  5880. {
  5881. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5882. PCI_VENDOR_ID_HP, 0x0600)
  5883. },
  5884. {
  5885. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5886. PCI_VENDOR_ID_HP, 0x0601)
  5887. },
  5888. {
  5889. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5890. PCI_VENDOR_ID_HP, 0x0602)
  5891. },
  5892. {
  5893. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5894. PCI_VENDOR_ID_HP, 0x0603)
  5895. },
  5896. {
  5897. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5898. PCI_VENDOR_ID_HP, 0x0609)
  5899. },
  5900. {
  5901. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5902. PCI_VENDOR_ID_HP, 0x0650)
  5903. },
  5904. {
  5905. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5906. PCI_VENDOR_ID_HP, 0x0651)
  5907. },
  5908. {
  5909. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5910. PCI_VENDOR_ID_HP, 0x0652)
  5911. },
  5912. {
  5913. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5914. PCI_VENDOR_ID_HP, 0x0653)
  5915. },
  5916. {
  5917. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5918. PCI_VENDOR_ID_HP, 0x0654)
  5919. },
  5920. {
  5921. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5922. PCI_VENDOR_ID_HP, 0x0655)
  5923. },
  5924. {
  5925. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5926. PCI_VENDOR_ID_HP, 0x0700)
  5927. },
  5928. {
  5929. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5930. PCI_VENDOR_ID_HP, 0x0701)
  5931. },
  5932. {
  5933. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5934. PCI_VENDOR_ID_HP, 0x1001)
  5935. },
  5936. {
  5937. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5938. PCI_VENDOR_ID_HP, 0x1100)
  5939. },
  5940. {
  5941. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5942. PCI_VENDOR_ID_HP, 0x1101)
  5943. },
  5944. {
  5945. PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x028f,
  5946. PCI_ANY_ID, PCI_ANY_ID)
  5947. },
  5948. { 0 }
  5949. };
  5950. MODULE_DEVICE_TABLE(pci, pqi_pci_id_table);
  5951. static struct pci_driver pqi_pci_driver = {
  5952. .name = DRIVER_NAME_SHORT,
  5953. .id_table = pqi_pci_id_table,
  5954. .probe = pqi_pci_probe,
  5955. .remove = pqi_pci_remove,
  5956. .shutdown = pqi_shutdown,
  5957. #if defined(CONFIG_PM)
  5958. .suspend = pqi_suspend,
  5959. .resume = pqi_resume,
  5960. #endif
  5961. };
  5962. static int __init pqi_init(void)
  5963. {
  5964. int rc;
  5965. pr_info(DRIVER_NAME "\n");
  5966. pqi_sas_transport_template =
  5967. sas_attach_transport(&pqi_sas_transport_functions);
  5968. if (!pqi_sas_transport_template)
  5969. return -ENODEV;
  5970. pqi_process_module_params();
  5971. rc = pci_register_driver(&pqi_pci_driver);
  5972. if (rc)
  5973. sas_release_transport(pqi_sas_transport_template);
  5974. return rc;
  5975. }
  5976. static void __exit pqi_cleanup(void)
  5977. {
  5978. pci_unregister_driver(&pqi_pci_driver);
  5979. sas_release_transport(pqi_sas_transport_template);
  5980. }
  5981. module_init(pqi_init);
  5982. module_exit(pqi_cleanup);
  5983. static void __attribute__((unused)) verify_structures(void)
  5984. {
  5985. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  5986. sis_host_to_ctrl_doorbell) != 0x20);
  5987. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  5988. sis_interrupt_mask) != 0x34);
  5989. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  5990. sis_ctrl_to_host_doorbell) != 0x9c);
  5991. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  5992. sis_ctrl_to_host_doorbell_clear) != 0xa0);
  5993. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  5994. sis_driver_scratch) != 0xb0);
  5995. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  5996. sis_firmware_status) != 0xbc);
  5997. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  5998. sis_mailbox) != 0x1000);
  5999. BUILD_BUG_ON(offsetof(struct pqi_ctrl_registers,
  6000. pqi_registers) != 0x4000);
  6001. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  6002. iu_type) != 0x0);
  6003. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  6004. iu_length) != 0x2);
  6005. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  6006. response_queue_id) != 0x4);
  6007. BUILD_BUG_ON(offsetof(struct pqi_iu_header,
  6008. work_area) != 0x6);
  6009. BUILD_BUG_ON(sizeof(struct pqi_iu_header) != 0x8);
  6010. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  6011. status) != 0x0);
  6012. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  6013. service_response) != 0x1);
  6014. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  6015. data_present) != 0x2);
  6016. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  6017. reserved) != 0x3);
  6018. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  6019. residual_count) != 0x4);
  6020. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  6021. data_length) != 0x8);
  6022. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  6023. reserved1) != 0xa);
  6024. BUILD_BUG_ON(offsetof(struct pqi_aio_error_info,
  6025. data) != 0xc);
  6026. BUILD_BUG_ON(sizeof(struct pqi_aio_error_info) != 0x10c);
  6027. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6028. data_in_result) != 0x0);
  6029. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6030. data_out_result) != 0x1);
  6031. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6032. reserved) != 0x2);
  6033. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6034. status) != 0x5);
  6035. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6036. status_qualifier) != 0x6);
  6037. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6038. sense_data_length) != 0x8);
  6039. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6040. response_data_length) != 0xa);
  6041. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6042. data_in_transferred) != 0xc);
  6043. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6044. data_out_transferred) != 0x10);
  6045. BUILD_BUG_ON(offsetof(struct pqi_raid_error_info,
  6046. data) != 0x14);
  6047. BUILD_BUG_ON(sizeof(struct pqi_raid_error_info) != 0x114);
  6048. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6049. signature) != 0x0);
  6050. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6051. function_and_status_code) != 0x8);
  6052. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6053. max_admin_iq_elements) != 0x10);
  6054. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6055. max_admin_oq_elements) != 0x11);
  6056. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6057. admin_iq_element_length) != 0x12);
  6058. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6059. admin_oq_element_length) != 0x13);
  6060. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6061. max_reset_timeout) != 0x14);
  6062. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6063. legacy_intx_status) != 0x18);
  6064. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6065. legacy_intx_mask_set) != 0x1c);
  6066. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6067. legacy_intx_mask_clear) != 0x20);
  6068. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6069. device_status) != 0x40);
  6070. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6071. admin_iq_pi_offset) != 0x48);
  6072. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6073. admin_oq_ci_offset) != 0x50);
  6074. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6075. admin_iq_element_array_addr) != 0x58);
  6076. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6077. admin_oq_element_array_addr) != 0x60);
  6078. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6079. admin_iq_ci_addr) != 0x68);
  6080. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6081. admin_oq_pi_addr) != 0x70);
  6082. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6083. admin_iq_num_elements) != 0x78);
  6084. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6085. admin_oq_num_elements) != 0x79);
  6086. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6087. admin_queue_int_msg_num) != 0x7a);
  6088. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6089. device_error) != 0x80);
  6090. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6091. error_details) != 0x88);
  6092. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6093. device_reset) != 0x90);
  6094. BUILD_BUG_ON(offsetof(struct pqi_device_registers,
  6095. power_action) != 0x94);
  6096. BUILD_BUG_ON(sizeof(struct pqi_device_registers) != 0x100);
  6097. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6098. header.iu_type) != 0);
  6099. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6100. header.iu_length) != 2);
  6101. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6102. header.work_area) != 6);
  6103. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6104. request_id) != 8);
  6105. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6106. function_code) != 10);
  6107. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6108. data.report_device_capability.buffer_length) != 44);
  6109. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6110. data.report_device_capability.sg_descriptor) != 48);
  6111. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6112. data.create_operational_iq.queue_id) != 12);
  6113. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6114. data.create_operational_iq.element_array_addr) != 16);
  6115. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6116. data.create_operational_iq.ci_addr) != 24);
  6117. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6118. data.create_operational_iq.num_elements) != 32);
  6119. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6120. data.create_operational_iq.element_length) != 34);
  6121. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6122. data.create_operational_iq.queue_protocol) != 36);
  6123. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6124. data.create_operational_oq.queue_id) != 12);
  6125. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6126. data.create_operational_oq.element_array_addr) != 16);
  6127. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6128. data.create_operational_oq.pi_addr) != 24);
  6129. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6130. data.create_operational_oq.num_elements) != 32);
  6131. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6132. data.create_operational_oq.element_length) != 34);
  6133. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6134. data.create_operational_oq.queue_protocol) != 36);
  6135. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6136. data.create_operational_oq.int_msg_num) != 40);
  6137. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6138. data.create_operational_oq.coalescing_count) != 42);
  6139. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6140. data.create_operational_oq.min_coalescing_time) != 44);
  6141. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6142. data.create_operational_oq.max_coalescing_time) != 48);
  6143. BUILD_BUG_ON(offsetof(struct pqi_general_admin_request,
  6144. data.delete_operational_queue.queue_id) != 12);
  6145. BUILD_BUG_ON(sizeof(struct pqi_general_admin_request) != 64);
  6146. BUILD_BUG_ON(FIELD_SIZEOF(struct pqi_general_admin_request,
  6147. data.create_operational_iq) != 64 - 11);
  6148. BUILD_BUG_ON(FIELD_SIZEOF(struct pqi_general_admin_request,
  6149. data.create_operational_oq) != 64 - 11);
  6150. BUILD_BUG_ON(FIELD_SIZEOF(struct pqi_general_admin_request,
  6151. data.delete_operational_queue) != 64 - 11);
  6152. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6153. header.iu_type) != 0);
  6154. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6155. header.iu_length) != 2);
  6156. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6157. header.work_area) != 6);
  6158. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6159. request_id) != 8);
  6160. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6161. function_code) != 10);
  6162. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6163. status) != 11);
  6164. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6165. data.create_operational_iq.status_descriptor) != 12);
  6166. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6167. data.create_operational_iq.iq_pi_offset) != 16);
  6168. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6169. data.create_operational_oq.status_descriptor) != 12);
  6170. BUILD_BUG_ON(offsetof(struct pqi_general_admin_response,
  6171. data.create_operational_oq.oq_ci_offset) != 16);
  6172. BUILD_BUG_ON(sizeof(struct pqi_general_admin_response) != 64);
  6173. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6174. header.iu_type) != 0);
  6175. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6176. header.iu_length) != 2);
  6177. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6178. header.response_queue_id) != 4);
  6179. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6180. header.work_area) != 6);
  6181. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6182. request_id) != 8);
  6183. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6184. nexus_id) != 10);
  6185. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6186. buffer_length) != 12);
  6187. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6188. lun_number) != 16);
  6189. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6190. protocol_specific) != 24);
  6191. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6192. error_index) != 27);
  6193. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6194. cdb) != 32);
  6195. BUILD_BUG_ON(offsetof(struct pqi_raid_path_request,
  6196. sg_descriptors) != 64);
  6197. BUILD_BUG_ON(sizeof(struct pqi_raid_path_request) !=
  6198. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  6199. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6200. header.iu_type) != 0);
  6201. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6202. header.iu_length) != 2);
  6203. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6204. header.response_queue_id) != 4);
  6205. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6206. header.work_area) != 6);
  6207. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6208. request_id) != 8);
  6209. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6210. nexus_id) != 12);
  6211. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6212. buffer_length) != 16);
  6213. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6214. data_encryption_key_index) != 22);
  6215. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6216. encrypt_tweak_lower) != 24);
  6217. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6218. encrypt_tweak_upper) != 28);
  6219. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6220. cdb) != 32);
  6221. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6222. error_index) != 48);
  6223. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6224. num_sg_descriptors) != 50);
  6225. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6226. cdb_length) != 51);
  6227. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6228. lun_number) != 52);
  6229. BUILD_BUG_ON(offsetof(struct pqi_aio_path_request,
  6230. sg_descriptors) != 64);
  6231. BUILD_BUG_ON(sizeof(struct pqi_aio_path_request) !=
  6232. PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
  6233. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  6234. header.iu_type) != 0);
  6235. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  6236. header.iu_length) != 2);
  6237. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  6238. request_id) != 8);
  6239. BUILD_BUG_ON(offsetof(struct pqi_io_response,
  6240. error_index) != 10);
  6241. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  6242. header.iu_type) != 0);
  6243. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  6244. header.iu_length) != 2);
  6245. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  6246. header.response_queue_id) != 4);
  6247. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  6248. request_id) != 8);
  6249. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  6250. data.report_event_configuration.buffer_length) != 12);
  6251. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  6252. data.report_event_configuration.sg_descriptors) != 16);
  6253. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  6254. data.set_event_configuration.global_event_oq_id) != 10);
  6255. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  6256. data.set_event_configuration.buffer_length) != 12);
  6257. BUILD_BUG_ON(offsetof(struct pqi_general_management_request,
  6258. data.set_event_configuration.sg_descriptors) != 16);
  6259. BUILD_BUG_ON(offsetof(struct pqi_iu_layer_descriptor,
  6260. max_inbound_iu_length) != 6);
  6261. BUILD_BUG_ON(offsetof(struct pqi_iu_layer_descriptor,
  6262. max_outbound_iu_length) != 14);
  6263. BUILD_BUG_ON(sizeof(struct pqi_iu_layer_descriptor) != 16);
  6264. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6265. data_length) != 0);
  6266. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6267. iq_arbitration_priority_support_bitmask) != 8);
  6268. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6269. maximum_aw_a) != 9);
  6270. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6271. maximum_aw_b) != 10);
  6272. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6273. maximum_aw_c) != 11);
  6274. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6275. max_inbound_queues) != 16);
  6276. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6277. max_elements_per_iq) != 18);
  6278. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6279. max_iq_element_length) != 24);
  6280. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6281. min_iq_element_length) != 26);
  6282. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6283. max_outbound_queues) != 30);
  6284. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6285. max_elements_per_oq) != 32);
  6286. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6287. intr_coalescing_time_granularity) != 34);
  6288. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6289. max_oq_element_length) != 36);
  6290. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6291. min_oq_element_length) != 38);
  6292. BUILD_BUG_ON(offsetof(struct pqi_device_capability,
  6293. iu_layer_descriptors) != 64);
  6294. BUILD_BUG_ON(sizeof(struct pqi_device_capability) != 576);
  6295. BUILD_BUG_ON(offsetof(struct pqi_event_descriptor,
  6296. event_type) != 0);
  6297. BUILD_BUG_ON(offsetof(struct pqi_event_descriptor,
  6298. oq_id) != 2);
  6299. BUILD_BUG_ON(sizeof(struct pqi_event_descriptor) != 4);
  6300. BUILD_BUG_ON(offsetof(struct pqi_event_config,
  6301. num_event_descriptors) != 2);
  6302. BUILD_BUG_ON(offsetof(struct pqi_event_config,
  6303. descriptors) != 4);
  6304. BUILD_BUG_ON(PQI_NUM_SUPPORTED_EVENTS !=
  6305. ARRAY_SIZE(pqi_supported_event_types));
  6306. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  6307. header.iu_type) != 0);
  6308. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  6309. header.iu_length) != 2);
  6310. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  6311. event_type) != 8);
  6312. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  6313. event_id) != 10);
  6314. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  6315. additional_event_id) != 12);
  6316. BUILD_BUG_ON(offsetof(struct pqi_event_response,
  6317. data) != 16);
  6318. BUILD_BUG_ON(sizeof(struct pqi_event_response) != 32);
  6319. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  6320. header.iu_type) != 0);
  6321. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  6322. header.iu_length) != 2);
  6323. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  6324. event_type) != 8);
  6325. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  6326. event_id) != 10);
  6327. BUILD_BUG_ON(offsetof(struct pqi_event_acknowledge_request,
  6328. additional_event_id) != 12);
  6329. BUILD_BUG_ON(sizeof(struct pqi_event_acknowledge_request) != 16);
  6330. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  6331. header.iu_type) != 0);
  6332. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  6333. header.iu_length) != 2);
  6334. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  6335. request_id) != 8);
  6336. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  6337. nexus_id) != 10);
  6338. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  6339. lun_number) != 16);
  6340. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  6341. protocol_specific) != 24);
  6342. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  6343. outbound_queue_id_to_manage) != 26);
  6344. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  6345. request_id_to_manage) != 28);
  6346. BUILD_BUG_ON(offsetof(struct pqi_task_management_request,
  6347. task_management_function) != 30);
  6348. BUILD_BUG_ON(sizeof(struct pqi_task_management_request) != 32);
  6349. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  6350. header.iu_type) != 0);
  6351. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  6352. header.iu_length) != 2);
  6353. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  6354. request_id) != 8);
  6355. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  6356. nexus_id) != 10);
  6357. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  6358. additional_response_info) != 12);
  6359. BUILD_BUG_ON(offsetof(struct pqi_task_management_response,
  6360. response_code) != 15);
  6361. BUILD_BUG_ON(sizeof(struct pqi_task_management_response) != 16);
  6362. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  6363. configured_logical_drive_count) != 0);
  6364. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  6365. configuration_signature) != 1);
  6366. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  6367. firmware_version) != 5);
  6368. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  6369. extended_logical_unit_count) != 154);
  6370. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  6371. firmware_build_number) != 190);
  6372. BUILD_BUG_ON(offsetof(struct bmic_identify_controller,
  6373. controller_mode) != 292);
  6374. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  6375. phys_bay_in_box) != 115);
  6376. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  6377. device_type) != 120);
  6378. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  6379. redundant_path_present_map) != 1736);
  6380. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  6381. active_path_number) != 1738);
  6382. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  6383. alternate_paths_phys_connector) != 1739);
  6384. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  6385. alternate_paths_phys_box_on_port) != 1755);
  6386. BUILD_BUG_ON(offsetof(struct bmic_identify_physical_device,
  6387. current_queue_depth_limit) != 1796);
  6388. BUILD_BUG_ON(sizeof(struct bmic_identify_physical_device) != 2560);
  6389. BUILD_BUG_ON(PQI_ADMIN_IQ_NUM_ELEMENTS > 255);
  6390. BUILD_BUG_ON(PQI_ADMIN_OQ_NUM_ELEMENTS > 255);
  6391. BUILD_BUG_ON(PQI_ADMIN_IQ_ELEMENT_LENGTH %
  6392. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  6393. BUILD_BUG_ON(PQI_ADMIN_OQ_ELEMENT_LENGTH %
  6394. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  6395. BUILD_BUG_ON(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH > 1048560);
  6396. BUILD_BUG_ON(PQI_OPERATIONAL_IQ_ELEMENT_LENGTH %
  6397. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  6398. BUILD_BUG_ON(PQI_OPERATIONAL_OQ_ELEMENT_LENGTH > 1048560);
  6399. BUILD_BUG_ON(PQI_OPERATIONAL_OQ_ELEMENT_LENGTH %
  6400. PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT != 0);
  6401. BUILD_BUG_ON(PQI_RESERVED_IO_SLOTS >= PQI_MAX_OUTSTANDING_REQUESTS);
  6402. BUILD_BUG_ON(PQI_RESERVED_IO_SLOTS >=
  6403. PQI_MAX_OUTSTANDING_REQUESTS_KDUMP);
  6404. }