core.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * core.c - DesignWare USB3 DRD Controller Core file
  4. *
  5. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/version.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/slab.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/ioport.h>
  20. #include <linux/io.h>
  21. #include <linux/list.h>
  22. #include <linux/delay.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/of.h>
  25. #include <linux/acpi.h>
  26. #include <linux/pinctrl/consumer.h>
  27. #include <linux/reset.h>
  28. #include <linux/usb/ch9.h>
  29. #include <linux/usb/gadget.h>
  30. #include <linux/usb/of.h>
  31. #include <linux/usb/otg.h>
  32. #include "core.h"
  33. #include "gadget.h"
  34. #include "io.h"
  35. #include "debug.h"
  36. #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
  37. /**
  38. * dwc3_get_dr_mode - Validates and sets dr_mode
  39. * @dwc: pointer to our context structure
  40. */
  41. static int dwc3_get_dr_mode(struct dwc3 *dwc)
  42. {
  43. enum usb_dr_mode mode;
  44. struct device *dev = dwc->dev;
  45. unsigned int hw_mode;
  46. if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  47. dwc->dr_mode = USB_DR_MODE_OTG;
  48. mode = dwc->dr_mode;
  49. hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  50. switch (hw_mode) {
  51. case DWC3_GHWPARAMS0_MODE_GADGET:
  52. if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  53. dev_err(dev,
  54. "Controller does not support host mode.\n");
  55. return -EINVAL;
  56. }
  57. mode = USB_DR_MODE_PERIPHERAL;
  58. break;
  59. case DWC3_GHWPARAMS0_MODE_HOST:
  60. if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  61. dev_err(dev,
  62. "Controller does not support device mode.\n");
  63. return -EINVAL;
  64. }
  65. mode = USB_DR_MODE_HOST;
  66. break;
  67. default:
  68. if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  69. mode = USB_DR_MODE_HOST;
  70. else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  71. mode = USB_DR_MODE_PERIPHERAL;
  72. /*
  73. * dwc_usb31 does not support OTG mode. If the controller
  74. * supports DRD but the dr_mode is not specified or set to OTG,
  75. * then set the mode to peripheral.
  76. */
  77. if (mode == USB_DR_MODE_OTG && dwc3_is_usb31(dwc))
  78. mode = USB_DR_MODE_PERIPHERAL;
  79. }
  80. if (mode != dwc->dr_mode) {
  81. dev_warn(dev,
  82. "Configuration mismatch. dr_mode forced to %s\n",
  83. mode == USB_DR_MODE_HOST ? "host" : "gadget");
  84. dwc->dr_mode = mode;
  85. }
  86. return 0;
  87. }
  88. void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
  89. {
  90. u32 reg;
  91. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  92. reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  93. reg |= DWC3_GCTL_PRTCAPDIR(mode);
  94. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  95. dwc->current_dr_role = mode;
  96. }
  97. static void __dwc3_set_mode(struct work_struct *work)
  98. {
  99. struct dwc3 *dwc = work_to_dwc(work);
  100. unsigned long flags;
  101. int ret;
  102. if (dwc->dr_mode != USB_DR_MODE_OTG)
  103. return;
  104. if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
  105. dwc3_otg_update(dwc, 0);
  106. if (!dwc->desired_dr_role)
  107. return;
  108. if (dwc->desired_dr_role == dwc->current_dr_role)
  109. return;
  110. if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
  111. return;
  112. switch (dwc->current_dr_role) {
  113. case DWC3_GCTL_PRTCAP_HOST:
  114. dwc3_host_exit(dwc);
  115. break;
  116. case DWC3_GCTL_PRTCAP_DEVICE:
  117. dwc3_gadget_exit(dwc);
  118. dwc3_event_buffers_cleanup(dwc);
  119. break;
  120. case DWC3_GCTL_PRTCAP_OTG:
  121. dwc3_otg_exit(dwc);
  122. spin_lock_irqsave(&dwc->lock, flags);
  123. dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
  124. spin_unlock_irqrestore(&dwc->lock, flags);
  125. dwc3_otg_update(dwc, 1);
  126. break;
  127. default:
  128. break;
  129. }
  130. spin_lock_irqsave(&dwc->lock, flags);
  131. dwc3_set_prtcap(dwc, dwc->desired_dr_role);
  132. spin_unlock_irqrestore(&dwc->lock, flags);
  133. switch (dwc->desired_dr_role) {
  134. case DWC3_GCTL_PRTCAP_HOST:
  135. ret = dwc3_host_init(dwc);
  136. if (ret) {
  137. dev_err(dwc->dev, "failed to initialize host\n");
  138. } else {
  139. if (dwc->usb2_phy)
  140. otg_set_vbus(dwc->usb2_phy->otg, true);
  141. phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
  142. phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
  143. phy_calibrate(dwc->usb2_generic_phy);
  144. }
  145. break;
  146. case DWC3_GCTL_PRTCAP_DEVICE:
  147. dwc3_event_buffers_setup(dwc);
  148. if (dwc->usb2_phy)
  149. otg_set_vbus(dwc->usb2_phy->otg, false);
  150. phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
  151. phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
  152. ret = dwc3_gadget_init(dwc);
  153. if (ret)
  154. dev_err(dwc->dev, "failed to initialize peripheral\n");
  155. break;
  156. case DWC3_GCTL_PRTCAP_OTG:
  157. dwc3_otg_init(dwc);
  158. dwc3_otg_update(dwc, 0);
  159. break;
  160. default:
  161. break;
  162. }
  163. }
  164. void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  165. {
  166. unsigned long flags;
  167. spin_lock_irqsave(&dwc->lock, flags);
  168. dwc->desired_dr_role = mode;
  169. spin_unlock_irqrestore(&dwc->lock, flags);
  170. queue_work(system_freezable_wq, &dwc->drd_work);
  171. }
  172. u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
  173. {
  174. struct dwc3 *dwc = dep->dwc;
  175. u32 reg;
  176. dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
  177. DWC3_GDBGFIFOSPACE_NUM(dep->number) |
  178. DWC3_GDBGFIFOSPACE_TYPE(type));
  179. reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
  180. return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
  181. }
  182. /**
  183. * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  184. * @dwc: pointer to our context structure
  185. */
  186. static int dwc3_core_soft_reset(struct dwc3 *dwc)
  187. {
  188. u32 reg;
  189. int retries = 1000;
  190. int ret;
  191. usb_phy_init(dwc->usb2_phy);
  192. usb_phy_init(dwc->usb3_phy);
  193. ret = phy_init(dwc->usb2_generic_phy);
  194. if (ret < 0)
  195. return ret;
  196. ret = phy_init(dwc->usb3_generic_phy);
  197. if (ret < 0) {
  198. phy_exit(dwc->usb2_generic_phy);
  199. return ret;
  200. }
  201. /*
  202. * We're resetting only the device side because, if we're in host mode,
  203. * XHCI driver will reset the host block. If dwc3 was configured for
  204. * host-only mode, then we can return early.
  205. */
  206. if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
  207. return 0;
  208. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  209. reg |= DWC3_DCTL_CSFTRST;
  210. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  211. do {
  212. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  213. if (!(reg & DWC3_DCTL_CSFTRST))
  214. goto done;
  215. udelay(1);
  216. } while (--retries);
  217. phy_exit(dwc->usb3_generic_phy);
  218. phy_exit(dwc->usb2_generic_phy);
  219. return -ETIMEDOUT;
  220. done:
  221. /*
  222. * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
  223. * we must wait at least 50ms before accessing the PHY domain
  224. * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
  225. */
  226. if (dwc3_is_usb31(dwc))
  227. msleep(50);
  228. return 0;
  229. }
  230. static const struct clk_bulk_data dwc3_core_clks[] = {
  231. { .id = "ref" },
  232. { .id = "bus_early" },
  233. { .id = "suspend" },
  234. };
  235. /*
  236. * dwc3_frame_length_adjustment - Adjusts frame length if required
  237. * @dwc3: Pointer to our controller context structure
  238. */
  239. static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
  240. {
  241. u32 reg;
  242. u32 dft;
  243. if (dwc->revision < DWC3_REVISION_250A)
  244. return;
  245. if (dwc->fladj == 0)
  246. return;
  247. reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
  248. dft = reg & DWC3_GFLADJ_30MHZ_MASK;
  249. if (dft != dwc->fladj) {
  250. reg &= ~DWC3_GFLADJ_30MHZ_MASK;
  251. reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
  252. dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
  253. }
  254. }
  255. /**
  256. * dwc3_free_one_event_buffer - Frees one event buffer
  257. * @dwc: Pointer to our controller context structure
  258. * @evt: Pointer to event buffer to be freed
  259. */
  260. static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  261. struct dwc3_event_buffer *evt)
  262. {
  263. dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
  264. }
  265. /**
  266. * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
  267. * @dwc: Pointer to our controller context structure
  268. * @length: size of the event buffer
  269. *
  270. * Returns a pointer to the allocated event buffer structure on success
  271. * otherwise ERR_PTR(errno).
  272. */
  273. static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
  274. unsigned length)
  275. {
  276. struct dwc3_event_buffer *evt;
  277. evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
  278. if (!evt)
  279. return ERR_PTR(-ENOMEM);
  280. evt->dwc = dwc;
  281. evt->length = length;
  282. evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
  283. if (!evt->cache)
  284. return ERR_PTR(-ENOMEM);
  285. evt->buf = dma_alloc_coherent(dwc->sysdev, length,
  286. &evt->dma, GFP_KERNEL);
  287. if (!evt->buf)
  288. return ERR_PTR(-ENOMEM);
  289. return evt;
  290. }
  291. /**
  292. * dwc3_free_event_buffers - frees all allocated event buffers
  293. * @dwc: Pointer to our controller context structure
  294. */
  295. static void dwc3_free_event_buffers(struct dwc3 *dwc)
  296. {
  297. struct dwc3_event_buffer *evt;
  298. evt = dwc->ev_buf;
  299. if (evt)
  300. dwc3_free_one_event_buffer(dwc, evt);
  301. }
  302. /**
  303. * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
  304. * @dwc: pointer to our controller context structure
  305. * @length: size of event buffer
  306. *
  307. * Returns 0 on success otherwise negative errno. In the error case, dwc
  308. * may contain some buffers allocated but not all which were requested.
  309. */
  310. static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  311. {
  312. struct dwc3_event_buffer *evt;
  313. evt = dwc3_alloc_one_event_buffer(dwc, length);
  314. if (IS_ERR(evt)) {
  315. dev_err(dwc->dev, "can't allocate event buffer\n");
  316. return PTR_ERR(evt);
  317. }
  318. dwc->ev_buf = evt;
  319. return 0;
  320. }
  321. /**
  322. * dwc3_event_buffers_setup - setup our allocated event buffers
  323. * @dwc: pointer to our controller context structure
  324. *
  325. * Returns 0 on success otherwise negative errno.
  326. */
  327. int dwc3_event_buffers_setup(struct dwc3 *dwc)
  328. {
  329. struct dwc3_event_buffer *evt;
  330. evt = dwc->ev_buf;
  331. evt->lpos = 0;
  332. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
  333. lower_32_bits(evt->dma));
  334. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
  335. upper_32_bits(evt->dma));
  336. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
  337. DWC3_GEVNTSIZ_SIZE(evt->length));
  338. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
  339. return 0;
  340. }
  341. void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  342. {
  343. struct dwc3_event_buffer *evt;
  344. evt = dwc->ev_buf;
  345. evt->lpos = 0;
  346. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
  347. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
  348. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
  349. | DWC3_GEVNTSIZ_SIZE(0));
  350. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
  351. }
  352. static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
  353. {
  354. if (!dwc->has_hibernation)
  355. return 0;
  356. if (!dwc->nr_scratch)
  357. return 0;
  358. dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
  359. DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
  360. if (!dwc->scratchbuf)
  361. return -ENOMEM;
  362. return 0;
  363. }
  364. static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
  365. {
  366. dma_addr_t scratch_addr;
  367. u32 param;
  368. int ret;
  369. if (!dwc->has_hibernation)
  370. return 0;
  371. if (!dwc->nr_scratch)
  372. return 0;
  373. /* should never fall here */
  374. if (!WARN_ON(dwc->scratchbuf))
  375. return 0;
  376. scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
  377. dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  378. DMA_BIDIRECTIONAL);
  379. if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
  380. dev_err(dwc->sysdev, "failed to map scratch buffer\n");
  381. ret = -EFAULT;
  382. goto err0;
  383. }
  384. dwc->scratch_addr = scratch_addr;
  385. param = lower_32_bits(scratch_addr);
  386. ret = dwc3_send_gadget_generic_command(dwc,
  387. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
  388. if (ret < 0)
  389. goto err1;
  390. param = upper_32_bits(scratch_addr);
  391. ret = dwc3_send_gadget_generic_command(dwc,
  392. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
  393. if (ret < 0)
  394. goto err1;
  395. return 0;
  396. err1:
  397. dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
  398. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  399. err0:
  400. return ret;
  401. }
  402. static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
  403. {
  404. if (!dwc->has_hibernation)
  405. return;
  406. if (!dwc->nr_scratch)
  407. return;
  408. /* should never fall here */
  409. if (!WARN_ON(dwc->scratchbuf))
  410. return;
  411. dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
  412. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  413. kfree(dwc->scratchbuf);
  414. }
  415. static void dwc3_core_num_eps(struct dwc3 *dwc)
  416. {
  417. struct dwc3_hwparams *parms = &dwc->hwparams;
  418. dwc->num_eps = DWC3_NUM_EPS(parms);
  419. }
  420. static void dwc3_cache_hwparams(struct dwc3 *dwc)
  421. {
  422. struct dwc3_hwparams *parms = &dwc->hwparams;
  423. parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  424. parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  425. parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  426. parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  427. parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  428. parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  429. parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  430. parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  431. parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  432. }
  433. static int dwc3_core_ulpi_init(struct dwc3 *dwc)
  434. {
  435. int intf;
  436. int ret = 0;
  437. intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
  438. if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
  439. (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
  440. dwc->hsphy_interface &&
  441. !strncmp(dwc->hsphy_interface, "ulpi", 4)))
  442. ret = dwc3_ulpi_init(dwc);
  443. return ret;
  444. }
  445. /**
  446. * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  447. * @dwc: Pointer to our controller context structure
  448. *
  449. * Returns 0 on success. The USB PHY interfaces are configured but not
  450. * initialized. The PHY interfaces and the PHYs get initialized together with
  451. * the core in dwc3_core_init.
  452. */
  453. static int dwc3_phy_setup(struct dwc3 *dwc)
  454. {
  455. u32 reg;
  456. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  457. /*
  458. * Make sure UX_EXIT_PX is cleared as that causes issues with some
  459. * PHYs. Also, this bit is not supposed to be used in normal operation.
  460. */
  461. reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
  462. /*
  463. * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
  464. * to '0' during coreConsultant configuration. So default value
  465. * will be '0' when the core is reset. Application needs to set it
  466. * to '1' after the core initialization is completed.
  467. */
  468. if (dwc->revision > DWC3_REVISION_194A)
  469. reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  470. if (dwc->u2ss_inp3_quirk)
  471. reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
  472. if (dwc->dis_rxdet_inp3_quirk)
  473. reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
  474. if (dwc->req_p1p2p3_quirk)
  475. reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
  476. if (dwc->del_p1p2p3_quirk)
  477. reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
  478. if (dwc->del_phy_power_chg_quirk)
  479. reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
  480. if (dwc->lfps_filter_quirk)
  481. reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
  482. if (dwc->rx_detect_poll_quirk)
  483. reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
  484. if (dwc->tx_de_emphasis_quirk)
  485. reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
  486. if (dwc->dis_u3_susphy_quirk)
  487. reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  488. if (dwc->dis_del_phy_power_chg_quirk)
  489. reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
  490. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  491. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  492. /* Select the HS PHY interface */
  493. switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
  494. case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
  495. if (dwc->hsphy_interface &&
  496. !strncmp(dwc->hsphy_interface, "utmi", 4)) {
  497. reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
  498. break;
  499. } else if (dwc->hsphy_interface &&
  500. !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
  501. reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
  502. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  503. } else {
  504. /* Relying on default value. */
  505. if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
  506. break;
  507. }
  508. /* FALLTHROUGH */
  509. case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
  510. /* FALLTHROUGH */
  511. default:
  512. break;
  513. }
  514. switch (dwc->hsphy_mode) {
  515. case USBPHY_INTERFACE_MODE_UTMI:
  516. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  517. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  518. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
  519. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
  520. break;
  521. case USBPHY_INTERFACE_MODE_UTMIW:
  522. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  523. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  524. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
  525. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
  526. break;
  527. default:
  528. break;
  529. }
  530. /*
  531. * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
  532. * '0' during coreConsultant configuration. So default value will
  533. * be '0' when the core is reset. Application needs to set it to
  534. * '1' after the core initialization is completed.
  535. */
  536. if (dwc->revision > DWC3_REVISION_194A)
  537. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  538. if (dwc->dis_u2_susphy_quirk)
  539. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  540. if (dwc->dis_enblslpm_quirk)
  541. reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  542. if (dwc->dis_u2_freeclk_exists_quirk)
  543. reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  544. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  545. return 0;
  546. }
  547. static void dwc3_core_exit(struct dwc3 *dwc)
  548. {
  549. dwc3_event_buffers_cleanup(dwc);
  550. usb_phy_shutdown(dwc->usb2_phy);
  551. usb_phy_shutdown(dwc->usb3_phy);
  552. phy_exit(dwc->usb2_generic_phy);
  553. phy_exit(dwc->usb3_generic_phy);
  554. usb_phy_set_suspend(dwc->usb2_phy, 1);
  555. usb_phy_set_suspend(dwc->usb3_phy, 1);
  556. phy_power_off(dwc->usb2_generic_phy);
  557. phy_power_off(dwc->usb3_generic_phy);
  558. clk_bulk_disable(dwc->num_clks, dwc->clks);
  559. clk_bulk_unprepare(dwc->num_clks, dwc->clks);
  560. reset_control_assert(dwc->reset);
  561. }
  562. static bool dwc3_core_is_valid(struct dwc3 *dwc)
  563. {
  564. u32 reg;
  565. reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  566. /* This should read as U3 followed by revision number */
  567. if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
  568. /* Detected DWC_usb3 IP */
  569. dwc->revision = reg;
  570. } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
  571. /* Detected DWC_usb31 IP */
  572. dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
  573. dwc->revision |= DWC3_REVISION_IS_DWC31;
  574. } else {
  575. return false;
  576. }
  577. return true;
  578. }
  579. static void dwc3_core_setup_global_control(struct dwc3 *dwc)
  580. {
  581. u32 hwparams4 = dwc->hwparams.hwparams4;
  582. u32 reg;
  583. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  584. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  585. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
  586. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  587. /**
  588. * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
  589. * issue which would cause xHCI compliance tests to fail.
  590. *
  591. * Because of that we cannot enable clock gating on such
  592. * configurations.
  593. *
  594. * Refers to:
  595. *
  596. * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
  597. * SOF/ITP Mode Used
  598. */
  599. if ((dwc->dr_mode == USB_DR_MODE_HOST ||
  600. dwc->dr_mode == USB_DR_MODE_OTG) &&
  601. (dwc->revision >= DWC3_REVISION_210A &&
  602. dwc->revision <= DWC3_REVISION_250A))
  603. reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
  604. else
  605. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  606. break;
  607. case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
  608. /* enable hibernation here */
  609. dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
  610. /*
  611. * REVISIT Enabling this bit so that host-mode hibernation
  612. * will work. Device-mode hibernation is not yet implemented.
  613. */
  614. reg |= DWC3_GCTL_GBLHIBERNATIONEN;
  615. break;
  616. default:
  617. /* nothing */
  618. break;
  619. }
  620. /* check if current dwc3 is on simulation board */
  621. if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
  622. dev_info(dwc->dev, "Running with FPGA optmizations\n");
  623. dwc->is_fpga = true;
  624. }
  625. WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
  626. "disable_scramble cannot be used on non-FPGA builds\n");
  627. if (dwc->disable_scramble_quirk && dwc->is_fpga)
  628. reg |= DWC3_GCTL_DISSCRAMBLE;
  629. else
  630. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  631. if (dwc->u2exit_lfps_quirk)
  632. reg |= DWC3_GCTL_U2EXIT_LFPS;
  633. /*
  634. * WORKAROUND: DWC3 revisions <1.90a have a bug
  635. * where the device can fail to connect at SuperSpeed
  636. * and falls back to high-speed mode which causes
  637. * the device to enter a Connect/Disconnect loop
  638. */
  639. if (dwc->revision < DWC3_REVISION_190A)
  640. reg |= DWC3_GCTL_U2RSTECN;
  641. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  642. }
  643. static int dwc3_core_get_phy(struct dwc3 *dwc);
  644. static int dwc3_core_ulpi_init(struct dwc3 *dwc);
  645. /* set global incr burst type configuration registers */
  646. static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
  647. {
  648. struct device *dev = dwc->dev;
  649. /* incrx_mode : for INCR burst type. */
  650. bool incrx_mode;
  651. /* incrx_size : for size of INCRX burst. */
  652. u32 incrx_size;
  653. u32 *vals;
  654. u32 cfg;
  655. int ntype;
  656. int ret;
  657. int i;
  658. cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
  659. /*
  660. * Handle property "snps,incr-burst-type-adjustment".
  661. * Get the number of value from this property:
  662. * result <= 0, means this property is not supported.
  663. * result = 1, means INCRx burst mode supported.
  664. * result > 1, means undefined length burst mode supported.
  665. */
  666. ntype = device_property_read_u32_array(dev,
  667. "snps,incr-burst-type-adjustment", NULL, 0);
  668. if (ntype <= 0)
  669. return;
  670. vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
  671. if (!vals) {
  672. dev_err(dev, "Error to get memory\n");
  673. return;
  674. }
  675. /* Get INCR burst type, and parse it */
  676. ret = device_property_read_u32_array(dev,
  677. "snps,incr-burst-type-adjustment", vals, ntype);
  678. if (ret) {
  679. dev_err(dev, "Error to get property\n");
  680. return;
  681. }
  682. incrx_size = *vals;
  683. if (ntype > 1) {
  684. /* INCRX (undefined length) burst mode */
  685. incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
  686. for (i = 1; i < ntype; i++) {
  687. if (vals[i] > incrx_size)
  688. incrx_size = vals[i];
  689. }
  690. } else {
  691. /* INCRX burst mode */
  692. incrx_mode = INCRX_BURST_MODE;
  693. }
  694. /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
  695. cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
  696. if (incrx_mode)
  697. cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
  698. switch (incrx_size) {
  699. case 256:
  700. cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
  701. break;
  702. case 128:
  703. cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
  704. break;
  705. case 64:
  706. cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
  707. break;
  708. case 32:
  709. cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
  710. break;
  711. case 16:
  712. cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
  713. break;
  714. case 8:
  715. cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
  716. break;
  717. case 4:
  718. cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
  719. break;
  720. case 1:
  721. break;
  722. default:
  723. dev_err(dev, "Invalid property\n");
  724. break;
  725. }
  726. dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
  727. }
  728. /**
  729. * dwc3_core_init - Low-level initialization of DWC3 Core
  730. * @dwc: Pointer to our controller context structure
  731. *
  732. * Returns 0 on success otherwise negative errno.
  733. */
  734. static int dwc3_core_init(struct dwc3 *dwc)
  735. {
  736. u32 reg;
  737. int ret;
  738. if (!dwc3_core_is_valid(dwc)) {
  739. dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  740. ret = -ENODEV;
  741. goto err0;
  742. }
  743. /*
  744. * Write Linux Version Code to our GUID register so it's easy to figure
  745. * out which kernel version a bug was found.
  746. */
  747. dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
  748. /* Handle USB2.0-only core configuration */
  749. if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  750. DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
  751. if (dwc->maximum_speed == USB_SPEED_SUPER)
  752. dwc->maximum_speed = USB_SPEED_HIGH;
  753. }
  754. ret = dwc3_phy_setup(dwc);
  755. if (ret)
  756. goto err0;
  757. if (!dwc->ulpi_ready) {
  758. ret = dwc3_core_ulpi_init(dwc);
  759. if (ret)
  760. goto err0;
  761. dwc->ulpi_ready = true;
  762. }
  763. if (!dwc->phys_ready) {
  764. ret = dwc3_core_get_phy(dwc);
  765. if (ret)
  766. goto err0a;
  767. dwc->phys_ready = true;
  768. }
  769. ret = dwc3_core_soft_reset(dwc);
  770. if (ret)
  771. goto err0a;
  772. dwc3_core_setup_global_control(dwc);
  773. dwc3_core_num_eps(dwc);
  774. ret = dwc3_setup_scratch_buffers(dwc);
  775. if (ret)
  776. goto err1;
  777. /* Adjust Frame Length */
  778. dwc3_frame_length_adjustment(dwc);
  779. dwc3_set_incr_burst_type(dwc);
  780. usb_phy_set_suspend(dwc->usb2_phy, 0);
  781. usb_phy_set_suspend(dwc->usb3_phy, 0);
  782. ret = phy_power_on(dwc->usb2_generic_phy);
  783. if (ret < 0)
  784. goto err2;
  785. ret = phy_power_on(dwc->usb3_generic_phy);
  786. if (ret < 0)
  787. goto err3;
  788. ret = dwc3_event_buffers_setup(dwc);
  789. if (ret) {
  790. dev_err(dwc->dev, "failed to setup event buffers\n");
  791. goto err4;
  792. }
  793. /*
  794. * ENDXFER polling is available on version 3.10a and later of
  795. * the DWC_usb3 controller. It is NOT available in the
  796. * DWC_usb31 controller.
  797. */
  798. if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
  799. reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
  800. reg |= DWC3_GUCTL2_RST_ACTBITLATER;
  801. dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
  802. }
  803. if (dwc->revision >= DWC3_REVISION_250A) {
  804. reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
  805. /*
  806. * Enable hardware control of sending remote wakeup
  807. * in HS when the device is in the L1 state.
  808. */
  809. if (dwc->revision >= DWC3_REVISION_290A)
  810. reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
  811. if (dwc->dis_tx_ipgap_linecheck_quirk)
  812. reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
  813. if (dwc->parkmode_disable_ss_quirk)
  814. reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
  815. dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
  816. }
  817. if (dwc->dr_mode == USB_DR_MODE_HOST ||
  818. dwc->dr_mode == USB_DR_MODE_OTG) {
  819. reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
  820. /*
  821. * Enable Auto retry Feature to make the controller operating in
  822. * Host mode on seeing transaction errors(CRC errors or internal
  823. * overrun scenerios) on IN transfers to reply to the device
  824. * with a non-terminating retry ACK (i.e, an ACK transcation
  825. * packet with Retry=1 & Nump != 0)
  826. */
  827. reg |= DWC3_GUCTL_HSTINAUTORETRY;
  828. dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
  829. }
  830. /*
  831. * Must config both number of packets and max burst settings to enable
  832. * RX and/or TX threshold.
  833. */
  834. if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
  835. u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
  836. u8 rx_maxburst = dwc->rx_max_burst_prd;
  837. u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
  838. u8 tx_maxburst = dwc->tx_max_burst_prd;
  839. if (rx_thr_num && rx_maxburst) {
  840. reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
  841. reg |= DWC31_RXTHRNUMPKTSEL_PRD;
  842. reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
  843. reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
  844. reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
  845. reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
  846. dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
  847. }
  848. if (tx_thr_num && tx_maxburst) {
  849. reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
  850. reg |= DWC31_TXTHRNUMPKTSEL_PRD;
  851. reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
  852. reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
  853. reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
  854. reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
  855. dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
  856. }
  857. }
  858. return 0;
  859. err4:
  860. phy_power_off(dwc->usb3_generic_phy);
  861. err3:
  862. phy_power_off(dwc->usb2_generic_phy);
  863. err2:
  864. usb_phy_set_suspend(dwc->usb2_phy, 1);
  865. usb_phy_set_suspend(dwc->usb3_phy, 1);
  866. err1:
  867. usb_phy_shutdown(dwc->usb2_phy);
  868. usb_phy_shutdown(dwc->usb3_phy);
  869. phy_exit(dwc->usb2_generic_phy);
  870. phy_exit(dwc->usb3_generic_phy);
  871. err0a:
  872. dwc3_ulpi_exit(dwc);
  873. err0:
  874. return ret;
  875. }
  876. static int dwc3_core_get_phy(struct dwc3 *dwc)
  877. {
  878. struct device *dev = dwc->dev;
  879. struct device_node *node = dev->of_node;
  880. int ret;
  881. if (node) {
  882. dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
  883. dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
  884. } else {
  885. dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
  886. dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
  887. }
  888. if (IS_ERR(dwc->usb2_phy)) {
  889. ret = PTR_ERR(dwc->usb2_phy);
  890. if (ret == -ENXIO || ret == -ENODEV) {
  891. dwc->usb2_phy = NULL;
  892. } else if (ret == -EPROBE_DEFER) {
  893. return ret;
  894. } else {
  895. dev_err(dev, "no usb2 phy configured\n");
  896. return ret;
  897. }
  898. }
  899. if (IS_ERR(dwc->usb3_phy)) {
  900. ret = PTR_ERR(dwc->usb3_phy);
  901. if (ret == -ENXIO || ret == -ENODEV) {
  902. dwc->usb3_phy = NULL;
  903. } else if (ret == -EPROBE_DEFER) {
  904. return ret;
  905. } else {
  906. dev_err(dev, "no usb3 phy configured\n");
  907. return ret;
  908. }
  909. }
  910. dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
  911. if (IS_ERR(dwc->usb2_generic_phy)) {
  912. ret = PTR_ERR(dwc->usb2_generic_phy);
  913. if (ret == -ENOSYS || ret == -ENODEV) {
  914. dwc->usb2_generic_phy = NULL;
  915. } else if (ret == -EPROBE_DEFER) {
  916. return ret;
  917. } else {
  918. dev_err(dev, "no usb2 phy configured\n");
  919. return ret;
  920. }
  921. }
  922. dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
  923. if (IS_ERR(dwc->usb3_generic_phy)) {
  924. ret = PTR_ERR(dwc->usb3_generic_phy);
  925. if (ret == -ENOSYS || ret == -ENODEV) {
  926. dwc->usb3_generic_phy = NULL;
  927. } else if (ret == -EPROBE_DEFER) {
  928. return ret;
  929. } else {
  930. dev_err(dev, "no usb3 phy configured\n");
  931. return ret;
  932. }
  933. }
  934. return 0;
  935. }
  936. static int dwc3_core_init_mode(struct dwc3 *dwc)
  937. {
  938. struct device *dev = dwc->dev;
  939. int ret;
  940. switch (dwc->dr_mode) {
  941. case USB_DR_MODE_PERIPHERAL:
  942. dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  943. if (dwc->usb2_phy)
  944. otg_set_vbus(dwc->usb2_phy->otg, false);
  945. phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
  946. phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
  947. ret = dwc3_gadget_init(dwc);
  948. if (ret) {
  949. if (ret != -EPROBE_DEFER)
  950. dev_err(dev, "failed to initialize gadget\n");
  951. return ret;
  952. }
  953. break;
  954. case USB_DR_MODE_HOST:
  955. dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
  956. if (dwc->usb2_phy)
  957. otg_set_vbus(dwc->usb2_phy->otg, true);
  958. phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
  959. phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
  960. ret = dwc3_host_init(dwc);
  961. if (ret) {
  962. if (ret != -EPROBE_DEFER)
  963. dev_err(dev, "failed to initialize host\n");
  964. return ret;
  965. }
  966. phy_calibrate(dwc->usb2_generic_phy);
  967. break;
  968. case USB_DR_MODE_OTG:
  969. INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
  970. ret = dwc3_drd_init(dwc);
  971. if (ret) {
  972. if (ret != -EPROBE_DEFER)
  973. dev_err(dev, "failed to initialize dual-role\n");
  974. return ret;
  975. }
  976. break;
  977. default:
  978. dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
  979. return -EINVAL;
  980. }
  981. return 0;
  982. }
  983. static void dwc3_core_exit_mode(struct dwc3 *dwc)
  984. {
  985. switch (dwc->dr_mode) {
  986. case USB_DR_MODE_PERIPHERAL:
  987. dwc3_gadget_exit(dwc);
  988. break;
  989. case USB_DR_MODE_HOST:
  990. dwc3_host_exit(dwc);
  991. break;
  992. case USB_DR_MODE_OTG:
  993. dwc3_drd_exit(dwc);
  994. break;
  995. default:
  996. /* do nothing */
  997. break;
  998. }
  999. /* de-assert DRVVBUS for HOST and OTG mode */
  1000. dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  1001. }
  1002. static void dwc3_get_properties(struct dwc3 *dwc)
  1003. {
  1004. struct device *dev = dwc->dev;
  1005. u8 lpm_nyet_threshold;
  1006. u8 tx_de_emphasis;
  1007. u8 hird_threshold;
  1008. u8 rx_thr_num_pkt_prd;
  1009. u8 rx_max_burst_prd;
  1010. u8 tx_thr_num_pkt_prd;
  1011. u8 tx_max_burst_prd;
  1012. /* default to highest possible threshold */
  1013. lpm_nyet_threshold = 0xf;
  1014. /* default to -3.5dB de-emphasis */
  1015. tx_de_emphasis = 1;
  1016. /*
  1017. * default to assert utmi_sleep_n and use maximum allowed HIRD
  1018. * threshold value of 0b1100
  1019. */
  1020. hird_threshold = 12;
  1021. dwc->maximum_speed = usb_get_maximum_speed(dev);
  1022. dwc->dr_mode = usb_get_dr_mode(dev);
  1023. dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
  1024. dwc->sysdev_is_parent = device_property_read_bool(dev,
  1025. "linux,sysdev_is_parent");
  1026. if (dwc->sysdev_is_parent)
  1027. dwc->sysdev = dwc->dev->parent;
  1028. else
  1029. dwc->sysdev = dwc->dev;
  1030. dwc->has_lpm_erratum = device_property_read_bool(dev,
  1031. "snps,has-lpm-erratum");
  1032. device_property_read_u8(dev, "snps,lpm-nyet-threshold",
  1033. &lpm_nyet_threshold);
  1034. dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
  1035. "snps,is-utmi-l1-suspend");
  1036. device_property_read_u8(dev, "snps,hird-threshold",
  1037. &hird_threshold);
  1038. dwc->usb3_lpm_capable = device_property_read_bool(dev,
  1039. "snps,usb3_lpm_capable");
  1040. device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
  1041. &rx_thr_num_pkt_prd);
  1042. device_property_read_u8(dev, "snps,rx-max-burst-prd",
  1043. &rx_max_burst_prd);
  1044. device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
  1045. &tx_thr_num_pkt_prd);
  1046. device_property_read_u8(dev, "snps,tx-max-burst-prd",
  1047. &tx_max_burst_prd);
  1048. dwc->disable_scramble_quirk = device_property_read_bool(dev,
  1049. "snps,disable_scramble_quirk");
  1050. dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
  1051. "snps,u2exit_lfps_quirk");
  1052. dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
  1053. "snps,u2ss_inp3_quirk");
  1054. dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
  1055. "snps,req_p1p2p3_quirk");
  1056. dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
  1057. "snps,del_p1p2p3_quirk");
  1058. dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
  1059. "snps,del_phy_power_chg_quirk");
  1060. dwc->lfps_filter_quirk = device_property_read_bool(dev,
  1061. "snps,lfps_filter_quirk");
  1062. dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
  1063. "snps,rx_detect_poll_quirk");
  1064. dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
  1065. "snps,dis_u3_susphy_quirk");
  1066. dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
  1067. "snps,dis_u2_susphy_quirk");
  1068. dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
  1069. "snps,dis_enblslpm_quirk");
  1070. dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
  1071. "snps,dis_rxdet_inp3_quirk");
  1072. dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
  1073. "snps,dis-u2-freeclk-exists-quirk");
  1074. dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
  1075. "snps,dis-del-phy-power-chg-quirk");
  1076. dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
  1077. "snps,dis-tx-ipgap-linecheck-quirk");
  1078. dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
  1079. "snps,parkmode-disable-ss-quirk");
  1080. dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
  1081. "snps,tx_de_emphasis_quirk");
  1082. device_property_read_u8(dev, "snps,tx_de_emphasis",
  1083. &tx_de_emphasis);
  1084. device_property_read_string(dev, "snps,hsphy_interface",
  1085. &dwc->hsphy_interface);
  1086. device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
  1087. &dwc->fladj);
  1088. dwc->dis_metastability_quirk = device_property_read_bool(dev,
  1089. "snps,dis_metastability_quirk");
  1090. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  1091. dwc->tx_de_emphasis = tx_de_emphasis;
  1092. dwc->hird_threshold = hird_threshold
  1093. | (dwc->is_utmi_l1_suspend << 4);
  1094. dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
  1095. dwc->rx_max_burst_prd = rx_max_burst_prd;
  1096. dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
  1097. dwc->tx_max_burst_prd = tx_max_burst_prd;
  1098. dwc->imod_interval = 0;
  1099. }
  1100. /* check whether the core supports IMOD */
  1101. bool dwc3_has_imod(struct dwc3 *dwc)
  1102. {
  1103. return ((dwc3_is_usb3(dwc) &&
  1104. dwc->revision >= DWC3_REVISION_300A) ||
  1105. (dwc3_is_usb31(dwc) &&
  1106. dwc->revision >= DWC3_USB31_REVISION_120A));
  1107. }
  1108. static void dwc3_check_params(struct dwc3 *dwc)
  1109. {
  1110. struct device *dev = dwc->dev;
  1111. /* Check for proper value of imod_interval */
  1112. if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
  1113. dev_warn(dwc->dev, "Interrupt moderation not supported\n");
  1114. dwc->imod_interval = 0;
  1115. }
  1116. /*
  1117. * Workaround for STAR 9000961433 which affects only version
  1118. * 3.00a of the DWC_usb3 core. This prevents the controller
  1119. * interrupt from being masked while handling events. IMOD
  1120. * allows us to work around this issue. Enable it for the
  1121. * affected version.
  1122. */
  1123. if (!dwc->imod_interval &&
  1124. (dwc->revision == DWC3_REVISION_300A))
  1125. dwc->imod_interval = 1;
  1126. /* Check the maximum_speed parameter */
  1127. switch (dwc->maximum_speed) {
  1128. case USB_SPEED_LOW:
  1129. case USB_SPEED_FULL:
  1130. case USB_SPEED_HIGH:
  1131. case USB_SPEED_SUPER:
  1132. case USB_SPEED_SUPER_PLUS:
  1133. break;
  1134. default:
  1135. dev_err(dev, "invalid maximum_speed parameter %d\n",
  1136. dwc->maximum_speed);
  1137. /* fall through */
  1138. case USB_SPEED_UNKNOWN:
  1139. /* default to superspeed */
  1140. dwc->maximum_speed = USB_SPEED_SUPER;
  1141. /*
  1142. * default to superspeed plus if we are capable.
  1143. */
  1144. if (dwc3_is_usb31(dwc) &&
  1145. (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  1146. DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
  1147. dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
  1148. break;
  1149. }
  1150. }
  1151. static int dwc3_probe(struct platform_device *pdev)
  1152. {
  1153. struct device *dev = &pdev->dev;
  1154. struct resource *res, dwc_res;
  1155. struct dwc3 *dwc;
  1156. int ret;
  1157. void __iomem *regs;
  1158. dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
  1159. if (!dwc)
  1160. return -ENOMEM;
  1161. dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
  1162. GFP_KERNEL);
  1163. if (!dwc->clks)
  1164. return -ENOMEM;
  1165. dwc->dev = dev;
  1166. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1167. if (!res) {
  1168. dev_err(dev, "missing memory resource\n");
  1169. return -ENODEV;
  1170. }
  1171. dwc->xhci_resources[0].start = res->start;
  1172. dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
  1173. DWC3_XHCI_REGS_END;
  1174. dwc->xhci_resources[0].flags = res->flags;
  1175. dwc->xhci_resources[0].name = res->name;
  1176. /*
  1177. * Request memory region but exclude xHCI regs,
  1178. * since it will be requested by the xhci-plat driver.
  1179. */
  1180. dwc_res = *res;
  1181. dwc_res.start += DWC3_GLOBALS_REGS_START;
  1182. regs = devm_ioremap_resource(dev, &dwc_res);
  1183. if (IS_ERR(regs))
  1184. return PTR_ERR(regs);
  1185. dwc->regs = regs;
  1186. dwc->regs_size = resource_size(&dwc_res);
  1187. dwc3_get_properties(dwc);
  1188. dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
  1189. if (IS_ERR(dwc->reset))
  1190. return PTR_ERR(dwc->reset);
  1191. if (dev->of_node) {
  1192. dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
  1193. ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
  1194. if (ret == -EPROBE_DEFER)
  1195. return ret;
  1196. /*
  1197. * Clocks are optional, but new DT platforms should support all
  1198. * clocks as required by the DT-binding.
  1199. */
  1200. if (ret)
  1201. dwc->num_clks = 0;
  1202. }
  1203. ret = reset_control_deassert(dwc->reset);
  1204. if (ret)
  1205. goto put_clks;
  1206. ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
  1207. if (ret)
  1208. goto assert_reset;
  1209. ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
  1210. if (ret)
  1211. goto unprepare_clks;
  1212. platform_set_drvdata(pdev, dwc);
  1213. dwc3_cache_hwparams(dwc);
  1214. spin_lock_init(&dwc->lock);
  1215. pm_runtime_set_active(dev);
  1216. pm_runtime_use_autosuspend(dev);
  1217. pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
  1218. pm_runtime_enable(dev);
  1219. ret = pm_runtime_get_sync(dev);
  1220. if (ret < 0)
  1221. goto err1;
  1222. pm_runtime_forbid(dev);
  1223. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  1224. if (ret) {
  1225. dev_err(dwc->dev, "failed to allocate event buffers\n");
  1226. ret = -ENOMEM;
  1227. goto err2;
  1228. }
  1229. ret = dwc3_get_dr_mode(dwc);
  1230. if (ret)
  1231. goto err3;
  1232. ret = dwc3_alloc_scratch_buffers(dwc);
  1233. if (ret)
  1234. goto err3;
  1235. ret = dwc3_core_init(dwc);
  1236. if (ret) {
  1237. if (ret != -EPROBE_DEFER)
  1238. dev_err(dev, "failed to initialize core: %d\n", ret);
  1239. goto err4;
  1240. }
  1241. dwc3_check_params(dwc);
  1242. ret = dwc3_core_init_mode(dwc);
  1243. if (ret)
  1244. goto err5;
  1245. dwc3_debugfs_init(dwc);
  1246. pm_runtime_put(dev);
  1247. return 0;
  1248. err5:
  1249. dwc3_event_buffers_cleanup(dwc);
  1250. usb_phy_shutdown(dwc->usb2_phy);
  1251. usb_phy_shutdown(dwc->usb3_phy);
  1252. phy_exit(dwc->usb2_generic_phy);
  1253. phy_exit(dwc->usb3_generic_phy);
  1254. usb_phy_set_suspend(dwc->usb2_phy, 1);
  1255. usb_phy_set_suspend(dwc->usb3_phy, 1);
  1256. phy_power_off(dwc->usb2_generic_phy);
  1257. phy_power_off(dwc->usb3_generic_phy);
  1258. dwc3_ulpi_exit(dwc);
  1259. err4:
  1260. dwc3_free_scratch_buffers(dwc);
  1261. err3:
  1262. dwc3_free_event_buffers(dwc);
  1263. err2:
  1264. pm_runtime_allow(&pdev->dev);
  1265. err1:
  1266. pm_runtime_put_sync(&pdev->dev);
  1267. pm_runtime_disable(&pdev->dev);
  1268. clk_bulk_disable(dwc->num_clks, dwc->clks);
  1269. unprepare_clks:
  1270. clk_bulk_unprepare(dwc->num_clks, dwc->clks);
  1271. assert_reset:
  1272. reset_control_assert(dwc->reset);
  1273. put_clks:
  1274. clk_bulk_put(dwc->num_clks, dwc->clks);
  1275. return ret;
  1276. }
  1277. static int dwc3_remove(struct platform_device *pdev)
  1278. {
  1279. struct dwc3 *dwc = platform_get_drvdata(pdev);
  1280. pm_runtime_get_sync(&pdev->dev);
  1281. dwc3_debugfs_exit(dwc);
  1282. dwc3_core_exit_mode(dwc);
  1283. dwc3_core_exit(dwc);
  1284. dwc3_ulpi_exit(dwc);
  1285. pm_runtime_disable(&pdev->dev);
  1286. pm_runtime_put_noidle(&pdev->dev);
  1287. pm_runtime_set_suspended(&pdev->dev);
  1288. dwc3_free_event_buffers(dwc);
  1289. dwc3_free_scratch_buffers(dwc);
  1290. clk_bulk_put(dwc->num_clks, dwc->clks);
  1291. return 0;
  1292. }
  1293. #ifdef CONFIG_PM
  1294. static int dwc3_core_init_for_resume(struct dwc3 *dwc)
  1295. {
  1296. int ret;
  1297. ret = reset_control_deassert(dwc->reset);
  1298. if (ret)
  1299. return ret;
  1300. ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
  1301. if (ret)
  1302. goto assert_reset;
  1303. ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
  1304. if (ret)
  1305. goto unprepare_clks;
  1306. ret = dwc3_core_init(dwc);
  1307. if (ret)
  1308. goto disable_clks;
  1309. return 0;
  1310. disable_clks:
  1311. clk_bulk_disable(dwc->num_clks, dwc->clks);
  1312. unprepare_clks:
  1313. clk_bulk_unprepare(dwc->num_clks, dwc->clks);
  1314. assert_reset:
  1315. reset_control_assert(dwc->reset);
  1316. return ret;
  1317. }
  1318. static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
  1319. {
  1320. unsigned long flags;
  1321. u32 reg;
  1322. switch (dwc->current_dr_role) {
  1323. case DWC3_GCTL_PRTCAP_DEVICE:
  1324. spin_lock_irqsave(&dwc->lock, flags);
  1325. dwc3_gadget_suspend(dwc);
  1326. spin_unlock_irqrestore(&dwc->lock, flags);
  1327. synchronize_irq(dwc->irq_gadget);
  1328. dwc3_core_exit(dwc);
  1329. break;
  1330. case DWC3_GCTL_PRTCAP_HOST:
  1331. if (!PMSG_IS_AUTO(msg)) {
  1332. dwc3_core_exit(dwc);
  1333. break;
  1334. }
  1335. /* Let controller to suspend HSPHY before PHY driver suspends */
  1336. if (dwc->dis_u2_susphy_quirk ||
  1337. dwc->dis_enblslpm_quirk) {
  1338. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  1339. reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
  1340. DWC3_GUSB2PHYCFG_SUSPHY;
  1341. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  1342. /* Give some time for USB2 PHY to suspend */
  1343. usleep_range(5000, 6000);
  1344. }
  1345. phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
  1346. phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
  1347. break;
  1348. case DWC3_GCTL_PRTCAP_OTG:
  1349. /* do nothing during runtime_suspend */
  1350. if (PMSG_IS_AUTO(msg))
  1351. break;
  1352. if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
  1353. spin_lock_irqsave(&dwc->lock, flags);
  1354. dwc3_gadget_suspend(dwc);
  1355. spin_unlock_irqrestore(&dwc->lock, flags);
  1356. synchronize_irq(dwc->irq_gadget);
  1357. }
  1358. dwc3_otg_exit(dwc);
  1359. dwc3_core_exit(dwc);
  1360. break;
  1361. default:
  1362. /* do nothing */
  1363. break;
  1364. }
  1365. return 0;
  1366. }
  1367. static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
  1368. {
  1369. unsigned long flags;
  1370. int ret;
  1371. u32 reg;
  1372. switch (dwc->current_dr_role) {
  1373. case DWC3_GCTL_PRTCAP_DEVICE:
  1374. ret = dwc3_core_init_for_resume(dwc);
  1375. if (ret)
  1376. return ret;
  1377. dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  1378. spin_lock_irqsave(&dwc->lock, flags);
  1379. dwc3_gadget_resume(dwc);
  1380. spin_unlock_irqrestore(&dwc->lock, flags);
  1381. break;
  1382. case DWC3_GCTL_PRTCAP_HOST:
  1383. if (!PMSG_IS_AUTO(msg)) {
  1384. ret = dwc3_core_init_for_resume(dwc);
  1385. if (ret)
  1386. return ret;
  1387. dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
  1388. break;
  1389. }
  1390. /* Restore GUSB2PHYCFG bits that were modified in suspend */
  1391. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  1392. if (dwc->dis_u2_susphy_quirk)
  1393. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  1394. if (dwc->dis_enblslpm_quirk)
  1395. reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  1396. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  1397. phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
  1398. phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
  1399. break;
  1400. case DWC3_GCTL_PRTCAP_OTG:
  1401. /* nothing to do on runtime_resume */
  1402. if (PMSG_IS_AUTO(msg))
  1403. break;
  1404. ret = dwc3_core_init_for_resume(dwc);
  1405. if (ret)
  1406. return ret;
  1407. dwc3_set_prtcap(dwc, dwc->current_dr_role);
  1408. dwc3_otg_init(dwc);
  1409. if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
  1410. dwc3_otg_host_init(dwc);
  1411. } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
  1412. spin_lock_irqsave(&dwc->lock, flags);
  1413. dwc3_gadget_resume(dwc);
  1414. spin_unlock_irqrestore(&dwc->lock, flags);
  1415. }
  1416. break;
  1417. default:
  1418. /* do nothing */
  1419. break;
  1420. }
  1421. return 0;
  1422. }
  1423. static int dwc3_runtime_checks(struct dwc3 *dwc)
  1424. {
  1425. switch (dwc->current_dr_role) {
  1426. case DWC3_GCTL_PRTCAP_DEVICE:
  1427. if (dwc->connected)
  1428. return -EBUSY;
  1429. break;
  1430. case DWC3_GCTL_PRTCAP_HOST:
  1431. default:
  1432. /* do nothing */
  1433. break;
  1434. }
  1435. return 0;
  1436. }
  1437. static int dwc3_runtime_suspend(struct device *dev)
  1438. {
  1439. struct dwc3 *dwc = dev_get_drvdata(dev);
  1440. int ret;
  1441. if (dwc3_runtime_checks(dwc))
  1442. return -EBUSY;
  1443. ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
  1444. if (ret)
  1445. return ret;
  1446. device_init_wakeup(dev, true);
  1447. return 0;
  1448. }
  1449. static int dwc3_runtime_resume(struct device *dev)
  1450. {
  1451. struct dwc3 *dwc = dev_get_drvdata(dev);
  1452. int ret;
  1453. device_init_wakeup(dev, false);
  1454. ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
  1455. if (ret)
  1456. return ret;
  1457. switch (dwc->current_dr_role) {
  1458. case DWC3_GCTL_PRTCAP_DEVICE:
  1459. dwc3_gadget_process_pending_events(dwc);
  1460. break;
  1461. case DWC3_GCTL_PRTCAP_HOST:
  1462. default:
  1463. /* do nothing */
  1464. break;
  1465. }
  1466. pm_runtime_mark_last_busy(dev);
  1467. return 0;
  1468. }
  1469. static int dwc3_runtime_idle(struct device *dev)
  1470. {
  1471. struct dwc3 *dwc = dev_get_drvdata(dev);
  1472. switch (dwc->current_dr_role) {
  1473. case DWC3_GCTL_PRTCAP_DEVICE:
  1474. if (dwc3_runtime_checks(dwc))
  1475. return -EBUSY;
  1476. break;
  1477. case DWC3_GCTL_PRTCAP_HOST:
  1478. default:
  1479. /* do nothing */
  1480. break;
  1481. }
  1482. pm_runtime_mark_last_busy(dev);
  1483. pm_runtime_autosuspend(dev);
  1484. return 0;
  1485. }
  1486. #endif /* CONFIG_PM */
  1487. #ifdef CONFIG_PM_SLEEP
  1488. static int dwc3_suspend(struct device *dev)
  1489. {
  1490. struct dwc3 *dwc = dev_get_drvdata(dev);
  1491. int ret;
  1492. ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
  1493. if (ret)
  1494. return ret;
  1495. pinctrl_pm_select_sleep_state(dev);
  1496. return 0;
  1497. }
  1498. static int dwc3_resume(struct device *dev)
  1499. {
  1500. struct dwc3 *dwc = dev_get_drvdata(dev);
  1501. int ret;
  1502. pinctrl_pm_select_default_state(dev);
  1503. ret = dwc3_resume_common(dwc, PMSG_RESUME);
  1504. if (ret)
  1505. return ret;
  1506. pm_runtime_disable(dev);
  1507. pm_runtime_set_active(dev);
  1508. pm_runtime_enable(dev);
  1509. return 0;
  1510. }
  1511. #endif /* CONFIG_PM_SLEEP */
  1512. static const struct dev_pm_ops dwc3_dev_pm_ops = {
  1513. SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
  1514. SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
  1515. dwc3_runtime_idle)
  1516. };
  1517. #ifdef CONFIG_OF
  1518. static const struct of_device_id of_dwc3_match[] = {
  1519. {
  1520. .compatible = "snps,dwc3"
  1521. },
  1522. {
  1523. .compatible = "synopsys,dwc3"
  1524. },
  1525. { },
  1526. };
  1527. MODULE_DEVICE_TABLE(of, of_dwc3_match);
  1528. #endif
  1529. #ifdef CONFIG_ACPI
  1530. #define ACPI_ID_INTEL_BSW "808622B7"
  1531. static const struct acpi_device_id dwc3_acpi_match[] = {
  1532. { ACPI_ID_INTEL_BSW, 0 },
  1533. { },
  1534. };
  1535. MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
  1536. #endif
  1537. static struct platform_driver dwc3_driver = {
  1538. .probe = dwc3_probe,
  1539. .remove = dwc3_remove,
  1540. .driver = {
  1541. .name = "dwc3",
  1542. .of_match_table = of_match_ptr(of_dwc3_match),
  1543. .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
  1544. .pm = &dwc3_dev_pm_ops,
  1545. },
  1546. };
  1547. module_platform_driver(dwc3_driver);
  1548. MODULE_ALIAS("platform:dwc3");
  1549. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  1550. MODULE_LICENSE("GPL v2");
  1551. MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");