ehci.h 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2001-2002 by David Brownell
  4. */
  5. #ifndef __LINUX_EHCI_HCD_H
  6. #define __LINUX_EHCI_HCD_H
  7. /* definitions used for the EHCI driver */
  8. /*
  9. * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  10. * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  11. * the host controller implementation.
  12. *
  13. * To facilitate the strongest possible byte-order checking from "sparse"
  14. * and so on, we use __leXX unless that's not practical.
  15. */
  16. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  17. typedef __u32 __bitwise __hc32;
  18. typedef __u16 __bitwise __hc16;
  19. #else
  20. #define __hc32 __le32
  21. #define __hc16 __le16
  22. #endif
  23. /* statistics can be kept for tuning/monitoring */
  24. #ifdef CONFIG_DYNAMIC_DEBUG
  25. #define EHCI_STATS
  26. #endif
  27. struct ehci_stats {
  28. /* irq usage */
  29. unsigned long normal;
  30. unsigned long error;
  31. unsigned long iaa;
  32. unsigned long lost_iaa;
  33. /* termination of urbs from core */
  34. unsigned long complete;
  35. unsigned long unlink;
  36. };
  37. /*
  38. * Scheduling and budgeting information for periodic transfers, for both
  39. * high-speed devices and full/low-speed devices lying behind a TT.
  40. */
  41. struct ehci_per_sched {
  42. struct usb_device *udev; /* access to the TT */
  43. struct usb_host_endpoint *ep;
  44. struct list_head ps_list; /* node on ehci_tt's ps_list */
  45. u16 tt_usecs; /* time on the FS/LS bus */
  46. u16 cs_mask; /* C-mask and S-mask bytes */
  47. u16 period; /* actual period in frames */
  48. u16 phase; /* actual phase, frame part */
  49. u8 bw_phase; /* same, for bandwidth
  50. reservation */
  51. u8 phase_uf; /* uframe part of the phase */
  52. u8 usecs, c_usecs; /* times on the HS bus */
  53. u8 bw_uperiod; /* period in microframes, for
  54. bandwidth reservation */
  55. u8 bw_period; /* same, in frames */
  56. };
  57. #define NO_FRAME 29999 /* frame not assigned yet */
  58. /* ehci_hcd->lock guards shared data against other CPUs:
  59. * ehci_hcd: async, unlink, periodic (and shadow), ...
  60. * usb_host_endpoint: hcpriv
  61. * ehci_qh: qh_next, qtd_list
  62. * ehci_qtd: qtd_list
  63. *
  64. * Also, hold this lock when talking to HC registers or
  65. * when updating hw_* fields in shared qh/qtd/... structures.
  66. */
  67. #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
  68. /*
  69. * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the
  70. * controller may be doing DMA. Lower values mean there's no DMA.
  71. */
  72. enum ehci_rh_state {
  73. EHCI_RH_HALTED,
  74. EHCI_RH_SUSPENDED,
  75. EHCI_RH_RUNNING,
  76. EHCI_RH_STOPPING
  77. };
  78. /*
  79. * Timer events, ordered by increasing delay length.
  80. * Always update event_delays_ns[] and event_handlers[] (defined in
  81. * ehci-timer.c) in parallel with this list.
  82. */
  83. enum ehci_hrtimer_event {
  84. EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
  85. EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
  86. EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
  87. EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
  88. EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
  89. EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */
  90. EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
  91. EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
  92. EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
  93. EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
  94. EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
  95. EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
  96. EHCI_HRTIMER_NUM_EVENTS /* Must come last */
  97. };
  98. #define EHCI_HRTIMER_NO_EVENT 99
  99. struct ehci_hcd { /* one per controller */
  100. /* timing support */
  101. enum ehci_hrtimer_event next_hrtimer_event;
  102. unsigned enabled_hrtimer_events;
  103. ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
  104. struct hrtimer hrtimer;
  105. int PSS_poll_count;
  106. int ASS_poll_count;
  107. int died_poll_count;
  108. /* glue to PCI and HCD framework */
  109. struct ehci_caps __iomem *caps;
  110. struct ehci_regs __iomem *regs;
  111. struct ehci_dbg_port __iomem *debug;
  112. __u32 hcs_params; /* cached register copy */
  113. spinlock_t lock;
  114. enum ehci_rh_state rh_state;
  115. /* general schedule support */
  116. bool scanning:1;
  117. bool need_rescan:1;
  118. bool intr_unlinking:1;
  119. bool iaa_in_progress:1;
  120. bool async_unlinking:1;
  121. bool shutdown:1;
  122. struct ehci_qh *qh_scan_next;
  123. /* async schedule support */
  124. struct ehci_qh *async;
  125. struct ehci_qh *dummy; /* For AMD quirk use */
  126. struct list_head async_unlink;
  127. struct list_head async_idle;
  128. unsigned async_unlink_cycle;
  129. unsigned async_count; /* async activity count */
  130. __hc32 old_current; /* Test for QH becoming */
  131. __hc32 old_token; /* inactive during unlink */
  132. /* periodic schedule support */
  133. #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
  134. unsigned periodic_size;
  135. __hc32 *periodic; /* hw periodic table */
  136. dma_addr_t periodic_dma;
  137. struct list_head intr_qh_list;
  138. unsigned i_thresh; /* uframes HC might cache */
  139. union ehci_shadow *pshadow; /* mirror hw periodic table */
  140. struct list_head intr_unlink_wait;
  141. struct list_head intr_unlink;
  142. unsigned intr_unlink_wait_cycle;
  143. unsigned intr_unlink_cycle;
  144. unsigned now_frame; /* frame from HC hardware */
  145. unsigned last_iso_frame; /* last frame scanned for iso */
  146. unsigned intr_count; /* intr activity count */
  147. unsigned isoc_count; /* isoc activity count */
  148. unsigned periodic_count; /* periodic activity count */
  149. unsigned uframe_periodic_max; /* max periodic time per uframe */
  150. /* list of itds & sitds completed while now_frame was still active */
  151. struct list_head cached_itd_list;
  152. struct ehci_itd *last_itd_to_free;
  153. struct list_head cached_sitd_list;
  154. struct ehci_sitd *last_sitd_to_free;
  155. /* per root hub port */
  156. unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
  157. /* bit vectors (one bit per port) */
  158. unsigned long bus_suspended; /* which ports were
  159. already suspended at the start of a bus suspend */
  160. unsigned long companion_ports; /* which ports are
  161. dedicated to the companion controller */
  162. unsigned long owned_ports; /* which ports are
  163. owned by the companion during a bus suspend */
  164. unsigned long port_c_suspend; /* which ports have
  165. the change-suspend feature turned on */
  166. unsigned long suspended_ports; /* which ports are
  167. suspended */
  168. unsigned long resuming_ports; /* which ports have
  169. started to resume */
  170. /* per-HC memory pools (could be per-bus, but ...) */
  171. struct dma_pool *qh_pool; /* qh per active urb */
  172. struct dma_pool *qtd_pool; /* one or more per qh */
  173. struct dma_pool *itd_pool; /* itd per iso urb */
  174. struct dma_pool *sitd_pool; /* sitd per split iso urb */
  175. unsigned random_frame;
  176. unsigned long next_statechange;
  177. ktime_t last_periodic_enable;
  178. u32 command;
  179. /* SILICON QUIRKS */
  180. unsigned no_selective_suspend:1;
  181. unsigned has_fsl_port_bug:1; /* FreeScale */
  182. unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */
  183. unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */
  184. unsigned big_endian_mmio:1;
  185. unsigned big_endian_desc:1;
  186. unsigned big_endian_capbase:1;
  187. unsigned has_amcc_usb23:1;
  188. unsigned need_io_watchdog:1;
  189. unsigned amd_pll_fix:1;
  190. unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
  191. unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
  192. unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
  193. unsigned need_oc_pp_cycle:1; /* MPC834X port power */
  194. unsigned imx28_write_fix:1; /* For Freescale i.MX28 */
  195. /* required for usb32 quirk */
  196. #define OHCI_CTRL_HCFS (3 << 6)
  197. #define OHCI_USB_OPER (2 << 6)
  198. #define OHCI_USB_SUSPEND (3 << 6)
  199. #define OHCI_HCCTRL_OFFSET 0x4
  200. #define OHCI_HCCTRL_LEN 0x4
  201. __hc32 *ohci_hcctrl_reg;
  202. unsigned has_hostpc:1;
  203. unsigned has_tdi_phy_lpm:1;
  204. unsigned has_ppcd:1; /* support per-port change bits */
  205. u8 sbrn; /* packed release number */
  206. /* irq statistics */
  207. #ifdef EHCI_STATS
  208. struct ehci_stats stats;
  209. # define COUNT(x) ((x)++)
  210. #else
  211. # define COUNT(x)
  212. #endif
  213. /* debug files */
  214. #ifdef CONFIG_DYNAMIC_DEBUG
  215. struct dentry *debug_dir;
  216. #endif
  217. /* bandwidth usage */
  218. #define EHCI_BANDWIDTH_SIZE 64
  219. #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3)
  220. u8 bandwidth[EHCI_BANDWIDTH_SIZE];
  221. /* us allocated per uframe */
  222. u8 tt_budget[EHCI_BANDWIDTH_SIZE];
  223. /* us budgeted per uframe */
  224. struct list_head tt_list;
  225. /* platform-specific data -- must come last */
  226. unsigned long priv[0] __aligned(sizeof(s64));
  227. };
  228. /* convert between an HCD pointer and the corresponding EHCI_HCD */
  229. static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
  230. {
  231. return (struct ehci_hcd *) (hcd->hcd_priv);
  232. }
  233. static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
  234. {
  235. return container_of((void *) ehci, struct usb_hcd, hcd_priv);
  236. }
  237. /*-------------------------------------------------------------------------*/
  238. #include <linux/usb/ehci_def.h>
  239. /*-------------------------------------------------------------------------*/
  240. #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
  241. /*
  242. * EHCI Specification 0.95 Section 3.5
  243. * QTD: describe data transfer components (buffer, direction, ...)
  244. * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
  245. *
  246. * These are associated only with "QH" (Queue Head) structures,
  247. * used with control, bulk, and interrupt transfers.
  248. */
  249. struct ehci_qtd {
  250. /* first part defined by EHCI spec */
  251. __hc32 hw_next; /* see EHCI 3.5.1 */
  252. __hc32 hw_alt_next; /* see EHCI 3.5.2 */
  253. __hc32 hw_token; /* see EHCI 3.5.3 */
  254. #define QTD_TOGGLE (1 << 31) /* data toggle */
  255. #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
  256. #define QTD_IOC (1 << 15) /* interrupt on complete */
  257. #define QTD_CERR(tok) (((tok)>>10) & 0x3)
  258. #define QTD_PID(tok) (((tok)>>8) & 0x3)
  259. #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
  260. #define QTD_STS_HALT (1 << 6) /* halted on error */
  261. #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
  262. #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
  263. #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
  264. #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
  265. #define QTD_STS_STS (1 << 1) /* split transaction state */
  266. #define QTD_STS_PING (1 << 0) /* issue PING? */
  267. #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
  268. #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
  269. #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
  270. __hc32 hw_buf[5]; /* see EHCI 3.5.4 */
  271. __hc32 hw_buf_hi[5]; /* Appendix B */
  272. /* the rest is HCD-private */
  273. dma_addr_t qtd_dma; /* qtd address */
  274. struct list_head qtd_list; /* sw qtd list */
  275. struct urb *urb; /* qtd's urb */
  276. size_t length; /* length of buffer */
  277. } __aligned(32);
  278. /* mask NakCnt+T in qh->hw_alt_next */
  279. #define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f)
  280. #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
  281. /*-------------------------------------------------------------------------*/
  282. /* type tag from {qh,itd,sitd,fstn}->hw_next */
  283. #define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
  284. /*
  285. * Now the following defines are not converted using the
  286. * cpu_to_le32() macro anymore, since we have to support
  287. * "dynamic" switching between be and le support, so that the driver
  288. * can be used on one system with SoC EHCI controller using big-endian
  289. * descriptors as well as a normal little-endian PCI EHCI controller.
  290. */
  291. /* values for that type tag */
  292. #define Q_TYPE_ITD (0 << 1)
  293. #define Q_TYPE_QH (1 << 1)
  294. #define Q_TYPE_SITD (2 << 1)
  295. #define Q_TYPE_FSTN (3 << 1)
  296. /* next async queue entry, or pointer to interrupt/periodic QH */
  297. #define QH_NEXT(ehci, dma) \
  298. (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
  299. /* for periodic/async schedules and qtd lists, mark end of list */
  300. #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
  301. /*
  302. * Entries in periodic shadow table are pointers to one of four kinds
  303. * of data structure. That's dictated by the hardware; a type tag is
  304. * encoded in the low bits of the hardware's periodic schedule. Use
  305. * Q_NEXT_TYPE to get the tag.
  306. *
  307. * For entries in the async schedule, the type tag always says "qh".
  308. */
  309. union ehci_shadow {
  310. struct ehci_qh *qh; /* Q_TYPE_QH */
  311. struct ehci_itd *itd; /* Q_TYPE_ITD */
  312. struct ehci_sitd *sitd; /* Q_TYPE_SITD */
  313. struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
  314. __hc32 *hw_next; /* (all types) */
  315. void *ptr;
  316. };
  317. /*-------------------------------------------------------------------------*/
  318. /*
  319. * EHCI Specification 0.95 Section 3.6
  320. * QH: describes control/bulk/interrupt endpoints
  321. * See Fig 3-7 "Queue Head Structure Layout".
  322. *
  323. * These appear in both the async and (for interrupt) periodic schedules.
  324. */
  325. /* first part defined by EHCI spec */
  326. struct ehci_qh_hw {
  327. __hc32 hw_next; /* see EHCI 3.6.1 */
  328. __hc32 hw_info1; /* see EHCI 3.6.2 */
  329. #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
  330. #define QH_HEAD (1 << 15) /* Head of async reclamation list */
  331. #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
  332. #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
  333. #define QH_LOW_SPEED (1 << 12)
  334. #define QH_FULL_SPEED (0 << 12)
  335. #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
  336. __hc32 hw_info2; /* see EHCI 3.6.2 */
  337. #define QH_SMASK 0x000000ff
  338. #define QH_CMASK 0x0000ff00
  339. #define QH_HUBADDR 0x007f0000
  340. #define QH_HUBPORT 0x3f800000
  341. #define QH_MULT 0xc0000000
  342. __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
  343. /* qtd overlay (hardware parts of a struct ehci_qtd) */
  344. __hc32 hw_qtd_next;
  345. __hc32 hw_alt_next;
  346. __hc32 hw_token;
  347. __hc32 hw_buf[5];
  348. __hc32 hw_buf_hi[5];
  349. } __aligned(32);
  350. struct ehci_qh {
  351. struct ehci_qh_hw *hw; /* Must come first */
  352. /* the rest is HCD-private */
  353. dma_addr_t qh_dma; /* address of qh */
  354. union ehci_shadow qh_next; /* ptr to qh; or periodic */
  355. struct list_head qtd_list; /* sw qtd list */
  356. struct list_head intr_node; /* list of intr QHs */
  357. struct ehci_qtd *dummy;
  358. struct list_head unlink_node;
  359. struct ehci_per_sched ps; /* scheduling info */
  360. unsigned unlink_cycle;
  361. u8 qh_state;
  362. #define QH_STATE_LINKED 1 /* HC sees this */
  363. #define QH_STATE_UNLINK 2 /* HC may still see this */
  364. #define QH_STATE_IDLE 3 /* HC doesn't see this */
  365. #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
  366. #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
  367. u8 xacterrs; /* XactErr retry counter */
  368. #define QH_XACTERR_MAX 32 /* XactErr retry limit */
  369. u8 unlink_reason;
  370. #define QH_UNLINK_HALTED 0x01 /* Halt flag is set */
  371. #define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */
  372. #define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */
  373. #define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */
  374. #define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */
  375. #define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */
  376. u8 gap_uf; /* uframes split/csplit gap */
  377. unsigned is_out:1; /* bulk or intr OUT */
  378. unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
  379. unsigned dequeue_during_giveback:1;
  380. unsigned should_be_inactive:1;
  381. };
  382. /*-------------------------------------------------------------------------*/
  383. /* description of one iso transaction (up to 3 KB data if highspeed) */
  384. struct ehci_iso_packet {
  385. /* These will be copied to iTD when scheduling */
  386. u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
  387. __hc32 transaction; /* itd->hw_transaction[i] |= */
  388. u8 cross; /* buf crosses pages */
  389. /* for full speed OUT splits */
  390. u32 buf1;
  391. };
  392. /* temporary schedule data for packets from iso urbs (both speeds)
  393. * each packet is one logical usb transaction to the device (not TT),
  394. * beginning at stream->next_uframe
  395. */
  396. struct ehci_iso_sched {
  397. struct list_head td_list;
  398. unsigned span;
  399. unsigned first_packet;
  400. struct ehci_iso_packet packet[0];
  401. };
  402. /*
  403. * ehci_iso_stream - groups all (s)itds for this endpoint.
  404. * acts like a qh would, if EHCI had them for ISO.
  405. */
  406. struct ehci_iso_stream {
  407. /* first field matches ehci_hq, but is NULL */
  408. struct ehci_qh_hw *hw;
  409. u8 bEndpointAddress;
  410. u8 highspeed;
  411. struct list_head td_list; /* queued itds/sitds */
  412. struct list_head free_list; /* list of unused itds/sitds */
  413. /* output of (re)scheduling */
  414. struct ehci_per_sched ps; /* scheduling info */
  415. unsigned next_uframe;
  416. __hc32 splits;
  417. /* the rest is derived from the endpoint descriptor,
  418. * including the extra info for hw_bufp[0..2]
  419. */
  420. u16 uperiod; /* period in uframes */
  421. u16 maxp;
  422. unsigned bandwidth;
  423. /* This is used to initialize iTD's hw_bufp fields */
  424. __hc32 buf0;
  425. __hc32 buf1;
  426. __hc32 buf2;
  427. /* this is used to initialize sITD's tt info */
  428. __hc32 address;
  429. };
  430. /*-------------------------------------------------------------------------*/
  431. /*
  432. * EHCI Specification 0.95 Section 3.3
  433. * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
  434. *
  435. * Schedule records for high speed iso xfers
  436. */
  437. struct ehci_itd {
  438. /* first part defined by EHCI spec */
  439. __hc32 hw_next; /* see EHCI 3.3.1 */
  440. __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
  441. #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
  442. #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
  443. #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
  444. #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
  445. #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
  446. #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
  447. #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
  448. __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
  449. __hc32 hw_bufp_hi[7]; /* Appendix B */
  450. /* the rest is HCD-private */
  451. dma_addr_t itd_dma; /* for this itd */
  452. union ehci_shadow itd_next; /* ptr to periodic q entry */
  453. struct urb *urb;
  454. struct ehci_iso_stream *stream; /* endpoint's queue */
  455. struct list_head itd_list; /* list of stream's itds */
  456. /* any/all hw_transactions here may be used by that urb */
  457. unsigned frame; /* where scheduled */
  458. unsigned pg;
  459. unsigned index[8]; /* in urb->iso_frame_desc */
  460. } __aligned(32);
  461. /*-------------------------------------------------------------------------*/
  462. /*
  463. * EHCI Specification 0.95 Section 3.4
  464. * siTD, aka split-transaction isochronous Transfer Descriptor
  465. * ... describe full speed iso xfers through TT in hubs
  466. * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
  467. */
  468. struct ehci_sitd {
  469. /* first part defined by EHCI spec */
  470. __hc32 hw_next;
  471. /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
  472. __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
  473. __hc32 hw_uframe; /* EHCI table 3-10 */
  474. __hc32 hw_results; /* EHCI table 3-11 */
  475. #define SITD_IOC (1 << 31) /* interrupt on completion */
  476. #define SITD_PAGE (1 << 30) /* buffer 0/1 */
  477. #define SITD_LENGTH(x) (((x) >> 16) & 0x3ff)
  478. #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
  479. #define SITD_STS_ERR (1 << 6) /* error from TT */
  480. #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
  481. #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
  482. #define SITD_STS_XACT (1 << 3) /* illegal IN response */
  483. #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
  484. #define SITD_STS_STS (1 << 1) /* split transaction state */
  485. #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
  486. __hc32 hw_buf[2]; /* EHCI table 3-12 */
  487. __hc32 hw_backpointer; /* EHCI table 3-13 */
  488. __hc32 hw_buf_hi[2]; /* Appendix B */
  489. /* the rest is HCD-private */
  490. dma_addr_t sitd_dma;
  491. union ehci_shadow sitd_next; /* ptr to periodic q entry */
  492. struct urb *urb;
  493. struct ehci_iso_stream *stream; /* endpoint's queue */
  494. struct list_head sitd_list; /* list of stream's sitds */
  495. unsigned frame;
  496. unsigned index;
  497. } __aligned(32);
  498. /*-------------------------------------------------------------------------*/
  499. /*
  500. * EHCI Specification 0.96 Section 3.7
  501. * Periodic Frame Span Traversal Node (FSTN)
  502. *
  503. * Manages split interrupt transactions (using TT) that span frame boundaries
  504. * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
  505. * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
  506. * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
  507. */
  508. struct ehci_fstn {
  509. __hc32 hw_next; /* any periodic q entry */
  510. __hc32 hw_prev; /* qh or EHCI_LIST_END */
  511. /* the rest is HCD-private */
  512. dma_addr_t fstn_dma;
  513. union ehci_shadow fstn_next; /* ptr to periodic q entry */
  514. } __aligned(32);
  515. /*-------------------------------------------------------------------------*/
  516. /*
  517. * USB-2.0 Specification Sections 11.14 and 11.18
  518. * Scheduling and budgeting split transactions using TTs
  519. *
  520. * A hub can have a single TT for all its ports, or multiple TTs (one for each
  521. * port). The bandwidth and budgeting information for the full/low-speed bus
  522. * below each TT is self-contained and independent of the other TTs or the
  523. * high-speed bus.
  524. *
  525. * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated
  526. * to an interrupt or isochronous endpoint for each frame. "Budget" refers to
  527. * the best-case estimate of the number of full-speed bytes allocated to an
  528. * endpoint for each microframe within an allocated frame.
  529. *
  530. * Removal of an endpoint invalidates a TT's budget. Instead of trying to
  531. * keep an up-to-date record, we recompute the budget when it is needed.
  532. */
  533. struct ehci_tt {
  534. u16 bandwidth[EHCI_BANDWIDTH_FRAMES];
  535. struct list_head tt_list; /* List of all ehci_tt's */
  536. struct list_head ps_list; /* Items using this TT */
  537. struct usb_tt *usb_tt;
  538. int tt_port; /* TT port number */
  539. };
  540. /*-------------------------------------------------------------------------*/
  541. /* Prepare the PORTSC wakeup flags during controller suspend/resume */
  542. #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
  543. ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
  544. #define ehci_prepare_ports_for_controller_resume(ehci) \
  545. ehci_adjust_port_wakeup_flags(ehci, false, false)
  546. /*-------------------------------------------------------------------------*/
  547. #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
  548. /*
  549. * Some EHCI controllers have a Transaction Translator built into the
  550. * root hub. This is a non-standard feature. Each controller will need
  551. * to add code to the following inline functions, and call them as
  552. * needed (mostly in root hub code).
  553. */
  554. #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
  555. /* Returns the speed of a device attached to a port on the root hub. */
  556. static inline unsigned int
  557. ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
  558. {
  559. if (ehci_is_TDI(ehci)) {
  560. switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
  561. case 0:
  562. return 0;
  563. case 1:
  564. return USB_PORT_STAT_LOW_SPEED;
  565. case 2:
  566. default:
  567. return USB_PORT_STAT_HIGH_SPEED;
  568. }
  569. }
  570. return USB_PORT_STAT_HIGH_SPEED;
  571. }
  572. #else
  573. #define ehci_is_TDI(e) (0)
  574. #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
  575. #endif
  576. /*-------------------------------------------------------------------------*/
  577. #ifdef CONFIG_PPC_83xx
  578. /* Some Freescale processors have an erratum in which the TT
  579. * port number in the queue head was 0..N-1 instead of 1..N.
  580. */
  581. #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
  582. #else
  583. #define ehci_has_fsl_portno_bug(e) (0)
  584. #endif
  585. #define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */
  586. #if defined(CONFIG_PPC_85xx)
  587. /* Some Freescale processors have an erratum (USB A-005275) in which
  588. * incoming packets get corrupted in HS mode
  589. */
  590. #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
  591. #else
  592. #define ehci_has_fsl_hs_errata(e) (0)
  593. #endif
  594. /*
  595. * Some Freescale/NXP processors have an erratum (USB A-005697)
  596. * in which we need to wait for 10ms for bus to enter suspend mode
  597. * after setting SUSP bit.
  598. */
  599. #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
  600. /*
  601. * While most USB host controllers implement their registers in
  602. * little-endian format, a minority (celleb companion chip) implement
  603. * them in big endian format.
  604. *
  605. * This attempts to support either format at compile time without a
  606. * runtime penalty, or both formats with the additional overhead
  607. * of checking a flag bit.
  608. *
  609. * ehci_big_endian_capbase is a special quirk for controllers that
  610. * implement the HC capability registers as separate registers and not
  611. * as fields of a 32-bit register.
  612. */
  613. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  614. #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
  615. #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
  616. #else
  617. #define ehci_big_endian_mmio(e) 0
  618. #define ehci_big_endian_capbase(e) 0
  619. #endif
  620. /*
  621. * Big-endian read/write functions are arch-specific.
  622. * Other arches can be added if/when they're needed.
  623. */
  624. #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
  625. #define readl_be(addr) __raw_readl((__force unsigned *)addr)
  626. #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
  627. #endif
  628. static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
  629. __u32 __iomem *regs)
  630. {
  631. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  632. return ehci_big_endian_mmio(ehci) ?
  633. readl_be(regs) :
  634. readl(regs);
  635. #else
  636. return readl(regs);
  637. #endif
  638. }
  639. #ifdef CONFIG_SOC_IMX28
  640. static inline void imx28_ehci_writel(const unsigned int val,
  641. volatile __u32 __iomem *addr)
  642. {
  643. __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
  644. }
  645. #else
  646. static inline void imx28_ehci_writel(const unsigned int val,
  647. volatile __u32 __iomem *addr)
  648. {
  649. }
  650. #endif
  651. static inline void ehci_writel(const struct ehci_hcd *ehci,
  652. const unsigned int val, __u32 __iomem *regs)
  653. {
  654. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  655. ehci_big_endian_mmio(ehci) ?
  656. writel_be(val, regs) :
  657. writel(val, regs);
  658. #else
  659. if (ehci->imx28_write_fix)
  660. imx28_ehci_writel(val, regs);
  661. else
  662. writel(val, regs);
  663. #endif
  664. }
  665. /*
  666. * On certain ppc-44x SoC there is a HW issue, that could only worked around with
  667. * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
  668. * Other common bits are dependent on has_amcc_usb23 quirk flag.
  669. */
  670. #ifdef CONFIG_44x
  671. static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
  672. {
  673. u32 hc_control;
  674. hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
  675. if (operational)
  676. hc_control |= OHCI_USB_OPER;
  677. else
  678. hc_control |= OHCI_USB_SUSPEND;
  679. writel_be(hc_control, ehci->ohci_hcctrl_reg);
  680. (void) readl_be(ehci->ohci_hcctrl_reg);
  681. }
  682. #else
  683. static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
  684. { }
  685. #endif
  686. /*-------------------------------------------------------------------------*/
  687. /*
  688. * The AMCC 440EPx not only implements its EHCI registers in big-endian
  689. * format, but also its DMA data structures (descriptors).
  690. *
  691. * EHCI controllers accessed through PCI work normally (little-endian
  692. * everywhere), so we won't bother supporting a BE-only mode for now.
  693. */
  694. #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  695. #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
  696. /* cpu to ehci */
  697. static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
  698. {
  699. return ehci_big_endian_desc(ehci)
  700. ? (__force __hc32)cpu_to_be32(x)
  701. : (__force __hc32)cpu_to_le32(x);
  702. }
  703. /* ehci to cpu */
  704. static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
  705. {
  706. return ehci_big_endian_desc(ehci)
  707. ? be32_to_cpu((__force __be32)x)
  708. : le32_to_cpu((__force __le32)x);
  709. }
  710. static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
  711. {
  712. return ehci_big_endian_desc(ehci)
  713. ? be32_to_cpup((__force __be32 *)x)
  714. : le32_to_cpup((__force __le32 *)x);
  715. }
  716. #else
  717. /* cpu to ehci */
  718. static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
  719. {
  720. return cpu_to_le32(x);
  721. }
  722. /* ehci to cpu */
  723. static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
  724. {
  725. return le32_to_cpu(x);
  726. }
  727. static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
  728. {
  729. return le32_to_cpup(x);
  730. }
  731. #endif
  732. /*-------------------------------------------------------------------------*/
  733. #define ehci_dbg(ehci, fmt, args...) \
  734. dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
  735. #define ehci_err(ehci, fmt, args...) \
  736. dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
  737. #define ehci_info(ehci, fmt, args...) \
  738. dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
  739. #define ehci_warn(ehci, fmt, args...) \
  740. dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
  741. /*-------------------------------------------------------------------------*/
  742. /* Declarations of things exported for use by ehci platform drivers */
  743. struct ehci_driver_overrides {
  744. size_t extra_priv_size;
  745. int (*reset)(struct usb_hcd *hcd);
  746. int (*port_power)(struct usb_hcd *hcd,
  747. int portnum, bool enable);
  748. };
  749. extern void ehci_init_driver(struct hc_driver *drv,
  750. const struct ehci_driver_overrides *over);
  751. extern int ehci_setup(struct usb_hcd *hcd);
  752. extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
  753. u32 mask, u32 done, int usec);
  754. extern int ehci_reset(struct ehci_hcd *ehci);
  755. extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
  756. extern int ehci_resume(struct usb_hcd *hcd, bool force_reset);
  757. extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
  758. bool suspending, bool do_wakeup);
  759. extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
  760. u16 wIndex, char *buf, u16 wLength);
  761. #endif /* __LINUX_EHCI_HCD_H */