xhci-dbgcap.c 22 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004
  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * xhci-dbgcap.c - xHCI debug capability support
  4. *
  5. * Copyright (C) 2017 Intel Corporation
  6. *
  7. * Author: Lu Baolu <baolu.lu@linux.intel.com>
  8. */
  9. #include <linux/dma-mapping.h>
  10. #include <linux/slab.h>
  11. #include <linux/nls.h>
  12. #include "xhci.h"
  13. #include "xhci-trace.h"
  14. #include "xhci-dbgcap.h"
  15. static inline void *
  16. dbc_dma_alloc_coherent(struct xhci_hcd *xhci, size_t size,
  17. dma_addr_t *dma_handle, gfp_t flags)
  18. {
  19. void *vaddr;
  20. vaddr = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
  21. size, dma_handle, flags);
  22. memset(vaddr, 0, size);
  23. return vaddr;
  24. }
  25. static inline void
  26. dbc_dma_free_coherent(struct xhci_hcd *xhci, size_t size,
  27. void *cpu_addr, dma_addr_t dma_handle)
  28. {
  29. if (cpu_addr)
  30. dma_free_coherent(xhci_to_hcd(xhci)->self.sysdev,
  31. size, cpu_addr, dma_handle);
  32. }
  33. static u32 xhci_dbc_populate_strings(struct dbc_str_descs *strings)
  34. {
  35. struct usb_string_descriptor *s_desc;
  36. u32 string_length;
  37. /* Serial string: */
  38. s_desc = (struct usb_string_descriptor *)strings->serial;
  39. utf8s_to_utf16s(DBC_STRING_SERIAL, strlen(DBC_STRING_SERIAL),
  40. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  41. DBC_MAX_STRING_LENGTH);
  42. s_desc->bLength = (strlen(DBC_STRING_SERIAL) + 1) * 2;
  43. s_desc->bDescriptorType = USB_DT_STRING;
  44. string_length = s_desc->bLength;
  45. string_length <<= 8;
  46. /* Product string: */
  47. s_desc = (struct usb_string_descriptor *)strings->product;
  48. utf8s_to_utf16s(DBC_STRING_PRODUCT, strlen(DBC_STRING_PRODUCT),
  49. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  50. DBC_MAX_STRING_LENGTH);
  51. s_desc->bLength = (strlen(DBC_STRING_PRODUCT) + 1) * 2;
  52. s_desc->bDescriptorType = USB_DT_STRING;
  53. string_length += s_desc->bLength;
  54. string_length <<= 8;
  55. /* Manufacture string: */
  56. s_desc = (struct usb_string_descriptor *)strings->manufacturer;
  57. utf8s_to_utf16s(DBC_STRING_MANUFACTURER,
  58. strlen(DBC_STRING_MANUFACTURER),
  59. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  60. DBC_MAX_STRING_LENGTH);
  61. s_desc->bLength = (strlen(DBC_STRING_MANUFACTURER) + 1) * 2;
  62. s_desc->bDescriptorType = USB_DT_STRING;
  63. string_length += s_desc->bLength;
  64. string_length <<= 8;
  65. /* String0: */
  66. strings->string0[0] = 4;
  67. strings->string0[1] = USB_DT_STRING;
  68. strings->string0[2] = 0x09;
  69. strings->string0[3] = 0x04;
  70. string_length += 4;
  71. return string_length;
  72. }
  73. static void xhci_dbc_init_contexts(struct xhci_hcd *xhci, u32 string_length)
  74. {
  75. struct xhci_dbc *dbc;
  76. struct dbc_info_context *info;
  77. struct xhci_ep_ctx *ep_ctx;
  78. u32 dev_info;
  79. dma_addr_t deq, dma;
  80. unsigned int max_burst;
  81. dbc = xhci->dbc;
  82. if (!dbc)
  83. return;
  84. /* Populate info Context: */
  85. info = (struct dbc_info_context *)dbc->ctx->bytes;
  86. dma = dbc->string_dma;
  87. info->string0 = cpu_to_le64(dma);
  88. info->manufacturer = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH);
  89. info->product = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 2);
  90. info->serial = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 3);
  91. info->length = cpu_to_le32(string_length);
  92. /* Populate bulk out endpoint context: */
  93. ep_ctx = dbc_bulkout_ctx(dbc);
  94. max_burst = DBC_CTRL_MAXBURST(readl(&dbc->regs->control));
  95. deq = dbc_bulkout_enq(dbc);
  96. ep_ctx->ep_info = 0;
  97. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_OUT_EP, 1024, max_burst);
  98. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_out->cycle_state);
  99. /* Populate bulk in endpoint context: */
  100. ep_ctx = dbc_bulkin_ctx(dbc);
  101. deq = dbc_bulkin_enq(dbc);
  102. ep_ctx->ep_info = 0;
  103. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_IN_EP, 1024, max_burst);
  104. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_in->cycle_state);
  105. /* Set DbC context and info registers: */
  106. xhci_write_64(xhci, dbc->ctx->dma, &dbc->regs->dccp);
  107. dev_info = cpu_to_le32((DBC_VENDOR_ID << 16) | DBC_PROTOCOL);
  108. writel(dev_info, &dbc->regs->devinfo1);
  109. dev_info = cpu_to_le32((DBC_DEVICE_REV << 16) | DBC_PRODUCT_ID);
  110. writel(dev_info, &dbc->regs->devinfo2);
  111. }
  112. static void xhci_dbc_giveback(struct dbc_request *req, int status)
  113. __releases(&dbc->lock)
  114. __acquires(&dbc->lock)
  115. {
  116. struct dbc_ep *dep = req->dep;
  117. struct xhci_dbc *dbc = dep->dbc;
  118. struct xhci_hcd *xhci = dbc->xhci;
  119. struct device *dev = xhci_to_hcd(dbc->xhci)->self.sysdev;
  120. list_del_init(&req->list_pending);
  121. req->trb_dma = 0;
  122. req->trb = NULL;
  123. if (req->status == -EINPROGRESS)
  124. req->status = status;
  125. trace_xhci_dbc_giveback_request(req);
  126. dma_unmap_single(dev,
  127. req->dma,
  128. req->length,
  129. dbc_ep_dma_direction(dep));
  130. /* Give back the transfer request: */
  131. spin_unlock(&dbc->lock);
  132. req->complete(xhci, req);
  133. spin_lock(&dbc->lock);
  134. }
  135. static void xhci_dbc_flush_single_request(struct dbc_request *req)
  136. {
  137. union xhci_trb *trb = req->trb;
  138. trb->generic.field[0] = 0;
  139. trb->generic.field[1] = 0;
  140. trb->generic.field[2] = 0;
  141. trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
  142. trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(TRB_TR_NOOP));
  143. xhci_dbc_giveback(req, -ESHUTDOWN);
  144. }
  145. static void xhci_dbc_flush_endpoint_requests(struct dbc_ep *dep)
  146. {
  147. struct dbc_request *req, *tmp;
  148. list_for_each_entry_safe(req, tmp, &dep->list_pending, list_pending)
  149. xhci_dbc_flush_single_request(req);
  150. }
  151. static void xhci_dbc_flush_reqests(struct xhci_dbc *dbc)
  152. {
  153. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_OUT]);
  154. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_IN]);
  155. }
  156. struct dbc_request *
  157. dbc_alloc_request(struct dbc_ep *dep, gfp_t gfp_flags)
  158. {
  159. struct dbc_request *req;
  160. req = kzalloc(sizeof(*req), gfp_flags);
  161. if (!req)
  162. return NULL;
  163. req->dep = dep;
  164. INIT_LIST_HEAD(&req->list_pending);
  165. INIT_LIST_HEAD(&req->list_pool);
  166. req->direction = dep->direction;
  167. trace_xhci_dbc_alloc_request(req);
  168. return req;
  169. }
  170. void
  171. dbc_free_request(struct dbc_ep *dep, struct dbc_request *req)
  172. {
  173. trace_xhci_dbc_free_request(req);
  174. kfree(req);
  175. }
  176. static void
  177. xhci_dbc_queue_trb(struct xhci_ring *ring, u32 field1,
  178. u32 field2, u32 field3, u32 field4)
  179. {
  180. union xhci_trb *trb, *next;
  181. trb = ring->enqueue;
  182. trb->generic.field[0] = cpu_to_le32(field1);
  183. trb->generic.field[1] = cpu_to_le32(field2);
  184. trb->generic.field[2] = cpu_to_le32(field3);
  185. trb->generic.field[3] = cpu_to_le32(field4);
  186. trace_xhci_dbc_gadget_ep_queue(ring, &trb->generic);
  187. ring->num_trbs_free--;
  188. next = ++(ring->enqueue);
  189. if (TRB_TYPE_LINK_LE32(next->link.control)) {
  190. next->link.control ^= cpu_to_le32(TRB_CYCLE);
  191. ring->enqueue = ring->enq_seg->trbs;
  192. ring->cycle_state ^= 1;
  193. }
  194. }
  195. static int xhci_dbc_queue_bulk_tx(struct dbc_ep *dep,
  196. struct dbc_request *req)
  197. {
  198. u64 addr;
  199. union xhci_trb *trb;
  200. unsigned int num_trbs;
  201. struct xhci_dbc *dbc = dep->dbc;
  202. struct xhci_ring *ring = dep->ring;
  203. u32 length, control, cycle;
  204. num_trbs = count_trbs(req->dma, req->length);
  205. WARN_ON(num_trbs != 1);
  206. if (ring->num_trbs_free < num_trbs)
  207. return -EBUSY;
  208. addr = req->dma;
  209. trb = ring->enqueue;
  210. cycle = ring->cycle_state;
  211. length = TRB_LEN(req->length);
  212. control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
  213. if (cycle)
  214. control &= cpu_to_le32(~TRB_CYCLE);
  215. else
  216. control |= cpu_to_le32(TRB_CYCLE);
  217. req->trb = ring->enqueue;
  218. req->trb_dma = xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
  219. xhci_dbc_queue_trb(ring,
  220. lower_32_bits(addr),
  221. upper_32_bits(addr),
  222. length, control);
  223. /*
  224. * Add a barrier between writes of trb fields and flipping
  225. * the cycle bit:
  226. */
  227. wmb();
  228. if (cycle)
  229. trb->generic.field[3] |= cpu_to_le32(TRB_CYCLE);
  230. else
  231. trb->generic.field[3] &= cpu_to_le32(~TRB_CYCLE);
  232. writel(DBC_DOOR_BELL_TARGET(dep->direction), &dbc->regs->doorbell);
  233. return 0;
  234. }
  235. static int
  236. dbc_ep_do_queue(struct dbc_ep *dep, struct dbc_request *req)
  237. {
  238. int ret;
  239. struct device *dev;
  240. struct xhci_dbc *dbc = dep->dbc;
  241. struct xhci_hcd *xhci = dbc->xhci;
  242. dev = xhci_to_hcd(xhci)->self.sysdev;
  243. if (!req->length || !req->buf)
  244. return -EINVAL;
  245. req->actual = 0;
  246. req->status = -EINPROGRESS;
  247. req->dma = dma_map_single(dev,
  248. req->buf,
  249. req->length,
  250. dbc_ep_dma_direction(dep));
  251. if (dma_mapping_error(dev, req->dma)) {
  252. xhci_err(xhci, "failed to map buffer\n");
  253. return -EFAULT;
  254. }
  255. ret = xhci_dbc_queue_bulk_tx(dep, req);
  256. if (ret) {
  257. xhci_err(xhci, "failed to queue trbs\n");
  258. dma_unmap_single(dev,
  259. req->dma,
  260. req->length,
  261. dbc_ep_dma_direction(dep));
  262. return -EFAULT;
  263. }
  264. list_add_tail(&req->list_pending, &dep->list_pending);
  265. return 0;
  266. }
  267. int dbc_ep_queue(struct dbc_ep *dep, struct dbc_request *req,
  268. gfp_t gfp_flags)
  269. {
  270. unsigned long flags;
  271. struct xhci_dbc *dbc = dep->dbc;
  272. int ret = -ESHUTDOWN;
  273. spin_lock_irqsave(&dbc->lock, flags);
  274. if (dbc->state == DS_CONFIGURED)
  275. ret = dbc_ep_do_queue(dep, req);
  276. spin_unlock_irqrestore(&dbc->lock, flags);
  277. mod_delayed_work(system_wq, &dbc->event_work, 0);
  278. trace_xhci_dbc_queue_request(req);
  279. return ret;
  280. }
  281. static inline void xhci_dbc_do_eps_init(struct xhci_hcd *xhci, bool direction)
  282. {
  283. struct dbc_ep *dep;
  284. struct xhci_dbc *dbc = xhci->dbc;
  285. dep = &dbc->eps[direction];
  286. dep->dbc = dbc;
  287. dep->direction = direction;
  288. dep->ring = direction ? dbc->ring_in : dbc->ring_out;
  289. INIT_LIST_HEAD(&dep->list_pending);
  290. }
  291. static void xhci_dbc_eps_init(struct xhci_hcd *xhci)
  292. {
  293. xhci_dbc_do_eps_init(xhci, BULK_OUT);
  294. xhci_dbc_do_eps_init(xhci, BULK_IN);
  295. }
  296. static void xhci_dbc_eps_exit(struct xhci_hcd *xhci)
  297. {
  298. struct xhci_dbc *dbc = xhci->dbc;
  299. memset(dbc->eps, 0, sizeof(struct dbc_ep) * ARRAY_SIZE(dbc->eps));
  300. }
  301. static int xhci_dbc_mem_init(struct xhci_hcd *xhci, gfp_t flags)
  302. {
  303. int ret;
  304. dma_addr_t deq;
  305. u32 string_length;
  306. struct xhci_dbc *dbc = xhci->dbc;
  307. /* Allocate various rings for events and transfers: */
  308. dbc->ring_evt = xhci_ring_alloc(xhci, 1, 1, TYPE_EVENT, 0, flags);
  309. if (!dbc->ring_evt)
  310. goto evt_fail;
  311. dbc->ring_in = xhci_ring_alloc(xhci, 1, 1, TYPE_BULK, 0, flags);
  312. if (!dbc->ring_in)
  313. goto in_fail;
  314. dbc->ring_out = xhci_ring_alloc(xhci, 1, 1, TYPE_BULK, 0, flags);
  315. if (!dbc->ring_out)
  316. goto out_fail;
  317. /* Allocate and populate ERST: */
  318. ret = xhci_alloc_erst(xhci, dbc->ring_evt, &dbc->erst, flags);
  319. if (ret)
  320. goto erst_fail;
  321. /* Allocate context data structure: */
  322. dbc->ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
  323. if (!dbc->ctx)
  324. goto ctx_fail;
  325. /* Allocate the string table: */
  326. dbc->string_size = sizeof(struct dbc_str_descs);
  327. dbc->string = dbc_dma_alloc_coherent(xhci,
  328. dbc->string_size,
  329. &dbc->string_dma,
  330. flags);
  331. if (!dbc->string)
  332. goto string_fail;
  333. /* Setup ERST register: */
  334. writel(dbc->erst.erst_size, &dbc->regs->ersts);
  335. xhci_write_64(xhci, dbc->erst.erst_dma_addr, &dbc->regs->erstba);
  336. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  337. dbc->ring_evt->dequeue);
  338. xhci_write_64(xhci, deq, &dbc->regs->erdp);
  339. /* Setup strings and contexts: */
  340. string_length = xhci_dbc_populate_strings(dbc->string);
  341. xhci_dbc_init_contexts(xhci, string_length);
  342. mmiowb();
  343. xhci_dbc_eps_init(xhci);
  344. dbc->state = DS_INITIALIZED;
  345. return 0;
  346. string_fail:
  347. xhci_free_container_ctx(xhci, dbc->ctx);
  348. dbc->ctx = NULL;
  349. ctx_fail:
  350. xhci_free_erst(xhci, &dbc->erst);
  351. erst_fail:
  352. xhci_ring_free(xhci, dbc->ring_out);
  353. dbc->ring_out = NULL;
  354. out_fail:
  355. xhci_ring_free(xhci, dbc->ring_in);
  356. dbc->ring_in = NULL;
  357. in_fail:
  358. xhci_ring_free(xhci, dbc->ring_evt);
  359. dbc->ring_evt = NULL;
  360. evt_fail:
  361. return -ENOMEM;
  362. }
  363. static void xhci_dbc_mem_cleanup(struct xhci_hcd *xhci)
  364. {
  365. struct xhci_dbc *dbc = xhci->dbc;
  366. if (!dbc)
  367. return;
  368. xhci_dbc_eps_exit(xhci);
  369. if (dbc->string) {
  370. dbc_dma_free_coherent(xhci,
  371. dbc->string_size,
  372. dbc->string, dbc->string_dma);
  373. dbc->string = NULL;
  374. }
  375. xhci_free_container_ctx(xhci, dbc->ctx);
  376. dbc->ctx = NULL;
  377. xhci_free_erst(xhci, &dbc->erst);
  378. xhci_ring_free(xhci, dbc->ring_out);
  379. xhci_ring_free(xhci, dbc->ring_in);
  380. xhci_ring_free(xhci, dbc->ring_evt);
  381. dbc->ring_in = NULL;
  382. dbc->ring_out = NULL;
  383. dbc->ring_evt = NULL;
  384. }
  385. static int xhci_do_dbc_start(struct xhci_hcd *xhci)
  386. {
  387. int ret;
  388. u32 ctrl;
  389. struct xhci_dbc *dbc = xhci->dbc;
  390. if (dbc->state != DS_DISABLED)
  391. return -EINVAL;
  392. writel(0, &dbc->regs->control);
  393. ret = xhci_handshake(&dbc->regs->control,
  394. DBC_CTRL_DBC_ENABLE,
  395. 0, 1000);
  396. if (ret)
  397. return ret;
  398. ret = xhci_dbc_mem_init(xhci, GFP_ATOMIC);
  399. if (ret)
  400. return ret;
  401. ctrl = readl(&dbc->regs->control);
  402. writel(ctrl | DBC_CTRL_DBC_ENABLE | DBC_CTRL_PORT_ENABLE,
  403. &dbc->regs->control);
  404. ret = xhci_handshake(&dbc->regs->control,
  405. DBC_CTRL_DBC_ENABLE,
  406. DBC_CTRL_DBC_ENABLE, 1000);
  407. if (ret)
  408. return ret;
  409. dbc->state = DS_ENABLED;
  410. return 0;
  411. }
  412. static int xhci_do_dbc_stop(struct xhci_hcd *xhci)
  413. {
  414. struct xhci_dbc *dbc = xhci->dbc;
  415. if (dbc->state == DS_DISABLED)
  416. return -1;
  417. writel(0, &dbc->regs->control);
  418. dbc->state = DS_DISABLED;
  419. return 0;
  420. }
  421. static int xhci_dbc_start(struct xhci_hcd *xhci)
  422. {
  423. int ret;
  424. unsigned long flags;
  425. struct xhci_dbc *dbc = xhci->dbc;
  426. WARN_ON(!dbc);
  427. pm_runtime_get_sync(xhci_to_hcd(xhci)->self.controller);
  428. spin_lock_irqsave(&dbc->lock, flags);
  429. ret = xhci_do_dbc_start(xhci);
  430. spin_unlock_irqrestore(&dbc->lock, flags);
  431. if (ret) {
  432. pm_runtime_put(xhci_to_hcd(xhci)->self.controller);
  433. return ret;
  434. }
  435. return mod_delayed_work(system_wq, &dbc->event_work, 1);
  436. }
  437. static void xhci_dbc_stop(struct xhci_hcd *xhci)
  438. {
  439. int ret;
  440. unsigned long flags;
  441. struct xhci_dbc *dbc = xhci->dbc;
  442. struct dbc_port *port = &dbc->port;
  443. WARN_ON(!dbc);
  444. cancel_delayed_work_sync(&dbc->event_work);
  445. if (port->registered)
  446. xhci_dbc_tty_unregister_device(xhci);
  447. spin_lock_irqsave(&dbc->lock, flags);
  448. ret = xhci_do_dbc_stop(xhci);
  449. spin_unlock_irqrestore(&dbc->lock, flags);
  450. if (!ret) {
  451. xhci_dbc_mem_cleanup(xhci);
  452. pm_runtime_put_sync(xhci_to_hcd(xhci)->self.controller);
  453. }
  454. }
  455. static void
  456. dbc_handle_port_status(struct xhci_hcd *xhci, union xhci_trb *event)
  457. {
  458. u32 portsc;
  459. struct xhci_dbc *dbc = xhci->dbc;
  460. portsc = readl(&dbc->regs->portsc);
  461. if (portsc & DBC_PORTSC_CONN_CHANGE)
  462. xhci_info(xhci, "DbC port connect change\n");
  463. if (portsc & DBC_PORTSC_RESET_CHANGE)
  464. xhci_info(xhci, "DbC port reset change\n");
  465. if (portsc & DBC_PORTSC_LINK_CHANGE)
  466. xhci_info(xhci, "DbC port link status change\n");
  467. if (portsc & DBC_PORTSC_CONFIG_CHANGE)
  468. xhci_info(xhci, "DbC config error change\n");
  469. /* Port reset change bit will be cleared in other place: */
  470. writel(portsc & ~DBC_PORTSC_RESET_CHANGE, &dbc->regs->portsc);
  471. }
  472. static void dbc_handle_xfer_event(struct xhci_hcd *xhci, union xhci_trb *event)
  473. {
  474. struct dbc_ep *dep;
  475. struct xhci_ring *ring;
  476. int ep_id;
  477. int status;
  478. u32 comp_code;
  479. size_t remain_length;
  480. struct dbc_request *req = NULL, *r;
  481. comp_code = GET_COMP_CODE(le32_to_cpu(event->generic.field[2]));
  482. remain_length = EVENT_TRB_LEN(le32_to_cpu(event->generic.field[2]));
  483. ep_id = TRB_TO_EP_ID(le32_to_cpu(event->generic.field[3]));
  484. dep = (ep_id == EPID_OUT) ?
  485. get_out_ep(xhci) : get_in_ep(xhci);
  486. ring = dep->ring;
  487. switch (comp_code) {
  488. case COMP_SUCCESS:
  489. remain_length = 0;
  490. /* FALLTHROUGH */
  491. case COMP_SHORT_PACKET:
  492. status = 0;
  493. break;
  494. case COMP_TRB_ERROR:
  495. case COMP_BABBLE_DETECTED_ERROR:
  496. case COMP_USB_TRANSACTION_ERROR:
  497. case COMP_STALL_ERROR:
  498. xhci_warn(xhci, "tx error %d detected\n", comp_code);
  499. status = -comp_code;
  500. break;
  501. default:
  502. xhci_err(xhci, "unknown tx error %d\n", comp_code);
  503. status = -comp_code;
  504. break;
  505. }
  506. /* Match the pending request: */
  507. list_for_each_entry(r, &dep->list_pending, list_pending) {
  508. if (r->trb_dma == event->trans_event.buffer) {
  509. req = r;
  510. break;
  511. }
  512. }
  513. if (!req) {
  514. xhci_warn(xhci, "no matched request\n");
  515. return;
  516. }
  517. trace_xhci_dbc_handle_transfer(ring, &req->trb->generic);
  518. ring->num_trbs_free++;
  519. req->actual = req->length - remain_length;
  520. xhci_dbc_giveback(req, status);
  521. }
  522. static enum evtreturn xhci_dbc_do_handle_events(struct xhci_dbc *dbc)
  523. {
  524. dma_addr_t deq;
  525. struct dbc_ep *dep;
  526. union xhci_trb *evt;
  527. u32 ctrl, portsc;
  528. struct xhci_hcd *xhci = dbc->xhci;
  529. bool update_erdp = false;
  530. /* DbC state machine: */
  531. switch (dbc->state) {
  532. case DS_DISABLED:
  533. case DS_INITIALIZED:
  534. return EVT_ERR;
  535. case DS_ENABLED:
  536. portsc = readl(&dbc->regs->portsc);
  537. if (portsc & DBC_PORTSC_CONN_STATUS) {
  538. dbc->state = DS_CONNECTED;
  539. xhci_info(xhci, "DbC connected\n");
  540. }
  541. return EVT_DONE;
  542. case DS_CONNECTED:
  543. ctrl = readl(&dbc->regs->control);
  544. if (ctrl & DBC_CTRL_DBC_RUN) {
  545. dbc->state = DS_CONFIGURED;
  546. xhci_info(xhci, "DbC configured\n");
  547. portsc = readl(&dbc->regs->portsc);
  548. writel(portsc, &dbc->regs->portsc);
  549. return EVT_GSER;
  550. }
  551. return EVT_DONE;
  552. case DS_CONFIGURED:
  553. /* Handle cable unplug event: */
  554. portsc = readl(&dbc->regs->portsc);
  555. if (!(portsc & DBC_PORTSC_PORT_ENABLED) &&
  556. !(portsc & DBC_PORTSC_CONN_STATUS)) {
  557. xhci_info(xhci, "DbC cable unplugged\n");
  558. dbc->state = DS_ENABLED;
  559. xhci_dbc_flush_reqests(dbc);
  560. return EVT_DISC;
  561. }
  562. /* Handle debug port reset event: */
  563. if (portsc & DBC_PORTSC_RESET_CHANGE) {
  564. xhci_info(xhci, "DbC port reset\n");
  565. writel(portsc, &dbc->regs->portsc);
  566. dbc->state = DS_ENABLED;
  567. xhci_dbc_flush_reqests(dbc);
  568. return EVT_DISC;
  569. }
  570. /* Handle endpoint stall event: */
  571. ctrl = readl(&dbc->regs->control);
  572. if ((ctrl & DBC_CTRL_HALT_IN_TR) ||
  573. (ctrl & DBC_CTRL_HALT_OUT_TR)) {
  574. xhci_info(xhci, "DbC Endpoint stall\n");
  575. dbc->state = DS_STALLED;
  576. if (ctrl & DBC_CTRL_HALT_IN_TR) {
  577. dep = get_in_ep(xhci);
  578. xhci_dbc_flush_endpoint_requests(dep);
  579. }
  580. if (ctrl & DBC_CTRL_HALT_OUT_TR) {
  581. dep = get_out_ep(xhci);
  582. xhci_dbc_flush_endpoint_requests(dep);
  583. }
  584. return EVT_DONE;
  585. }
  586. /* Clear DbC run change bit: */
  587. if (ctrl & DBC_CTRL_DBC_RUN_CHANGE) {
  588. writel(ctrl, &dbc->regs->control);
  589. ctrl = readl(&dbc->regs->control);
  590. }
  591. break;
  592. case DS_STALLED:
  593. ctrl = readl(&dbc->regs->control);
  594. if (!(ctrl & DBC_CTRL_HALT_IN_TR) &&
  595. !(ctrl & DBC_CTRL_HALT_OUT_TR) &&
  596. (ctrl & DBC_CTRL_DBC_RUN)) {
  597. dbc->state = DS_CONFIGURED;
  598. break;
  599. }
  600. return EVT_DONE;
  601. default:
  602. xhci_err(xhci, "Unknown DbC state %d\n", dbc->state);
  603. break;
  604. }
  605. /* Handle the events in the event ring: */
  606. evt = dbc->ring_evt->dequeue;
  607. while ((le32_to_cpu(evt->event_cmd.flags) & TRB_CYCLE) ==
  608. dbc->ring_evt->cycle_state) {
  609. /*
  610. * Add a barrier between reading the cycle flag and any
  611. * reads of the event's flags/data below:
  612. */
  613. rmb();
  614. trace_xhci_dbc_handle_event(dbc->ring_evt, &evt->generic);
  615. switch (le32_to_cpu(evt->event_cmd.flags) & TRB_TYPE_BITMASK) {
  616. case TRB_TYPE(TRB_PORT_STATUS):
  617. dbc_handle_port_status(xhci, evt);
  618. break;
  619. case TRB_TYPE(TRB_TRANSFER):
  620. dbc_handle_xfer_event(xhci, evt);
  621. break;
  622. default:
  623. break;
  624. }
  625. inc_deq(xhci, dbc->ring_evt);
  626. evt = dbc->ring_evt->dequeue;
  627. update_erdp = true;
  628. }
  629. /* Update event ring dequeue pointer: */
  630. if (update_erdp) {
  631. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  632. dbc->ring_evt->dequeue);
  633. xhci_write_64(xhci, deq, &dbc->regs->erdp);
  634. }
  635. return EVT_DONE;
  636. }
  637. static void xhci_dbc_handle_events(struct work_struct *work)
  638. {
  639. int ret;
  640. enum evtreturn evtr;
  641. struct xhci_dbc *dbc;
  642. unsigned long flags;
  643. struct xhci_hcd *xhci;
  644. dbc = container_of(to_delayed_work(work), struct xhci_dbc, event_work);
  645. xhci = dbc->xhci;
  646. spin_lock_irqsave(&dbc->lock, flags);
  647. evtr = xhci_dbc_do_handle_events(dbc);
  648. spin_unlock_irqrestore(&dbc->lock, flags);
  649. switch (evtr) {
  650. case EVT_GSER:
  651. ret = xhci_dbc_tty_register_device(xhci);
  652. if (ret) {
  653. xhci_err(xhci, "failed to alloc tty device\n");
  654. break;
  655. }
  656. xhci_info(xhci, "DbC now attached to /dev/ttyDBC0\n");
  657. break;
  658. case EVT_DISC:
  659. xhci_dbc_tty_unregister_device(xhci);
  660. break;
  661. case EVT_DONE:
  662. break;
  663. default:
  664. xhci_info(xhci, "stop handling dbc events\n");
  665. return;
  666. }
  667. mod_delayed_work(system_wq, &dbc->event_work, 1);
  668. }
  669. static void xhci_do_dbc_exit(struct xhci_hcd *xhci)
  670. {
  671. unsigned long flags;
  672. spin_lock_irqsave(&xhci->lock, flags);
  673. kfree(xhci->dbc);
  674. xhci->dbc = NULL;
  675. spin_unlock_irqrestore(&xhci->lock, flags);
  676. }
  677. static int xhci_do_dbc_init(struct xhci_hcd *xhci)
  678. {
  679. u32 reg;
  680. struct xhci_dbc *dbc;
  681. unsigned long flags;
  682. void __iomem *base;
  683. int dbc_cap_offs;
  684. base = &xhci->cap_regs->hc_capbase;
  685. dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG);
  686. if (!dbc_cap_offs)
  687. return -ENODEV;
  688. dbc = kzalloc(sizeof(*dbc), GFP_KERNEL);
  689. if (!dbc)
  690. return -ENOMEM;
  691. dbc->regs = base + dbc_cap_offs;
  692. /* We will avoid using DbC in xhci driver if it's in use. */
  693. reg = readl(&dbc->regs->control);
  694. if (reg & DBC_CTRL_DBC_ENABLE) {
  695. kfree(dbc);
  696. return -EBUSY;
  697. }
  698. spin_lock_irqsave(&xhci->lock, flags);
  699. if (xhci->dbc) {
  700. spin_unlock_irqrestore(&xhci->lock, flags);
  701. kfree(dbc);
  702. return -EBUSY;
  703. }
  704. xhci->dbc = dbc;
  705. spin_unlock_irqrestore(&xhci->lock, flags);
  706. dbc->xhci = xhci;
  707. INIT_DELAYED_WORK(&dbc->event_work, xhci_dbc_handle_events);
  708. spin_lock_init(&dbc->lock);
  709. return 0;
  710. }
  711. static ssize_t dbc_show(struct device *dev,
  712. struct device_attribute *attr,
  713. char *buf)
  714. {
  715. const char *p;
  716. struct xhci_dbc *dbc;
  717. struct xhci_hcd *xhci;
  718. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  719. dbc = xhci->dbc;
  720. switch (dbc->state) {
  721. case DS_DISABLED:
  722. p = "disabled";
  723. break;
  724. case DS_INITIALIZED:
  725. p = "initialized";
  726. break;
  727. case DS_ENABLED:
  728. p = "enabled";
  729. break;
  730. case DS_CONNECTED:
  731. p = "connected";
  732. break;
  733. case DS_CONFIGURED:
  734. p = "configured";
  735. break;
  736. case DS_STALLED:
  737. p = "stalled";
  738. break;
  739. default:
  740. p = "unknown";
  741. }
  742. return sprintf(buf, "%s\n", p);
  743. }
  744. static ssize_t dbc_store(struct device *dev,
  745. struct device_attribute *attr,
  746. const char *buf, size_t count)
  747. {
  748. struct xhci_hcd *xhci;
  749. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  750. if (!strncmp(buf, "enable", 6))
  751. xhci_dbc_start(xhci);
  752. else if (!strncmp(buf, "disable", 7))
  753. xhci_dbc_stop(xhci);
  754. else
  755. return -EINVAL;
  756. return count;
  757. }
  758. static DEVICE_ATTR_RW(dbc);
  759. int xhci_dbc_init(struct xhci_hcd *xhci)
  760. {
  761. int ret;
  762. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  763. ret = xhci_do_dbc_init(xhci);
  764. if (ret)
  765. goto init_err3;
  766. ret = xhci_dbc_tty_register_driver(xhci);
  767. if (ret)
  768. goto init_err2;
  769. ret = device_create_file(dev, &dev_attr_dbc);
  770. if (ret)
  771. goto init_err1;
  772. return 0;
  773. init_err1:
  774. xhci_dbc_tty_unregister_driver();
  775. init_err2:
  776. xhci_do_dbc_exit(xhci);
  777. init_err3:
  778. return ret;
  779. }
  780. void xhci_dbc_exit(struct xhci_hcd *xhci)
  781. {
  782. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  783. if (!xhci->dbc)
  784. return;
  785. device_remove_file(dev, &dev_attr_dbc);
  786. xhci_dbc_tty_unregister_driver();
  787. xhci_dbc_stop(xhci);
  788. xhci_do_dbc_exit(xhci);
  789. }
  790. #ifdef CONFIG_PM
  791. int xhci_dbc_suspend(struct xhci_hcd *xhci)
  792. {
  793. struct xhci_dbc *dbc = xhci->dbc;
  794. if (!dbc)
  795. return 0;
  796. if (dbc->state == DS_CONFIGURED)
  797. dbc->resume_required = 1;
  798. xhci_dbc_stop(xhci);
  799. return 0;
  800. }
  801. int xhci_dbc_resume(struct xhci_hcd *xhci)
  802. {
  803. int ret = 0;
  804. struct xhci_dbc *dbc = xhci->dbc;
  805. if (!dbc)
  806. return 0;
  807. if (dbc->resume_required) {
  808. dbc->resume_required = 0;
  809. xhci_dbc_start(xhci);
  810. }
  811. return ret;
  812. }
  813. #endif /* CONFIG_PM */