helios4.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
  4. * based on board/solidrun/clearfog/clearfog.c
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <miiphy.h>
  9. #include <netdev.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/cpu.h>
  12. #include <asm/arch/soc.h>
  13. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  14. #include <../serdes/a38x/high_speed_env_spec.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #define ETH_PHY_CTRL_REG 0
  17. #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
  18. #define ETH_PHY_CTRL_POWER_DOWN_MASK BIT(ETH_PHY_CTRL_POWER_DOWN_BIT)
  19. /*
  20. * Those values and defines are taken from the Marvell U-Boot version
  21. * "u-boot-2013.01-15t1-helios4" as well as the upstream config for clearfog
  22. */
  23. #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
  24. #define BOARD_GPP_OUT_ENA_MID 0xffffffff
  25. #define BOARD_GPP_OUT_VAL_LOW 0x0
  26. #define BOARD_GPP_OUT_VAL_MID 0x0
  27. #define BOARD_GPP_POL_LOW 0x0
  28. #define BOARD_GPP_POL_MID 0x0
  29. /* IO expander on Marvell GP board includes e.g. fan enabling */
  30. struct marvell_io_exp {
  31. u8 addr;
  32. u8 val;
  33. };
  34. static struct marvell_io_exp io_exp[] = {
  35. {6, 0xf9},
  36. {2, 0x46}, /* Assert reset signals and enable USB3 current limiter */
  37. {6, 0xb9}
  38. };
  39. static struct serdes_map board_serdes_map[] = {
  40. {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  41. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  42. {SATA1, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  43. {SATA3, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  44. {SATA2, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  45. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  46. };
  47. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  48. {
  49. *serdes_map_array = board_serdes_map;
  50. *count = ARRAY_SIZE(board_serdes_map);
  51. return 0;
  52. }
  53. /*
  54. * Define the DDR layout / topology here in the board file. This will
  55. * be used by the DDR3 init code in the SPL U-Boot version to configure
  56. * the DDR3 controller.
  57. */
  58. static struct mv_ddr_topology_map board_topology_map = {
  59. DEBUG_LEVEL_ERROR,
  60. 0x1, /* active interfaces */
  61. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  62. { { { {0x1, 0, 0, 0},
  63. {0x1, 0, 0, 0},
  64. {0x1, 0, 0, 0},
  65. {0x1, 0, 0, 0},
  66. {0x1, 0, 0, 0} },
  67. SPEED_BIN_DDR_1600K, /* speed_bin */
  68. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  69. MV_DDR_DIE_CAP_8GBIT, /* mem_size */
  70. DDR_FREQ_800, /* frequency */
  71. 0, 0, /* cas_wl cas_l */
  72. MV_DDR_TEMP_LOW, /* temperature */
  73. MV_DDR_TIM_DEFAULT} }, /* timing */
  74. BUS_MASK_32BIT_ECC, /* Busses mask */
  75. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  76. { {0} }, /* raw spd data */
  77. {0} /* timing parameters */
  78. };
  79. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  80. {
  81. /* Return the board topology as defined in the board code */
  82. return &board_topology_map;
  83. }
  84. int board_early_init_f(void)
  85. {
  86. /* Configure MPP */
  87. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  88. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  89. writel(0x10400011, MVEBU_MPP_BASE + 0x08);
  90. writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
  91. writel(0x44400002, MVEBU_MPP_BASE + 0x10);
  92. writel(0x41144004, MVEBU_MPP_BASE + 0x14);
  93. writel(0x40333333, MVEBU_MPP_BASE + 0x18);
  94. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  95. /* Set GPP Out value */
  96. writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  97. writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  98. /* Set GPP Polarity */
  99. writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  100. writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  101. /* Set GPP Out Enable */
  102. writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  103. writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  104. return 0;
  105. }
  106. int board_init(void)
  107. {
  108. int i;
  109. /* Address of boot parameters */
  110. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  111. /* Init I2C IO expanders */
  112. for (i = 0; i < ARRAY_SIZE(io_exp); i++) {
  113. struct udevice *dev;
  114. int ret;
  115. ret = i2c_get_chip_for_busnum(0, io_exp[i].addr, 1, &dev);
  116. if (ret) {
  117. printf("Cannot find I2C: %d\n", ret);
  118. return 0;
  119. }
  120. ret = dm_i2c_write(dev, io_exp[i].val, &io_exp[i].val, 1);
  121. if (ret) {
  122. printf("Failed to set IO expander via I2C\n");
  123. return -EIO;
  124. }
  125. }
  126. return 0;
  127. }
  128. int checkboard(void)
  129. {
  130. puts("Board: Helios4\n");
  131. return 0;
  132. }
  133. int board_eth_init(bd_t *bis)
  134. {
  135. cpu_eth_init(bis); /* Built in controller(s) come first */
  136. return pci_eth_init(bis);
  137. }