lowlevel_init.S 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2008 Nobuhiro Iwamatsu
  4. * Copyright (C) 2008 Renesas Solutions Corp.
  5. */
  6. #include <config.h>
  7. #include <asm/processor.h>
  8. #include <asm/macro.h>
  9. .global lowlevel_init
  10. .text
  11. .align 2
  12. lowlevel_init:
  13. /* Cache setting */
  14. write32 CCR1_A ,CCR1_D
  15. /* ConfigurePortPins */
  16. write16 PECRL3_A, PECRL3_D
  17. write16 PCCRL4_A, PCCRL4_D0
  18. write16 PECRL4_A, PECRL4_D0
  19. write16 PEIORL_A, PEIORL_D0
  20. write16 PCIORL_A, PCIORL_D
  21. write16 PFCRH2_A, PFCRH2_D
  22. write16 PFCRH3_A, PFCRH3_D
  23. write16 PFCRH1_A, PFCRH1_D
  24. write16 PFIORH_A, PFIORH_D
  25. write16 PECRL1_A, PECRL1_D0
  26. write16 PEIORL_A, PEIORL_D1
  27. /* Configure Operating Frequency */
  28. write16 WTCSR_A, WTCSR_D0
  29. write16 WTCSR_A, WTCSR_D1
  30. write16 WTCNT_A, WTCNT_D
  31. /* Set clock mode*/
  32. write16 FRQCR_A, FRQCR_D
  33. /* Configure Bus And Memory */
  34. init_bsc_cs0:
  35. write16 PCCRL4_A, PCCRL4_D1
  36. write16 PECRL1_A, PECRL1_D1
  37. write32 CMNCR_A, CMNCR_D
  38. write32 CS0BCR_A, CS0BCR_D
  39. write32 CS0WCR_A, CS0WCR_D
  40. init_bsc_cs1:
  41. write16 PECRL4_A, PECRL4_D1
  42. write32 CS1WCR_A, CS1WCR_D
  43. init_sdram:
  44. write16 PCCRL2_A, PCCRL2_D
  45. write16 PCCRL4_A, PCCRL4_D2
  46. write16 PCCRL1_A, PCCRL1_D
  47. write16 PCCRL3_A, PCCRL3_D
  48. write32 CS3BCR_A, CS3BCR_D
  49. write32 CS3WCR_A, CS3WCR_D
  50. write32 SDCR_A, SDCR_D
  51. write32 RTCOR_A, RTCOR_D
  52. write32 RTCSR_A, RTCSR_D
  53. /* wait 200us */
  54. mov.l REPEAT_D, r3
  55. mov #0, r2
  56. repeat0:
  57. add #1, r2
  58. cmp/hs r3, r2
  59. bf repeat0
  60. nop
  61. mov.l SDRAM_MODE, r1
  62. mov #0, r0
  63. mov.l r0, @r1
  64. nop
  65. rts
  66. .align 4
  67. CCR1_A: .long CCR1
  68. CCR1_D: .long 0x0000090B
  69. PCCRL4_A: .long 0xFFFE3910
  70. PCCRL4_D0: .word 0x0000
  71. .align 2
  72. PECRL4_A: .long 0xFFFE3A10
  73. PECRL4_D0: .word 0x0000
  74. .align 2
  75. PECRL3_A: .long 0xFFFE3A12
  76. PECRL3_D: .word 0x0000
  77. .align 2
  78. PEIORL_A: .long 0xFFFE3A06
  79. PEIORL_D0: .word 0x1C00
  80. PEIORL_D1: .word 0x1C02
  81. PCIORL_A: .long 0xFFFE3906
  82. PCIORL_D: .word 0x4000
  83. .align 2
  84. PFCRH2_A: .long 0xFFFE3A8C
  85. PFCRH2_D: .word 0x0000
  86. .align 2
  87. PFCRH3_A: .long 0xFFFE3A8A
  88. PFCRH3_D: .word 0x0000
  89. .align 2
  90. PFCRH1_A: .long 0xFFFE3A8E
  91. PFCRH1_D: .word 0x0000
  92. .align 2
  93. PFIORH_A: .long 0xFFFE3A84
  94. PFIORH_D: .word 0x0729
  95. .align 2
  96. PECRL1_A: .long 0xFFFE3A16
  97. PECRL1_D0: .word 0x0033
  98. .align 2
  99. WTCSR_A: .long 0xFFFE0000
  100. WTCSR_D0: .word 0xA518
  101. WTCSR_D1: .word 0xA51D
  102. WTCNT_A: .long 0xFFFE0002
  103. WTCNT_D: .word 0x5A84
  104. .align 2
  105. FRQCR_A: .long 0xFFFE0010
  106. FRQCR_D: .word 0x0104
  107. .align 2
  108. PCCRL4_D1: .word 0x0010
  109. PECRL1_D1: .word 0x0133
  110. CMNCR_A: .long 0xFFFC0000
  111. CMNCR_D: .long 0x00001810
  112. CS0BCR_A: .long 0xFFFC0004
  113. CS0BCR_D: .long 0x10000400
  114. CS0WCR_A: .long 0xFFFC0028
  115. CS0WCR_D: .long 0x00000B41
  116. PECRL4_D1: .word 0x0100
  117. .align 2
  118. CS1WCR_A: .long 0xFFFC002C
  119. CS1WCR_D: .long 0x00000B01
  120. PCCRL4_D2: .word 0x0011
  121. .align 2
  122. PCCRL3_A: .long 0xFFFE3912
  123. PCCRL3_D: .word 0x0011
  124. .align 2
  125. PCCRL2_A: .long 0xFFFE3914
  126. PCCRL2_D: .word 0x1111
  127. .align 2
  128. PCCRL1_A: .long 0xFFFE3916
  129. PCCRL1_D: .word 0x1010
  130. .align 2
  131. PDCRL4_A: .long 0xFFFE3990
  132. PDCRL4_D: .word 0x0011
  133. .align 2
  134. PDCRL3_A: .long 0xFFFE3992
  135. PDCRL3_D: .word 0x00011
  136. .align 2
  137. PDCRL2_A: .long 0xFFFE3994
  138. PDCRL2_D: .word 0x1111
  139. .align 2
  140. PDCRL1_A: .long 0xFFFE3996
  141. PDCRL1_D: .word 0x1000
  142. .align 2
  143. CS3BCR_A: .long 0xFFFC0010
  144. CS3BCR_D: .long 0x00004400
  145. CS3WCR_A: .long 0xFFFC0034
  146. CS3WCR_D: .long 0x00002892
  147. SDCR_A: .long 0xFFFC004C
  148. SDCR_D: .long 0x00000809
  149. RTCOR_A: .long 0xFFFC0058
  150. RTCOR_D: .long 0xA55A0041
  151. RTCSR_A: .long 0xFFFC0050
  152. RTCSR_D: .long 0xa55a0010
  153. SDRAM_MODE: .long 0xFFFC5040
  154. REPEAT_D: .long 0x00009C40