socrates.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008
  4. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  5. *
  6. * Copyright 2004 Freescale Semiconductor.
  7. * (C) Copyright 2002,2003, Motorola Inc.
  8. * Xianghua Xiao, (X.Xiao@motorola.com)
  9. *
  10. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  11. */
  12. #include <common.h>
  13. #include <pci.h>
  14. #include <asm/processor.h>
  15. #include <asm/immap_85xx.h>
  16. #include <ioports.h>
  17. #include <flash.h>
  18. #include <linux/libfdt.h>
  19. #include <fdt_support.h>
  20. #include <asm/io.h>
  21. #include <i2c.h>
  22. #include <mb862xx.h>
  23. #include <video_fb.h>
  24. #include "upm_table.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. extern flash_info_t flash_info[]; /* FLASH chips info */
  27. extern GraphicDevice mb862xx;
  28. void local_bus_init (void);
  29. ulong flash_get_size (ulong base, int banknum);
  30. int checkboard (void)
  31. {
  32. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  33. char buf[64];
  34. int f;
  35. int i = env_get_f("serial#", buf, sizeof(buf));
  36. #ifdef CONFIG_PCI
  37. char *src;
  38. #endif
  39. puts("Board: Socrates");
  40. if (i > 0) {
  41. puts(", serial# ");
  42. puts(buf);
  43. }
  44. putc('\n');
  45. #ifdef CONFIG_PCI
  46. /* Check the PCI_clk sel bit */
  47. if (in_be32(&gur->porpllsr) & (1<<15)) {
  48. src = "SYSCLK";
  49. f = CONFIG_SYS_CLK_FREQ;
  50. } else {
  51. src = "PCI_CLK";
  52. f = CONFIG_PCI_CLK_FREQ;
  53. }
  54. printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
  55. #else
  56. printf ("PCI1: disabled\n");
  57. #endif
  58. /*
  59. * Initialize local bus.
  60. */
  61. local_bus_init ();
  62. return 0;
  63. }
  64. int misc_init_r (void)
  65. {
  66. /*
  67. * Adjust flash start and offset to detected values
  68. */
  69. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  70. gd->bd->bi_flashoffset = 0;
  71. /*
  72. * Check if boot FLASH isn't max size
  73. */
  74. if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
  75. set_lbc_or(0, gd->bd->bi_flashstart |
  76. (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
  77. set_lbc_br(0, gd->bd->bi_flashstart |
  78. (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
  79. /*
  80. * Re-check to get correct base address
  81. */
  82. flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
  83. }
  84. /*
  85. * Check if only one FLASH bank is available
  86. */
  87. if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
  88. set_lbc_or(1, 0);
  89. set_lbc_br(1, 0);
  90. /*
  91. * Re-do flash protection upon new addresses
  92. */
  93. flash_protect (FLAG_PROTECT_CLEAR,
  94. gd->bd->bi_flashstart, 0xffffffff,
  95. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  96. /* Monitor protection ON by default */
  97. flash_protect (FLAG_PROTECT_SET,
  98. CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
  99. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  100. /* Environment protection ON by default */
  101. flash_protect (FLAG_PROTECT_SET,
  102. CONFIG_ENV_ADDR,
  103. CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
  104. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  105. /* Redundant environment protection ON by default */
  106. flash_protect (FLAG_PROTECT_SET,
  107. CONFIG_ENV_ADDR_REDUND,
  108. CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
  109. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  110. }
  111. return 0;
  112. }
  113. /*
  114. * Initialize Local Bus
  115. */
  116. void local_bus_init (void)
  117. {
  118. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  119. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  120. sys_info_t sysinfo;
  121. uint clkdiv;
  122. uint lbc_mhz;
  123. uint lcrr = CONFIG_SYS_LBC_LCRR;
  124. get_sys_info (&sysinfo);
  125. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  126. lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
  127. /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
  128. if (lbc_mhz >= 66)
  129. lcrr &= ~LCRR_DBYP; /* DLL Enabled */
  130. else
  131. lcrr |= LCRR_DBYP; /* DLL Bypass */
  132. out_be32 (&lbc->lcrr, lcrr);
  133. asm ("sync;isync;msync");
  134. out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
  135. out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
  136. out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
  137. out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
  138. /* Init UPMA for FPGA access */
  139. out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
  140. upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
  141. /* Init UPMB for Lime controller access */
  142. out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
  143. upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
  144. }
  145. #if defined(CONFIG_PCI)
  146. /*
  147. * Initialize PCI Devices, report devices found.
  148. */
  149. #ifndef CONFIG_PCI_PNP
  150. static struct pci_config_table pci_mpc85xxads_config_table[] = {
  151. {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  152. PCI_IDSEL_NUMBER, PCI_ANY_ID,
  153. pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
  154. PCI_ENET0_MEMADDR,
  155. PCI_COMMAND_MEMORY |
  156. PCI_COMMAND_MASTER}},
  157. {}
  158. };
  159. #endif
  160. static struct pci_controller hose = {
  161. #ifndef CONFIG_PCI_PNP
  162. config_table:pci_mpc85xxads_config_table,
  163. #endif
  164. };
  165. #endif /* CONFIG_PCI */
  166. void pci_init_board (void)
  167. {
  168. #ifdef CONFIG_PCI
  169. pci_mpc85xx_init (&hose);
  170. #endif /* CONFIG_PCI */
  171. }
  172. #ifdef CONFIG_BOARD_EARLY_INIT_R
  173. int board_early_init_r (void)
  174. {
  175. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  176. /* set and reset the GPIO pin 2 which will reset the W83782G chip */
  177. out_8((unsigned char*)&gur->gpoutdr, 0x3F );
  178. out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
  179. udelay(200);
  180. out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
  181. return (0);
  182. }
  183. #endif /* CONFIG_BOARD_EARLY_INIT_R */
  184. #ifdef CONFIG_OF_BOARD_SETUP
  185. int ft_board_setup(void *blob, bd_t *bd)
  186. {
  187. u32 val[12];
  188. int rc, i = 0;
  189. ft_cpu_setup(blob, bd);
  190. /* Fixup NOR FLASH mapping */
  191. val[i++] = 0; /* chip select number */
  192. val[i++] = 0; /* always 0 */
  193. val[i++] = gd->bd->bi_flashstart;
  194. val[i++] = gd->bd->bi_flashsize;
  195. if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
  196. /* Fixup LIME mapping */
  197. val[i++] = 2; /* chip select number */
  198. val[i++] = 0; /* always 0 */
  199. val[i++] = CONFIG_SYS_LIME_BASE;
  200. val[i++] = CONFIG_SYS_LIME_SIZE;
  201. }
  202. /* Fixup FPGA mapping */
  203. val[i++] = 3; /* chip select number */
  204. val[i++] = 0; /* always 0 */
  205. val[i++] = CONFIG_SYS_FPGA_BASE;
  206. val[i++] = CONFIG_SYS_FPGA_SIZE;
  207. rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
  208. val, i * sizeof(u32), 1);
  209. if (rc)
  210. printf("Unable to update localbus ranges, err=%s\n",
  211. fdt_strerror(rc));
  212. return 0;
  213. }
  214. #endif /* CONFIG_OF_BOARD_SETUP */
  215. #define DEFAULT_BRIGHTNESS 25
  216. #define BACKLIGHT_ENABLE (1 << 31)
  217. static const gdc_regs init_regs [] =
  218. {
  219. {0x0100, 0x00010f00},
  220. {0x0020, 0x801901df},
  221. {0x0024, 0x00000000},
  222. {0x0028, 0x00000000},
  223. {0x002c, 0x00000000},
  224. {0x0110, 0x00000000},
  225. {0x0114, 0x00000000},
  226. {0x0118, 0x01df0320},
  227. {0x0004, 0x041f0000},
  228. {0x0008, 0x031f031f},
  229. {0x000c, 0x017f0349},
  230. {0x0010, 0x020c0000},
  231. {0x0014, 0x01df01e9},
  232. {0x0018, 0x00000000},
  233. {0x001c, 0x01e00320},
  234. {0x0100, 0x80010f00},
  235. {0x0, 0x0}
  236. };
  237. const gdc_regs *board_get_regs (void)
  238. {
  239. return init_regs;
  240. }
  241. int lime_probe(void)
  242. {
  243. uint cfg_br2;
  244. uint cfg_or2;
  245. int type;
  246. cfg_br2 = get_lbc_br(2);
  247. cfg_or2 = get_lbc_or(2);
  248. /* Configure GPCM for CS2 */
  249. set_lbc_br(2, 0);
  250. set_lbc_or(2, 0xfc000410);
  251. set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
  252. /* Get controller type */
  253. type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
  254. /* Restore previous CS2 configuration */
  255. set_lbc_br(2, 0);
  256. set_lbc_or(2, cfg_or2);
  257. set_lbc_br(2, cfg_br2);
  258. return (type == MB862XX_TYPE_LIME) ? 1 : 0;
  259. }
  260. /* Returns Lime base address */
  261. unsigned int board_video_init (void)
  262. {
  263. if (!lime_probe())
  264. return 0;
  265. mb862xx.winSizeX = 800;
  266. mb862xx.winSizeY = 480;
  267. mb862xx.gdfIndex = GDF_15BIT_555RGB;
  268. mb862xx.gdfBytesPP = 2;
  269. return CONFIG_SYS_LIME_BASE;
  270. }
  271. #define W83782D_REG_CFG 0x40
  272. #define W83782D_REG_BANK_SEL 0x4e
  273. #define W83782D_REG_ADCCLK 0x4b
  274. #define W83782D_REG_BEEP_CTRL 0x4d
  275. #define W83782D_REG_BEEP_CTRL2 0x57
  276. #define W83782D_REG_PWMOUT1 0x5b
  277. #define W83782D_REG_VBAT 0x5d
  278. static int w83782d_hwmon_init(void)
  279. {
  280. u8 buf;
  281. if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
  282. return -1;
  283. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
  284. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
  285. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
  286. buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
  287. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
  288. buf | 0x80);
  289. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
  290. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
  291. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
  292. buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
  293. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
  294. (buf & 0xf4) | 0x01);
  295. return 0;
  296. }
  297. static void board_backlight_brightness(int br)
  298. {
  299. u32 reg;
  300. u8 buf;
  301. u8 old_buf;
  302. /* Select bank 0 */
  303. if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
  304. goto err;
  305. else
  306. buf = old_buf & 0xf8;
  307. if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
  308. goto err;
  309. if (br > 0) {
  310. /* PWMOUT1 duty cycle ctrl */
  311. buf = 255 / (100 / br);
  312. if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
  313. goto err;
  314. /* LEDs on */
  315. reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
  316. if (!(reg & BACKLIGHT_ENABLE))
  317. out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
  318. reg | BACKLIGHT_ENABLE);
  319. } else {
  320. buf = 0;
  321. if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
  322. goto err;
  323. /* LEDs off */
  324. reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
  325. reg &= ~BACKLIGHT_ENABLE;
  326. out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
  327. }
  328. /* Restore previous bank setting */
  329. if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
  330. goto err;
  331. return;
  332. err:
  333. printf("W83782G I2C access failed\n");
  334. }
  335. void board_backlight_switch (int flag)
  336. {
  337. char * param;
  338. int rc;
  339. if (w83782d_hwmon_init())
  340. printf ("hwmon IC init failed\n");
  341. if (flag) {
  342. param = env_get("brightness");
  343. rc = param ? simple_strtol(param, NULL, 10) : -1;
  344. if (rc < 0)
  345. rc = DEFAULT_BRIGHTNESS;
  346. } else {
  347. rc = 0;
  348. }
  349. board_backlight_brightness(rc);
  350. }
  351. #if defined(CONFIG_CONSOLE_EXTRA_INFO)
  352. /*
  353. * Return text to be printed besides the logo.
  354. */
  355. void video_get_info_str (int line_number, char *info)
  356. {
  357. if (line_number == 1) {
  358. strcpy (info, " Board: Socrates");
  359. } else {
  360. info [0] = '\0';
  361. }
  362. }
  363. #endif