ark1668e-sysreg.h 1.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556
  1. #ifndef __ASM_ARCH_ARK1668E_SYSREG_H
  2. #define __ASM_ARCH_ARK1668E_SYSREG_H
  3. #include <asm/io.h>
  4. #define SYS_REG_BASE 0xe4900000
  5. #define SYS_CLK_SEL 0x40
  6. #define SYS_DEVICE_CLK_CFG1 0x64
  7. #define SYS_DEVICE_CLK_CFG3 0x6c
  8. #define SYS_PLLRFCK_CTL 0x14c
  9. #define SYS_CPUPLL_CFG 0x150
  10. #define SYS_SYSPLL_CFG 0x154
  11. #define SYS_AUDPLL_CFG 0x158
  12. #define SYS_DDR_IO_CFG 0x19c
  13. #define SYS_PAD_CTRL00 0x1c0
  14. #define SYS_PAD_CTRL01 0x1c4
  15. #define SYS_PAD_CTRL02 0x1c8
  16. #define SYS_PAD_CTRL03 0x1cc
  17. #define SYS_PAD_CTRL04 0x1d0
  18. #define SYS_PAD_CTRL05 0x1d4
  19. #define SYS_PAD_CTRL06 0x1d8
  20. #define SYS_PAD_CTRL07 0x1dc
  21. #define SYS_PAD_CTRL08 0x1e0
  22. #define SYS_PAD_CTRL09 0x1e4
  23. #define SYS_IO_DRIVER01 0x1f4
  24. #define SYS_IO_DRIVER02 0x1f8
  25. #define SYS_CPU_CFG2 0x208
  26. #define SYS_DEVICE_CLK_CFG6 0x22c
  27. #define SYS_CPUPLL_CFG_0 0x280
  28. #define SYS_CPUPLL_CFG_1 0x284
  29. #define SYS_CPUPLL_CFG_2 0x288
  30. #define SYS_LCDPLL_CFG_0 0x28c
  31. #define SYS_LCDPLL_CFG_1 0x290
  32. #define SYS_LCDPLL_CFG_2 0x294
  33. #define SYS_AXIPLL_CFG_0 0x298
  34. #define SYS_AHBPLL_CFG_0 0x29c
  35. #define SYS_APBPLL_CFG_0 0x2a0
  36. #define SYS_AUDPLL_CFG_0 0x2a4
  37. #define SYS_DDRPLL_CFG_0 0x2a8
  38. #define SYS_TVPLL_CFG_0 0x2ac
  39. #define SYS_MACPLL_CFG_0 0x2b4
  40. #define SYS_MACPLL_CFG_1 0x2b8
  41. #define SYS_MACPLL_CFG_2 0x2bc
  42. static inline volatile unsigned int read_sys_reg(int offset)
  43. {
  44. return readl(SYS_REG_BASE + offset);
  45. }
  46. static inline void write_sys_reg(unsigned int val, int offset)
  47. {
  48. writel(val, SYS_REG_BASE + offset);
  49. }
  50. #endif