regmap-irq.c 21 KB

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  1. /*
  2. * regmap based irq_chip
  3. *
  4. * Copyright 2011 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/device.h>
  13. #include <linux/export.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/regmap.h>
  19. #include <linux/slab.h>
  20. #include "internal.h"
  21. struct regmap_irq_chip_data {
  22. struct mutex lock;
  23. struct irq_chip irq_chip;
  24. struct regmap *map;
  25. const struct regmap_irq_chip *chip;
  26. int irq_base;
  27. struct irq_domain *domain;
  28. int irq;
  29. int wake_count;
  30. void *status_reg_buf;
  31. unsigned int *status_buf;
  32. unsigned int *mask_buf;
  33. unsigned int *mask_buf_def;
  34. unsigned int *wake_buf;
  35. unsigned int *type_buf;
  36. unsigned int *type_buf_def;
  37. unsigned int irq_reg_stride;
  38. unsigned int type_reg_stride;
  39. };
  40. static inline const
  41. struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
  42. int irq)
  43. {
  44. return &data->chip->irqs[irq];
  45. }
  46. static void regmap_irq_lock(struct irq_data *data)
  47. {
  48. struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  49. mutex_lock(&d->lock);
  50. }
  51. static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
  52. unsigned int reg, unsigned int mask,
  53. unsigned int val)
  54. {
  55. if (d->chip->mask_writeonly)
  56. return regmap_write_bits(d->map, reg, mask, val);
  57. else
  58. return regmap_update_bits(d->map, reg, mask, val);
  59. }
  60. static void regmap_irq_sync_unlock(struct irq_data *data)
  61. {
  62. struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  63. struct regmap *map = d->map;
  64. int i, ret;
  65. u32 reg;
  66. u32 unmask_offset;
  67. if (d->chip->runtime_pm) {
  68. ret = pm_runtime_get_sync(map->dev);
  69. if (ret < 0)
  70. dev_err(map->dev, "IRQ sync failed to resume: %d\n",
  71. ret);
  72. }
  73. /*
  74. * If there's been a change in the mask write it back to the
  75. * hardware. We rely on the use of the regmap core cache to
  76. * suppress pointless writes.
  77. */
  78. for (i = 0; i < d->chip->num_regs; i++) {
  79. if (!d->chip->mask_base)
  80. continue;
  81. reg = d->chip->mask_base +
  82. (i * map->reg_stride * d->irq_reg_stride);
  83. if (d->chip->mask_invert) {
  84. ret = regmap_irq_update_bits(d, reg,
  85. d->mask_buf_def[i], ~d->mask_buf[i]);
  86. } else if (d->chip->unmask_base) {
  87. /* set mask with mask_base register */
  88. ret = regmap_irq_update_bits(d, reg,
  89. d->mask_buf_def[i], ~d->mask_buf[i]);
  90. if (ret < 0)
  91. dev_err(d->map->dev,
  92. "Failed to sync unmasks in %x\n",
  93. reg);
  94. unmask_offset = d->chip->unmask_base -
  95. d->chip->mask_base;
  96. /* clear mask with unmask_base register */
  97. ret = regmap_irq_update_bits(d,
  98. reg + unmask_offset,
  99. d->mask_buf_def[i],
  100. d->mask_buf[i]);
  101. } else {
  102. ret = regmap_irq_update_bits(d, reg,
  103. d->mask_buf_def[i], d->mask_buf[i]);
  104. }
  105. if (ret != 0)
  106. dev_err(d->map->dev, "Failed to sync masks in %x\n",
  107. reg);
  108. reg = d->chip->wake_base +
  109. (i * map->reg_stride * d->irq_reg_stride);
  110. if (d->wake_buf) {
  111. if (d->chip->wake_invert)
  112. ret = regmap_irq_update_bits(d, reg,
  113. d->mask_buf_def[i],
  114. ~d->wake_buf[i]);
  115. else
  116. ret = regmap_irq_update_bits(d, reg,
  117. d->mask_buf_def[i],
  118. d->wake_buf[i]);
  119. if (ret != 0)
  120. dev_err(d->map->dev,
  121. "Failed to sync wakes in %x: %d\n",
  122. reg, ret);
  123. }
  124. if (!d->chip->init_ack_masked)
  125. continue;
  126. /*
  127. * Ack all the masked interrupts unconditionally,
  128. * OR if there is masked interrupt which hasn't been Acked,
  129. * it'll be ignored in irq handler, then may introduce irq storm
  130. */
  131. if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
  132. reg = d->chip->ack_base +
  133. (i * map->reg_stride * d->irq_reg_stride);
  134. /* some chips ack by write 0 */
  135. if (d->chip->ack_invert)
  136. ret = regmap_write(map, reg, ~d->mask_buf[i]);
  137. else
  138. ret = regmap_write(map, reg, d->mask_buf[i]);
  139. if (ret != 0)
  140. dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
  141. reg, ret);
  142. }
  143. }
  144. for (i = 0; i < d->chip->num_type_reg; i++) {
  145. if (!d->type_buf_def[i])
  146. continue;
  147. reg = d->chip->type_base +
  148. (i * map->reg_stride * d->type_reg_stride);
  149. if (d->chip->type_invert)
  150. ret = regmap_irq_update_bits(d, reg,
  151. d->type_buf_def[i], ~d->type_buf[i]);
  152. else
  153. ret = regmap_irq_update_bits(d, reg,
  154. d->type_buf_def[i], d->type_buf[i]);
  155. if (ret != 0)
  156. dev_err(d->map->dev, "Failed to sync type in %x\n",
  157. reg);
  158. }
  159. if (d->chip->runtime_pm)
  160. pm_runtime_put(map->dev);
  161. /* If we've changed our wakeup count propagate it to the parent */
  162. if (d->wake_count < 0)
  163. for (i = d->wake_count; i < 0; i++)
  164. irq_set_irq_wake(d->irq, 0);
  165. else if (d->wake_count > 0)
  166. for (i = 0; i < d->wake_count; i++)
  167. irq_set_irq_wake(d->irq, 1);
  168. d->wake_count = 0;
  169. mutex_unlock(&d->lock);
  170. }
  171. static void regmap_irq_enable(struct irq_data *data)
  172. {
  173. struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  174. struct regmap *map = d->map;
  175. const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
  176. d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
  177. }
  178. static void regmap_irq_disable(struct irq_data *data)
  179. {
  180. struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  181. struct regmap *map = d->map;
  182. const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
  183. d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
  184. }
  185. static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
  186. {
  187. struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  188. struct regmap *map = d->map;
  189. const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
  190. int reg = irq_data->type_reg_offset / map->reg_stride;
  191. if (!(irq_data->type_rising_mask | irq_data->type_falling_mask))
  192. return 0;
  193. d->type_buf[reg] &= ~(irq_data->type_falling_mask |
  194. irq_data->type_rising_mask);
  195. switch (type) {
  196. case IRQ_TYPE_EDGE_FALLING:
  197. d->type_buf[reg] |= irq_data->type_falling_mask;
  198. break;
  199. case IRQ_TYPE_EDGE_RISING:
  200. d->type_buf[reg] |= irq_data->type_rising_mask;
  201. break;
  202. case IRQ_TYPE_EDGE_BOTH:
  203. d->type_buf[reg] |= (irq_data->type_falling_mask |
  204. irq_data->type_rising_mask);
  205. break;
  206. default:
  207. return -EINVAL;
  208. }
  209. return 0;
  210. }
  211. static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
  212. {
  213. struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  214. struct regmap *map = d->map;
  215. const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
  216. if (on) {
  217. if (d->wake_buf)
  218. d->wake_buf[irq_data->reg_offset / map->reg_stride]
  219. &= ~irq_data->mask;
  220. d->wake_count++;
  221. } else {
  222. if (d->wake_buf)
  223. d->wake_buf[irq_data->reg_offset / map->reg_stride]
  224. |= irq_data->mask;
  225. d->wake_count--;
  226. }
  227. return 0;
  228. }
  229. static const struct irq_chip regmap_irq_chip = {
  230. .irq_bus_lock = regmap_irq_lock,
  231. .irq_bus_sync_unlock = regmap_irq_sync_unlock,
  232. .irq_disable = regmap_irq_disable,
  233. .irq_enable = regmap_irq_enable,
  234. .irq_set_type = regmap_irq_set_type,
  235. .irq_set_wake = regmap_irq_set_wake,
  236. };
  237. static irqreturn_t regmap_irq_thread(int irq, void *d)
  238. {
  239. struct regmap_irq_chip_data *data = d;
  240. const struct regmap_irq_chip *chip = data->chip;
  241. struct regmap *map = data->map;
  242. int ret, i;
  243. bool handled = false;
  244. u32 reg;
  245. if (chip->handle_pre_irq)
  246. chip->handle_pre_irq(chip->irq_drv_data);
  247. if (chip->runtime_pm) {
  248. ret = pm_runtime_get_sync(map->dev);
  249. if (ret < 0) {
  250. dev_err(map->dev, "IRQ thread failed to resume: %d\n",
  251. ret);
  252. pm_runtime_put(map->dev);
  253. goto exit;
  254. }
  255. }
  256. /*
  257. * Read in the statuses, using a single bulk read if possible
  258. * in order to reduce the I/O overheads.
  259. */
  260. if (!map->use_single_read && map->reg_stride == 1 &&
  261. data->irq_reg_stride == 1) {
  262. u8 *buf8 = data->status_reg_buf;
  263. u16 *buf16 = data->status_reg_buf;
  264. u32 *buf32 = data->status_reg_buf;
  265. BUG_ON(!data->status_reg_buf);
  266. ret = regmap_bulk_read(map, chip->status_base,
  267. data->status_reg_buf,
  268. chip->num_regs);
  269. if (ret != 0) {
  270. dev_err(map->dev, "Failed to read IRQ status: %d\n",
  271. ret);
  272. goto exit;
  273. }
  274. for (i = 0; i < data->chip->num_regs; i++) {
  275. switch (map->format.val_bytes) {
  276. case 1:
  277. data->status_buf[i] = buf8[i];
  278. break;
  279. case 2:
  280. data->status_buf[i] = buf16[i];
  281. break;
  282. case 4:
  283. data->status_buf[i] = buf32[i];
  284. break;
  285. default:
  286. BUG();
  287. goto exit;
  288. }
  289. }
  290. } else {
  291. for (i = 0; i < data->chip->num_regs; i++) {
  292. ret = regmap_read(map, chip->status_base +
  293. (i * map->reg_stride
  294. * data->irq_reg_stride),
  295. &data->status_buf[i]);
  296. if (ret != 0) {
  297. dev_err(map->dev,
  298. "Failed to read IRQ status: %d\n",
  299. ret);
  300. if (chip->runtime_pm)
  301. pm_runtime_put(map->dev);
  302. goto exit;
  303. }
  304. }
  305. }
  306. /*
  307. * Ignore masked IRQs and ack if we need to; we ack early so
  308. * there is no race between handling and acknowleding the
  309. * interrupt. We assume that typically few of the interrupts
  310. * will fire simultaneously so don't worry about overhead from
  311. * doing a write per register.
  312. */
  313. for (i = 0; i < data->chip->num_regs; i++) {
  314. data->status_buf[i] &= ~data->mask_buf[i];
  315. if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
  316. reg = chip->ack_base +
  317. (i * map->reg_stride * data->irq_reg_stride);
  318. ret = regmap_write(map, reg, data->status_buf[i]);
  319. if (ret != 0)
  320. dev_err(map->dev, "Failed to ack 0x%x: %d\n",
  321. reg, ret);
  322. }
  323. }
  324. for (i = 0; i < chip->num_irqs; i++) {
  325. if (data->status_buf[chip->irqs[i].reg_offset /
  326. map->reg_stride] & chip->irqs[i].mask) {
  327. handle_nested_irq(irq_find_mapping(data->domain, i));
  328. handled = true;
  329. }
  330. }
  331. if (chip->runtime_pm)
  332. pm_runtime_put(map->dev);
  333. exit:
  334. if (chip->handle_post_irq)
  335. chip->handle_post_irq(chip->irq_drv_data);
  336. if (handled)
  337. return IRQ_HANDLED;
  338. else
  339. return IRQ_NONE;
  340. }
  341. static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
  342. irq_hw_number_t hw)
  343. {
  344. struct regmap_irq_chip_data *data = h->host_data;
  345. irq_set_chip_data(virq, data);
  346. irq_set_chip(virq, &data->irq_chip);
  347. irq_set_nested_thread(virq, 1);
  348. irq_set_parent(virq, data->irq);
  349. irq_set_noprobe(virq);
  350. return 0;
  351. }
  352. static const struct irq_domain_ops regmap_domain_ops = {
  353. .map = regmap_irq_map,
  354. .xlate = irq_domain_xlate_onetwocell,
  355. };
  356. /**
  357. * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
  358. *
  359. * @map: The regmap for the device.
  360. * @irq: The IRQ the device uses to signal interrupts.
  361. * @irq_flags: The IRQF_ flags to use for the primary interrupt.
  362. * @irq_base: Allocate at specific IRQ number if irq_base > 0.
  363. * @chip: Configuration for the interrupt controller.
  364. * @data: Runtime data structure for the controller, allocated on success.
  365. *
  366. * Returns 0 on success or an errno on failure.
  367. *
  368. * In order for this to be efficient the chip really should use a
  369. * register cache. The chip driver is responsible for restoring the
  370. * register values used by the IRQ controller over suspend and resume.
  371. */
  372. int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
  373. int irq_base, const struct regmap_irq_chip *chip,
  374. struct regmap_irq_chip_data **data)
  375. {
  376. struct regmap_irq_chip_data *d;
  377. int i;
  378. int ret = -ENOMEM;
  379. u32 reg;
  380. u32 unmask_offset;
  381. if (chip->num_regs <= 0)
  382. return -EINVAL;
  383. for (i = 0; i < chip->num_irqs; i++) {
  384. if (chip->irqs[i].reg_offset % map->reg_stride)
  385. return -EINVAL;
  386. if (chip->irqs[i].reg_offset / map->reg_stride >=
  387. chip->num_regs)
  388. return -EINVAL;
  389. }
  390. if (irq_base) {
  391. irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
  392. if (irq_base < 0) {
  393. dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
  394. irq_base);
  395. return irq_base;
  396. }
  397. }
  398. d = kzalloc(sizeof(*d), GFP_KERNEL);
  399. if (!d)
  400. return -ENOMEM;
  401. d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
  402. GFP_KERNEL);
  403. if (!d->status_buf)
  404. goto err_alloc;
  405. d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
  406. GFP_KERNEL);
  407. if (!d->mask_buf)
  408. goto err_alloc;
  409. d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
  410. GFP_KERNEL);
  411. if (!d->mask_buf_def)
  412. goto err_alloc;
  413. if (chip->wake_base) {
  414. d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
  415. GFP_KERNEL);
  416. if (!d->wake_buf)
  417. goto err_alloc;
  418. }
  419. if (chip->num_type_reg) {
  420. d->type_buf_def = kcalloc(chip->num_type_reg,
  421. sizeof(unsigned int), GFP_KERNEL);
  422. if (!d->type_buf_def)
  423. goto err_alloc;
  424. d->type_buf = kcalloc(chip->num_type_reg, sizeof(unsigned int),
  425. GFP_KERNEL);
  426. if (!d->type_buf)
  427. goto err_alloc;
  428. }
  429. d->irq_chip = regmap_irq_chip;
  430. d->irq_chip.name = chip->name;
  431. d->irq = irq;
  432. d->map = map;
  433. d->chip = chip;
  434. d->irq_base = irq_base;
  435. if (chip->irq_reg_stride)
  436. d->irq_reg_stride = chip->irq_reg_stride;
  437. else
  438. d->irq_reg_stride = 1;
  439. if (chip->type_reg_stride)
  440. d->type_reg_stride = chip->type_reg_stride;
  441. else
  442. d->type_reg_stride = 1;
  443. if (!map->use_single_read && map->reg_stride == 1 &&
  444. d->irq_reg_stride == 1) {
  445. d->status_reg_buf = kmalloc_array(chip->num_regs,
  446. map->format.val_bytes,
  447. GFP_KERNEL);
  448. if (!d->status_reg_buf)
  449. goto err_alloc;
  450. }
  451. mutex_init(&d->lock);
  452. for (i = 0; i < chip->num_irqs; i++)
  453. d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
  454. |= chip->irqs[i].mask;
  455. /* Mask all the interrupts by default */
  456. for (i = 0; i < chip->num_regs; i++) {
  457. d->mask_buf[i] = d->mask_buf_def[i];
  458. if (!chip->mask_base)
  459. continue;
  460. reg = chip->mask_base +
  461. (i * map->reg_stride * d->irq_reg_stride);
  462. if (chip->mask_invert)
  463. ret = regmap_irq_update_bits(d, reg,
  464. d->mask_buf[i], ~d->mask_buf[i]);
  465. else if (d->chip->unmask_base) {
  466. unmask_offset = d->chip->unmask_base -
  467. d->chip->mask_base;
  468. ret = regmap_irq_update_bits(d,
  469. reg + unmask_offset,
  470. d->mask_buf[i],
  471. d->mask_buf[i]);
  472. } else
  473. ret = regmap_irq_update_bits(d, reg,
  474. d->mask_buf[i], d->mask_buf[i]);
  475. if (ret != 0) {
  476. dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
  477. reg, ret);
  478. goto err_alloc;
  479. }
  480. if (!chip->init_ack_masked)
  481. continue;
  482. /* Ack masked but set interrupts */
  483. reg = chip->status_base +
  484. (i * map->reg_stride * d->irq_reg_stride);
  485. ret = regmap_read(map, reg, &d->status_buf[i]);
  486. if (ret != 0) {
  487. dev_err(map->dev, "Failed to read IRQ status: %d\n",
  488. ret);
  489. goto err_alloc;
  490. }
  491. if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
  492. reg = chip->ack_base +
  493. (i * map->reg_stride * d->irq_reg_stride);
  494. if (chip->ack_invert)
  495. ret = regmap_write(map, reg,
  496. ~(d->status_buf[i] & d->mask_buf[i]));
  497. else
  498. ret = regmap_write(map, reg,
  499. d->status_buf[i] & d->mask_buf[i]);
  500. if (ret != 0) {
  501. dev_err(map->dev, "Failed to ack 0x%x: %d\n",
  502. reg, ret);
  503. goto err_alloc;
  504. }
  505. }
  506. }
  507. /* Wake is disabled by default */
  508. if (d->wake_buf) {
  509. for (i = 0; i < chip->num_regs; i++) {
  510. d->wake_buf[i] = d->mask_buf_def[i];
  511. reg = chip->wake_base +
  512. (i * map->reg_stride * d->irq_reg_stride);
  513. if (chip->wake_invert)
  514. ret = regmap_irq_update_bits(d, reg,
  515. d->mask_buf_def[i],
  516. 0);
  517. else
  518. ret = regmap_irq_update_bits(d, reg,
  519. d->mask_buf_def[i],
  520. d->wake_buf[i]);
  521. if (ret != 0) {
  522. dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
  523. reg, ret);
  524. goto err_alloc;
  525. }
  526. }
  527. }
  528. if (chip->num_type_reg) {
  529. for (i = 0; i < chip->num_irqs; i++) {
  530. reg = chip->irqs[i].type_reg_offset / map->reg_stride;
  531. d->type_buf_def[reg] |= chip->irqs[i].type_rising_mask |
  532. chip->irqs[i].type_falling_mask;
  533. }
  534. for (i = 0; i < chip->num_type_reg; ++i) {
  535. if (!d->type_buf_def[i])
  536. continue;
  537. reg = chip->type_base +
  538. (i * map->reg_stride * d->type_reg_stride);
  539. if (chip->type_invert)
  540. ret = regmap_irq_update_bits(d, reg,
  541. d->type_buf_def[i], 0xFF);
  542. else
  543. ret = regmap_irq_update_bits(d, reg,
  544. d->type_buf_def[i], 0x0);
  545. if (ret != 0) {
  546. dev_err(map->dev,
  547. "Failed to set type in 0x%x: %x\n",
  548. reg, ret);
  549. goto err_alloc;
  550. }
  551. }
  552. }
  553. if (irq_base)
  554. d->domain = irq_domain_add_legacy(map->dev->of_node,
  555. chip->num_irqs, irq_base, 0,
  556. &regmap_domain_ops, d);
  557. else
  558. d->domain = irq_domain_add_linear(map->dev->of_node,
  559. chip->num_irqs,
  560. &regmap_domain_ops, d);
  561. if (!d->domain) {
  562. dev_err(map->dev, "Failed to create IRQ domain\n");
  563. ret = -ENOMEM;
  564. goto err_alloc;
  565. }
  566. ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
  567. irq_flags | IRQF_ONESHOT,
  568. chip->name, d);
  569. if (ret != 0) {
  570. dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
  571. irq, chip->name, ret);
  572. goto err_domain;
  573. }
  574. *data = d;
  575. return 0;
  576. err_domain:
  577. /* Should really dispose of the domain but... */
  578. err_alloc:
  579. kfree(d->type_buf);
  580. kfree(d->type_buf_def);
  581. kfree(d->wake_buf);
  582. kfree(d->mask_buf_def);
  583. kfree(d->mask_buf);
  584. kfree(d->status_buf);
  585. kfree(d->status_reg_buf);
  586. kfree(d);
  587. return ret;
  588. }
  589. EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
  590. /**
  591. * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
  592. *
  593. * @irq: Primary IRQ for the device
  594. * @d: &regmap_irq_chip_data allocated by regmap_add_irq_chip()
  595. *
  596. * This function also disposes of all mapped IRQs on the chip.
  597. */
  598. void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
  599. {
  600. unsigned int virq;
  601. int hwirq;
  602. if (!d)
  603. return;
  604. free_irq(irq, d);
  605. /* Dispose all virtual irq from irq domain before removing it */
  606. for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
  607. /* Ignore hwirq if holes in the IRQ list */
  608. if (!d->chip->irqs[hwirq].mask)
  609. continue;
  610. /*
  611. * Find the virtual irq of hwirq on chip and if it is
  612. * there then dispose it
  613. */
  614. virq = irq_find_mapping(d->domain, hwirq);
  615. if (virq)
  616. irq_dispose_mapping(virq);
  617. }
  618. irq_domain_remove(d->domain);
  619. kfree(d->type_buf);
  620. kfree(d->type_buf_def);
  621. kfree(d->wake_buf);
  622. kfree(d->mask_buf_def);
  623. kfree(d->mask_buf);
  624. kfree(d->status_reg_buf);
  625. kfree(d->status_buf);
  626. kfree(d);
  627. }
  628. EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
  629. static void devm_regmap_irq_chip_release(struct device *dev, void *res)
  630. {
  631. struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
  632. regmap_del_irq_chip(d->irq, d);
  633. }
  634. static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
  635. {
  636. struct regmap_irq_chip_data **r = res;
  637. if (!r || !*r) {
  638. WARN_ON(!r || !*r);
  639. return 0;
  640. }
  641. return *r == data;
  642. }
  643. /**
  644. * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
  645. *
  646. * @dev: The device pointer on which irq_chip belongs to.
  647. * @map: The regmap for the device.
  648. * @irq: The IRQ the device uses to signal interrupts
  649. * @irq_flags: The IRQF_ flags to use for the primary interrupt.
  650. * @irq_base: Allocate at specific IRQ number if irq_base > 0.
  651. * @chip: Configuration for the interrupt controller.
  652. * @data: Runtime data structure for the controller, allocated on success
  653. *
  654. * Returns 0 on success or an errno on failure.
  655. *
  656. * The &regmap_irq_chip_data will be automatically released when the device is
  657. * unbound.
  658. */
  659. int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
  660. int irq_flags, int irq_base,
  661. const struct regmap_irq_chip *chip,
  662. struct regmap_irq_chip_data **data)
  663. {
  664. struct regmap_irq_chip_data **ptr, *d;
  665. int ret;
  666. ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
  667. GFP_KERNEL);
  668. if (!ptr)
  669. return -ENOMEM;
  670. ret = regmap_add_irq_chip(map, irq, irq_flags, irq_base,
  671. chip, &d);
  672. if (ret < 0) {
  673. devres_free(ptr);
  674. return ret;
  675. }
  676. *ptr = d;
  677. devres_add(dev, ptr);
  678. *data = d;
  679. return 0;
  680. }
  681. EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
  682. /**
  683. * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
  684. *
  685. * @dev: Device for which which resource was allocated.
  686. * @irq: Primary IRQ for the device.
  687. * @data: &regmap_irq_chip_data allocated by regmap_add_irq_chip().
  688. *
  689. * A resource managed version of regmap_del_irq_chip().
  690. */
  691. void devm_regmap_del_irq_chip(struct device *dev, int irq,
  692. struct regmap_irq_chip_data *data)
  693. {
  694. int rc;
  695. WARN_ON(irq != data->irq);
  696. rc = devres_release(dev, devm_regmap_irq_chip_release,
  697. devm_regmap_irq_chip_match, data);
  698. if (rc != 0)
  699. WARN_ON(rc);
  700. }
  701. EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
  702. /**
  703. * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
  704. *
  705. * @data: regmap irq controller to operate on.
  706. *
  707. * Useful for drivers to request their own IRQs.
  708. */
  709. int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
  710. {
  711. WARN_ON(!data->irq_base);
  712. return data->irq_base;
  713. }
  714. EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
  715. /**
  716. * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
  717. *
  718. * @data: regmap irq controller to operate on.
  719. * @irq: index of the interrupt requested in the chip IRQs.
  720. *
  721. * Useful for drivers to request their own IRQs.
  722. */
  723. int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
  724. {
  725. /* Handle holes in the IRQ list */
  726. if (!data->chip->irqs[irq].mask)
  727. return -EINVAL;
  728. return irq_create_mapping(data->domain, irq);
  729. }
  730. EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
  731. /**
  732. * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
  733. *
  734. * @data: regmap_irq controller to operate on.
  735. *
  736. * Useful for drivers to request their own IRQs and for integration
  737. * with subsystems. For ease of integration NULL is accepted as a
  738. * domain, allowing devices to just call this even if no domain is
  739. * allocated.
  740. */
  741. struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
  742. {
  743. if (data)
  744. return data->domain;
  745. else
  746. return NULL;
  747. }
  748. EXPORT_SYMBOL_GPL(regmap_irq_get_domain);