tpm_crb.c 18 KB

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  1. /*
  2. * Copyright (C) 2014 Intel Corporation
  3. *
  4. * Authors:
  5. * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
  6. *
  7. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  8. *
  9. * This device driver implements the TPM interface as defined in
  10. * the TCG CRB 2.0 TPM specification.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; version 2
  15. * of the License.
  16. */
  17. #include <linux/acpi.h>
  18. #include <linux/highmem.h>
  19. #include <linux/rculist.h>
  20. #include <linux/module.h>
  21. #include <linux/pm_runtime.h>
  22. #ifdef CONFIG_ARM64
  23. #include <linux/arm-smccc.h>
  24. #endif
  25. #include "tpm.h"
  26. #define ACPI_SIG_TPM2 "TPM2"
  27. #define TPM_CRB_MAX_RESOURCES 3
  28. static const guid_t crb_acpi_start_guid =
  29. GUID_INIT(0x6BBF6CAB, 0x5463, 0x4714,
  30. 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4);
  31. enum crb_defaults {
  32. CRB_ACPI_START_REVISION_ID = 1,
  33. CRB_ACPI_START_INDEX = 1,
  34. };
  35. enum crb_loc_ctrl {
  36. CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0),
  37. CRB_LOC_CTRL_RELINQUISH = BIT(1),
  38. };
  39. enum crb_loc_state {
  40. CRB_LOC_STATE_LOC_ASSIGNED = BIT(1),
  41. CRB_LOC_STATE_TPM_REG_VALID_STS = BIT(7),
  42. };
  43. enum crb_ctrl_req {
  44. CRB_CTRL_REQ_CMD_READY = BIT(0),
  45. CRB_CTRL_REQ_GO_IDLE = BIT(1),
  46. };
  47. enum crb_ctrl_sts {
  48. CRB_CTRL_STS_ERROR = BIT(0),
  49. CRB_CTRL_STS_TPM_IDLE = BIT(1),
  50. };
  51. enum crb_start {
  52. CRB_START_INVOKE = BIT(0),
  53. };
  54. enum crb_cancel {
  55. CRB_CANCEL_INVOKE = BIT(0),
  56. };
  57. struct crb_regs_head {
  58. u32 loc_state;
  59. u32 reserved1;
  60. u32 loc_ctrl;
  61. u32 loc_sts;
  62. u8 reserved2[32];
  63. u64 intf_id;
  64. u64 ctrl_ext;
  65. } __packed;
  66. struct crb_regs_tail {
  67. u32 ctrl_req;
  68. u32 ctrl_sts;
  69. u32 ctrl_cancel;
  70. u32 ctrl_start;
  71. u32 ctrl_int_enable;
  72. u32 ctrl_int_sts;
  73. u32 ctrl_cmd_size;
  74. u32 ctrl_cmd_pa_low;
  75. u32 ctrl_cmd_pa_high;
  76. u32 ctrl_rsp_size;
  77. u64 ctrl_rsp_pa;
  78. } __packed;
  79. enum crb_status {
  80. CRB_DRV_STS_COMPLETE = BIT(0),
  81. };
  82. struct crb_priv {
  83. u32 sm;
  84. const char *hid;
  85. struct crb_regs_head __iomem *regs_h;
  86. struct crb_regs_tail __iomem *regs_t;
  87. u8 __iomem *cmd;
  88. u8 __iomem *rsp;
  89. u32 cmd_size;
  90. u32 smc_func_id;
  91. };
  92. struct tpm2_crb_smc {
  93. u32 interrupt;
  94. u8 interrupt_flags;
  95. u8 op_flags;
  96. u16 reserved2;
  97. u32 smc_func_id;
  98. };
  99. static bool crb_wait_for_reg_32(u32 __iomem *reg, u32 mask, u32 value,
  100. unsigned long timeout)
  101. {
  102. ktime_t start;
  103. ktime_t stop;
  104. start = ktime_get();
  105. stop = ktime_add(start, ms_to_ktime(timeout));
  106. do {
  107. if ((ioread32(reg) & mask) == value)
  108. return true;
  109. usleep_range(50, 100);
  110. } while (ktime_before(ktime_get(), stop));
  111. return ((ioread32(reg) & mask) == value);
  112. }
  113. /**
  114. * __crb_go_idle - request tpm crb device to go the idle state
  115. *
  116. * @dev: crb device
  117. * @priv: crb private data
  118. *
  119. * Write CRB_CTRL_REQ_GO_IDLE to TPM_CRB_CTRL_REQ
  120. * The device should respond within TIMEOUT_C by clearing the bit.
  121. * Anyhow, we do not wait here as a consequent CMD_READY request
  122. * will be handled correctly even if idle was not completed.
  123. *
  124. * The function does nothing for devices with ACPI-start method
  125. * or SMC-start method.
  126. *
  127. * Return: 0 always
  128. */
  129. static int __crb_go_idle(struct device *dev, struct crb_priv *priv)
  130. {
  131. if ((priv->sm == ACPI_TPM2_START_METHOD) ||
  132. (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD) ||
  133. (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC))
  134. return 0;
  135. iowrite32(CRB_CTRL_REQ_GO_IDLE, &priv->regs_t->ctrl_req);
  136. if (!crb_wait_for_reg_32(&priv->regs_t->ctrl_req,
  137. CRB_CTRL_REQ_GO_IDLE/* mask */,
  138. 0, /* value */
  139. TPM2_TIMEOUT_C)) {
  140. dev_warn(dev, "goIdle timed out\n");
  141. return -ETIME;
  142. }
  143. return 0;
  144. }
  145. static int crb_go_idle(struct tpm_chip *chip)
  146. {
  147. struct device *dev = &chip->dev;
  148. struct crb_priv *priv = dev_get_drvdata(dev);
  149. return __crb_go_idle(dev, priv);
  150. }
  151. /**
  152. * __crb_cmd_ready - request tpm crb device to enter ready state
  153. *
  154. * @dev: crb device
  155. * @priv: crb private data
  156. *
  157. * Write CRB_CTRL_REQ_CMD_READY to TPM_CRB_CTRL_REQ
  158. * and poll till the device acknowledge it by clearing the bit.
  159. * The device should respond within TIMEOUT_C.
  160. *
  161. * The function does nothing for devices with ACPI-start method
  162. * or SMC-start method.
  163. *
  164. * Return: 0 on success -ETIME on timeout;
  165. */
  166. static int __crb_cmd_ready(struct device *dev, struct crb_priv *priv)
  167. {
  168. if ((priv->sm == ACPI_TPM2_START_METHOD) ||
  169. (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD) ||
  170. (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC))
  171. return 0;
  172. iowrite32(CRB_CTRL_REQ_CMD_READY, &priv->regs_t->ctrl_req);
  173. if (!crb_wait_for_reg_32(&priv->regs_t->ctrl_req,
  174. CRB_CTRL_REQ_CMD_READY /* mask */,
  175. 0, /* value */
  176. TPM2_TIMEOUT_C)) {
  177. dev_warn(dev, "cmdReady timed out\n");
  178. return -ETIME;
  179. }
  180. return 0;
  181. }
  182. static int crb_cmd_ready(struct tpm_chip *chip)
  183. {
  184. struct device *dev = &chip->dev;
  185. struct crb_priv *priv = dev_get_drvdata(dev);
  186. return __crb_cmd_ready(dev, priv);
  187. }
  188. static int __crb_request_locality(struct device *dev,
  189. struct crb_priv *priv, int loc)
  190. {
  191. u32 value = CRB_LOC_STATE_LOC_ASSIGNED |
  192. CRB_LOC_STATE_TPM_REG_VALID_STS;
  193. if (!priv->regs_h)
  194. return 0;
  195. iowrite32(CRB_LOC_CTRL_REQUEST_ACCESS, &priv->regs_h->loc_ctrl);
  196. if (!crb_wait_for_reg_32(&priv->regs_h->loc_state, value, value,
  197. TPM2_TIMEOUT_C)) {
  198. dev_warn(dev, "TPM_LOC_STATE_x.requestAccess timed out\n");
  199. return -ETIME;
  200. }
  201. return 0;
  202. }
  203. static int crb_request_locality(struct tpm_chip *chip, int loc)
  204. {
  205. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  206. return __crb_request_locality(&chip->dev, priv, loc);
  207. }
  208. static int __crb_relinquish_locality(struct device *dev,
  209. struct crb_priv *priv, int loc)
  210. {
  211. u32 mask = CRB_LOC_STATE_LOC_ASSIGNED |
  212. CRB_LOC_STATE_TPM_REG_VALID_STS;
  213. u32 value = CRB_LOC_STATE_TPM_REG_VALID_STS;
  214. if (!priv->regs_h)
  215. return 0;
  216. iowrite32(CRB_LOC_CTRL_RELINQUISH, &priv->regs_h->loc_ctrl);
  217. if (!crb_wait_for_reg_32(&priv->regs_h->loc_state, mask, value,
  218. TPM2_TIMEOUT_C)) {
  219. dev_warn(dev, "TPM_LOC_STATE_x.requestAccess timed out\n");
  220. return -ETIME;
  221. }
  222. return 0;
  223. }
  224. static int crb_relinquish_locality(struct tpm_chip *chip, int loc)
  225. {
  226. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  227. return __crb_relinquish_locality(&chip->dev, priv, loc);
  228. }
  229. static u8 crb_status(struct tpm_chip *chip)
  230. {
  231. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  232. u8 sts = 0;
  233. if ((ioread32(&priv->regs_t->ctrl_start) & CRB_START_INVOKE) !=
  234. CRB_START_INVOKE)
  235. sts |= CRB_DRV_STS_COMPLETE;
  236. return sts;
  237. }
  238. static int crb_recv(struct tpm_chip *chip, u8 *buf, size_t count)
  239. {
  240. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  241. unsigned int expected;
  242. /* A sanity check that the upper layer wants to get at least the header
  243. * as that is the minimum size for any TPM response.
  244. */
  245. if (count < TPM_HEADER_SIZE)
  246. return -EIO;
  247. /* If this bit is set, according to the spec, the TPM is in
  248. * unrecoverable condition.
  249. */
  250. if (ioread32(&priv->regs_t->ctrl_sts) & CRB_CTRL_STS_ERROR)
  251. return -EIO;
  252. /* Read the first 8 bytes in order to get the length of the response.
  253. * We read exactly a quad word in order to make sure that the remaining
  254. * reads will be aligned.
  255. */
  256. memcpy_fromio(buf, priv->rsp, 8);
  257. expected = be32_to_cpup((__be32 *)&buf[2]);
  258. if (expected > count || expected < TPM_HEADER_SIZE)
  259. return -EIO;
  260. memcpy_fromio(&buf[8], &priv->rsp[8], expected - 8);
  261. return expected;
  262. }
  263. static int crb_do_acpi_start(struct tpm_chip *chip)
  264. {
  265. union acpi_object *obj;
  266. int rc;
  267. obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
  268. &crb_acpi_start_guid,
  269. CRB_ACPI_START_REVISION_ID,
  270. CRB_ACPI_START_INDEX,
  271. NULL);
  272. if (!obj)
  273. return -ENXIO;
  274. rc = obj->integer.value == 0 ? 0 : -ENXIO;
  275. ACPI_FREE(obj);
  276. return rc;
  277. }
  278. #ifdef CONFIG_ARM64
  279. /*
  280. * This is a TPM Command Response Buffer start method that invokes a
  281. * Secure Monitor Call to requrest the firmware to execute or cancel
  282. * a TPM 2.0 command.
  283. */
  284. static int tpm_crb_smc_start(struct device *dev, unsigned long func_id)
  285. {
  286. struct arm_smccc_res res;
  287. arm_smccc_smc(func_id, 0, 0, 0, 0, 0, 0, 0, &res);
  288. if (res.a0 != 0) {
  289. dev_err(dev,
  290. FW_BUG "tpm_crb_smc_start() returns res.a0 = 0x%lx\n",
  291. res.a0);
  292. return -EIO;
  293. }
  294. return 0;
  295. }
  296. #else
  297. static int tpm_crb_smc_start(struct device *dev, unsigned long func_id)
  298. {
  299. dev_err(dev, FW_BUG "tpm_crb: incorrect start method\n");
  300. return -EINVAL;
  301. }
  302. #endif
  303. static int crb_send(struct tpm_chip *chip, u8 *buf, size_t len)
  304. {
  305. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  306. int rc = 0;
  307. /* Zero the cancel register so that the next command will not get
  308. * canceled.
  309. */
  310. iowrite32(0, &priv->regs_t->ctrl_cancel);
  311. if (len > priv->cmd_size) {
  312. dev_err(&chip->dev, "invalid command count value %zd %d\n",
  313. len, priv->cmd_size);
  314. return -E2BIG;
  315. }
  316. memcpy_toio(priv->cmd, buf, len);
  317. /* Make sure that cmd is populated before issuing start. */
  318. wmb();
  319. /* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
  320. * report only ACPI start but in practice seems to require both
  321. * CRB start, hence invoking CRB start method if hid == MSFT0101.
  322. */
  323. if ((priv->sm == ACPI_TPM2_COMMAND_BUFFER) ||
  324. (priv->sm == ACPI_TPM2_MEMORY_MAPPED) ||
  325. (!strcmp(priv->hid, "MSFT0101")))
  326. iowrite32(CRB_START_INVOKE, &priv->regs_t->ctrl_start);
  327. if ((priv->sm == ACPI_TPM2_START_METHOD) ||
  328. (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD))
  329. rc = crb_do_acpi_start(chip);
  330. if (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC) {
  331. iowrite32(CRB_START_INVOKE, &priv->regs_t->ctrl_start);
  332. rc = tpm_crb_smc_start(&chip->dev, priv->smc_func_id);
  333. }
  334. return rc;
  335. }
  336. static void crb_cancel(struct tpm_chip *chip)
  337. {
  338. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  339. iowrite32(CRB_CANCEL_INVOKE, &priv->regs_t->ctrl_cancel);
  340. if (((priv->sm == ACPI_TPM2_START_METHOD) ||
  341. (priv->sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD)) &&
  342. crb_do_acpi_start(chip))
  343. dev_err(&chip->dev, "ACPI Start failed\n");
  344. }
  345. static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
  346. {
  347. struct crb_priv *priv = dev_get_drvdata(&chip->dev);
  348. u32 cancel = ioread32(&priv->regs_t->ctrl_cancel);
  349. return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
  350. }
  351. static const struct tpm_class_ops tpm_crb = {
  352. .flags = TPM_OPS_AUTO_STARTUP,
  353. .status = crb_status,
  354. .recv = crb_recv,
  355. .send = crb_send,
  356. .cancel = crb_cancel,
  357. .req_canceled = crb_req_canceled,
  358. .go_idle = crb_go_idle,
  359. .cmd_ready = crb_cmd_ready,
  360. .request_locality = crb_request_locality,
  361. .relinquish_locality = crb_relinquish_locality,
  362. .req_complete_mask = CRB_DRV_STS_COMPLETE,
  363. .req_complete_val = CRB_DRV_STS_COMPLETE,
  364. };
  365. static int crb_check_resource(struct acpi_resource *ares, void *data)
  366. {
  367. struct resource *iores_array = data;
  368. struct resource_win win;
  369. struct resource *res = &(win.res);
  370. int i;
  371. if (acpi_dev_resource_memory(ares, res) ||
  372. acpi_dev_resource_address_space(ares, &win)) {
  373. for (i = 0; i < TPM_CRB_MAX_RESOURCES + 1; ++i) {
  374. if (resource_type(iores_array + i) != IORESOURCE_MEM) {
  375. iores_array[i] = *res;
  376. iores_array[i].name = NULL;
  377. break;
  378. }
  379. }
  380. }
  381. return 1;
  382. }
  383. static void __iomem *crb_map_res(struct device *dev, struct resource *iores,
  384. void __iomem **iobase_ptr, u64 start, u32 size)
  385. {
  386. struct resource new_res = {
  387. .start = start,
  388. .end = start + size - 1,
  389. .flags = IORESOURCE_MEM,
  390. };
  391. /* Detect a 64 bit address on a 32 bit system */
  392. if (start != new_res.start)
  393. return (void __iomem *) ERR_PTR(-EINVAL);
  394. if (!iores)
  395. return devm_ioremap_resource(dev, &new_res);
  396. if (!*iobase_ptr) {
  397. *iobase_ptr = devm_ioremap_resource(dev, iores);
  398. if (IS_ERR(*iobase_ptr))
  399. return *iobase_ptr;
  400. }
  401. return *iobase_ptr + (new_res.start - iores->start);
  402. }
  403. /*
  404. * Work around broken BIOSs that return inconsistent values from the ACPI
  405. * region vs the registers. Trust the ACPI region. Such broken systems
  406. * probably cannot send large TPM commands since the buffer will be truncated.
  407. */
  408. static u64 crb_fixup_cmd_size(struct device *dev, struct resource *io_res,
  409. u64 start, u64 size)
  410. {
  411. if (io_res->start > start || io_res->end < start)
  412. return size;
  413. if (start + size - 1 <= io_res->end)
  414. return size;
  415. dev_err(dev,
  416. FW_BUG "ACPI region does not cover the entire command/response buffer. %pr vs %llx %llx\n",
  417. io_res, start, size);
  418. return io_res->end - start + 1;
  419. }
  420. static int crb_map_io(struct acpi_device *device, struct crb_priv *priv,
  421. struct acpi_table_tpm2 *buf)
  422. {
  423. struct list_head acpi_resource_list;
  424. struct resource iores_array[TPM_CRB_MAX_RESOURCES + 1] = { {0} };
  425. void __iomem *iobase_array[TPM_CRB_MAX_RESOURCES] = {NULL};
  426. struct device *dev = &device->dev;
  427. struct resource *iores;
  428. void __iomem **iobase_ptr;
  429. int i;
  430. u32 pa_high, pa_low;
  431. u64 cmd_pa;
  432. u32 cmd_size;
  433. __le64 __rsp_pa;
  434. u64 rsp_pa;
  435. u32 rsp_size;
  436. int ret;
  437. INIT_LIST_HEAD(&acpi_resource_list);
  438. ret = acpi_dev_get_resources(device, &acpi_resource_list,
  439. crb_check_resource, iores_array);
  440. if (ret < 0)
  441. return ret;
  442. acpi_dev_free_resource_list(&acpi_resource_list);
  443. if (resource_type(iores_array) != IORESOURCE_MEM) {
  444. dev_err(dev, FW_BUG "TPM2 ACPI table does not define a memory resource\n");
  445. return -EINVAL;
  446. } else if (resource_type(iores_array + TPM_CRB_MAX_RESOURCES) ==
  447. IORESOURCE_MEM) {
  448. dev_warn(dev, "TPM2 ACPI table defines too many memory resources\n");
  449. memset(iores_array + TPM_CRB_MAX_RESOURCES,
  450. 0, sizeof(*iores_array));
  451. iores_array[TPM_CRB_MAX_RESOURCES].flags = 0;
  452. }
  453. iores = NULL;
  454. iobase_ptr = NULL;
  455. for (i = 0; resource_type(iores_array + i) == IORESOURCE_MEM; ++i) {
  456. if (buf->control_address >= iores_array[i].start &&
  457. buf->control_address + sizeof(struct crb_regs_tail) - 1 <=
  458. iores_array[i].end) {
  459. iores = iores_array + i;
  460. iobase_ptr = iobase_array + i;
  461. break;
  462. }
  463. }
  464. priv->regs_t = crb_map_res(dev, iores, iobase_ptr, buf->control_address,
  465. sizeof(struct crb_regs_tail));
  466. if (IS_ERR(priv->regs_t))
  467. return PTR_ERR(priv->regs_t);
  468. /* The ACPI IO region starts at the head area and continues to include
  469. * the control area, as one nice sane region except for some older
  470. * stuff that puts the control area outside the ACPI IO region.
  471. */
  472. if ((priv->sm == ACPI_TPM2_COMMAND_BUFFER) ||
  473. (priv->sm == ACPI_TPM2_MEMORY_MAPPED)) {
  474. if (iores &&
  475. buf->control_address == iores->start +
  476. sizeof(*priv->regs_h))
  477. priv->regs_h = *iobase_ptr;
  478. else
  479. dev_warn(dev, FW_BUG "Bad ACPI memory layout");
  480. }
  481. ret = __crb_request_locality(dev, priv, 0);
  482. if (ret)
  483. return ret;
  484. /*
  485. * PTT HW bug w/a: wake up the device to access
  486. * possibly not retained registers.
  487. */
  488. ret = __crb_cmd_ready(dev, priv);
  489. if (ret)
  490. goto out_relinquish_locality;
  491. pa_high = ioread32(&priv->regs_t->ctrl_cmd_pa_high);
  492. pa_low = ioread32(&priv->regs_t->ctrl_cmd_pa_low);
  493. cmd_pa = ((u64)pa_high << 32) | pa_low;
  494. cmd_size = ioread32(&priv->regs_t->ctrl_cmd_size);
  495. iores = NULL;
  496. iobase_ptr = NULL;
  497. for (i = 0; iores_array[i].end; ++i) {
  498. if (cmd_pa >= iores_array[i].start &&
  499. cmd_pa <= iores_array[i].end) {
  500. iores = iores_array + i;
  501. iobase_ptr = iobase_array + i;
  502. break;
  503. }
  504. }
  505. if (iores)
  506. cmd_size = crb_fixup_cmd_size(dev, iores, cmd_pa, cmd_size);
  507. dev_dbg(dev, "cmd_hi = %X cmd_low = %X cmd_size %X\n",
  508. pa_high, pa_low, cmd_size);
  509. priv->cmd = crb_map_res(dev, iores, iobase_ptr, cmd_pa, cmd_size);
  510. if (IS_ERR(priv->cmd)) {
  511. ret = PTR_ERR(priv->cmd);
  512. goto out;
  513. }
  514. memcpy_fromio(&__rsp_pa, &priv->regs_t->ctrl_rsp_pa, 8);
  515. rsp_pa = le64_to_cpu(__rsp_pa);
  516. rsp_size = ioread32(&priv->regs_t->ctrl_rsp_size);
  517. iores = NULL;
  518. iobase_ptr = NULL;
  519. for (i = 0; resource_type(iores_array + i) == IORESOURCE_MEM; ++i) {
  520. if (rsp_pa >= iores_array[i].start &&
  521. rsp_pa <= iores_array[i].end) {
  522. iores = iores_array + i;
  523. iobase_ptr = iobase_array + i;
  524. break;
  525. }
  526. }
  527. if (iores)
  528. rsp_size = crb_fixup_cmd_size(dev, iores, rsp_pa, rsp_size);
  529. if (cmd_pa != rsp_pa) {
  530. priv->rsp = crb_map_res(dev, iores, iobase_ptr,
  531. rsp_pa, rsp_size);
  532. ret = PTR_ERR_OR_ZERO(priv->rsp);
  533. goto out;
  534. }
  535. /* According to the PTP specification, overlapping command and response
  536. * buffer sizes must be identical.
  537. */
  538. if (cmd_size != rsp_size) {
  539. dev_err(dev, FW_BUG "overlapping command and response buffer sizes are not identical");
  540. ret = -EINVAL;
  541. goto out;
  542. }
  543. priv->rsp = priv->cmd;
  544. out:
  545. if (!ret)
  546. priv->cmd_size = cmd_size;
  547. __crb_go_idle(dev, priv);
  548. out_relinquish_locality:
  549. __crb_relinquish_locality(dev, priv, 0);
  550. return ret;
  551. }
  552. static int crb_acpi_add(struct acpi_device *device)
  553. {
  554. struct acpi_table_tpm2 *buf;
  555. struct crb_priv *priv;
  556. struct tpm_chip *chip;
  557. struct device *dev = &device->dev;
  558. struct tpm2_crb_smc *crb_smc;
  559. acpi_status status;
  560. u32 sm;
  561. int rc;
  562. status = acpi_get_table(ACPI_SIG_TPM2, 1,
  563. (struct acpi_table_header **) &buf);
  564. if (ACPI_FAILURE(status) || buf->header.length < sizeof(*buf)) {
  565. dev_err(dev, FW_BUG "failed to get TPM2 ACPI table\n");
  566. return -EINVAL;
  567. }
  568. /* Should the FIFO driver handle this? */
  569. sm = buf->start_method;
  570. if (sm == ACPI_TPM2_MEMORY_MAPPED)
  571. return -ENODEV;
  572. priv = devm_kzalloc(dev, sizeof(struct crb_priv), GFP_KERNEL);
  573. if (!priv)
  574. return -ENOMEM;
  575. if (sm == ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC) {
  576. if (buf->header.length < (sizeof(*buf) + sizeof(*crb_smc))) {
  577. dev_err(dev,
  578. FW_BUG "TPM2 ACPI table has wrong size %u for start method type %d\n",
  579. buf->header.length,
  580. ACPI_TPM2_COMMAND_BUFFER_WITH_ARM_SMC);
  581. return -EINVAL;
  582. }
  583. crb_smc = ACPI_ADD_PTR(struct tpm2_crb_smc, buf, sizeof(*buf));
  584. priv->smc_func_id = crb_smc->smc_func_id;
  585. }
  586. priv->sm = sm;
  587. priv->hid = acpi_device_hid(device);
  588. rc = crb_map_io(device, priv, buf);
  589. if (rc)
  590. return rc;
  591. chip = tpmm_chip_alloc(dev, &tpm_crb);
  592. if (IS_ERR(chip))
  593. return PTR_ERR(chip);
  594. dev_set_drvdata(&chip->dev, priv);
  595. chip->acpi_dev_handle = device->handle;
  596. chip->flags = TPM_CHIP_FLAG_TPM2;
  597. return tpm_chip_register(chip);
  598. }
  599. static int crb_acpi_remove(struct acpi_device *device)
  600. {
  601. struct device *dev = &device->dev;
  602. struct tpm_chip *chip = dev_get_drvdata(dev);
  603. tpm_chip_unregister(chip);
  604. return 0;
  605. }
  606. static const struct dev_pm_ops crb_pm = {
  607. SET_SYSTEM_SLEEP_PM_OPS(tpm_pm_suspend, tpm_pm_resume)
  608. };
  609. static const struct acpi_device_id crb_device_ids[] = {
  610. {"MSFT0101", 0},
  611. {"", 0},
  612. };
  613. MODULE_DEVICE_TABLE(acpi, crb_device_ids);
  614. static struct acpi_driver crb_acpi_driver = {
  615. .name = "tpm_crb",
  616. .ids = crb_device_ids,
  617. .ops = {
  618. .add = crb_acpi_add,
  619. .remove = crb_acpi_remove,
  620. },
  621. .drv = {
  622. .pm = &crb_pm,
  623. },
  624. };
  625. module_acpi_driver(crb_acpi_driver);
  626. MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
  627. MODULE_DESCRIPTION("TPM2 Driver");
  628. MODULE_VERSION("0.1");
  629. MODULE_LICENSE("GPL");