arm_arch_timer.c 43 KB

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  1. /*
  2. * linux/drivers/clocksource/arm_arch_timer.c
  3. *
  4. * Copyright (C) 2011 ARM Ltd.
  5. * All Rights Reserved
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) "arm_arch_timer: " fmt
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/device.h>
  15. #include <linux/smp.h>
  16. #include <linux/cpu.h>
  17. #include <linux/cpu_pm.h>
  18. #include <linux/clockchips.h>
  19. #include <linux/clocksource.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/of_irq.h>
  22. #include <linux/of_address.h>
  23. #include <linux/io.h>
  24. #include <linux/slab.h>
  25. #include <linux/sched/clock.h>
  26. #include <linux/sched_clock.h>
  27. #include <linux/acpi.h>
  28. #include <asm/arch_timer.h>
  29. #include <asm/virt.h>
  30. #include <clocksource/arm_arch_timer.h>
  31. #undef pr_fmt
  32. #define pr_fmt(fmt) "arch_timer: " fmt
  33. #define CNTTIDR 0x08
  34. #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
  35. #define CNTACR(n) (0x40 + ((n) * 4))
  36. #define CNTACR_RPCT BIT(0)
  37. #define CNTACR_RVCT BIT(1)
  38. #define CNTACR_RFRQ BIT(2)
  39. #define CNTACR_RVOFF BIT(3)
  40. #define CNTACR_RWVT BIT(4)
  41. #define CNTACR_RWPT BIT(5)
  42. #define CNTVCT_LO 0x08
  43. #define CNTVCT_HI 0x0c
  44. #define CNTFRQ 0x10
  45. #define CNTP_TVAL 0x28
  46. #define CNTP_CTL 0x2c
  47. #define CNTV_TVAL 0x38
  48. #define CNTV_CTL 0x3c
  49. static unsigned arch_timers_present __initdata;
  50. static void __iomem *arch_counter_base;
  51. struct arch_timer {
  52. void __iomem *base;
  53. struct clock_event_device evt;
  54. };
  55. #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
  56. static u32 arch_timer_rate;
  57. static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
  58. static struct clock_event_device __percpu *arch_timer_evt;
  59. static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI;
  60. static bool arch_timer_c3stop;
  61. static bool arch_timer_mem_use_virtual;
  62. static bool arch_counter_suspend_stop;
  63. static bool vdso_default = true;
  64. static cpumask_t evtstrm_available = CPU_MASK_NONE;
  65. static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
  66. static int __init early_evtstrm_cfg(char *buf)
  67. {
  68. return strtobool(buf, &evtstrm_enable);
  69. }
  70. early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
  71. /*
  72. * Architected system timer support.
  73. */
  74. static __always_inline
  75. void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
  76. struct clock_event_device *clk)
  77. {
  78. if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
  79. struct arch_timer *timer = to_arch_timer(clk);
  80. switch (reg) {
  81. case ARCH_TIMER_REG_CTRL:
  82. writel_relaxed(val, timer->base + CNTP_CTL);
  83. break;
  84. case ARCH_TIMER_REG_TVAL:
  85. writel_relaxed(val, timer->base + CNTP_TVAL);
  86. break;
  87. }
  88. } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
  89. struct arch_timer *timer = to_arch_timer(clk);
  90. switch (reg) {
  91. case ARCH_TIMER_REG_CTRL:
  92. writel_relaxed(val, timer->base + CNTV_CTL);
  93. break;
  94. case ARCH_TIMER_REG_TVAL:
  95. writel_relaxed(val, timer->base + CNTV_TVAL);
  96. break;
  97. }
  98. } else {
  99. arch_timer_reg_write_cp15(access, reg, val);
  100. }
  101. }
  102. static __always_inline
  103. u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
  104. struct clock_event_device *clk)
  105. {
  106. u32 val;
  107. if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
  108. struct arch_timer *timer = to_arch_timer(clk);
  109. switch (reg) {
  110. case ARCH_TIMER_REG_CTRL:
  111. val = readl_relaxed(timer->base + CNTP_CTL);
  112. break;
  113. case ARCH_TIMER_REG_TVAL:
  114. val = readl_relaxed(timer->base + CNTP_TVAL);
  115. break;
  116. }
  117. } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
  118. struct arch_timer *timer = to_arch_timer(clk);
  119. switch (reg) {
  120. case ARCH_TIMER_REG_CTRL:
  121. val = readl_relaxed(timer->base + CNTV_CTL);
  122. break;
  123. case ARCH_TIMER_REG_TVAL:
  124. val = readl_relaxed(timer->base + CNTV_TVAL);
  125. break;
  126. }
  127. } else {
  128. val = arch_timer_reg_read_cp15(access, reg);
  129. }
  130. return val;
  131. }
  132. /*
  133. * Default to cp15 based access because arm64 uses this function for
  134. * sched_clock() before DT is probed and the cp15 method is guaranteed
  135. * to exist on arm64. arm doesn't use this before DT is probed so even
  136. * if we don't have the cp15 accessors we won't have a problem.
  137. */
  138. u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
  139. EXPORT_SYMBOL_GPL(arch_timer_read_counter);
  140. u64 arch_counter_last_cntpct = 0;
  141. EXPORT_SYMBOL_GPL(arch_counter_last_cntpct);
  142. static u64 arch_counter_read(struct clocksource *cs)
  143. {
  144. return arch_timer_read_counter();
  145. }
  146. static u64 arch_counter_read_cc(const struct cyclecounter *cc)
  147. {
  148. return arch_timer_read_counter();
  149. }
  150. static struct clocksource clocksource_counter = {
  151. .name = "arch_sys_counter",
  152. .rating = 400,
  153. .read = arch_counter_read,
  154. .mask = CLOCKSOURCE_MASK(56),
  155. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  156. };
  157. static struct cyclecounter cyclecounter __ro_after_init = {
  158. .read = arch_counter_read_cc,
  159. .mask = CLOCKSOURCE_MASK(56),
  160. };
  161. struct ate_acpi_oem_info {
  162. char oem_id[ACPI_OEM_ID_SIZE + 1];
  163. char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
  164. u32 oem_revision;
  165. };
  166. #ifdef CONFIG_FSL_ERRATUM_A008585
  167. /*
  168. * The number of retries is an arbitrary value well beyond the highest number
  169. * of iterations the loop has been observed to take.
  170. */
  171. #define __fsl_a008585_read_reg(reg) ({ \
  172. u64 _old, _new; \
  173. int _retries = 200; \
  174. \
  175. do { \
  176. _old = read_sysreg(reg); \
  177. _new = read_sysreg(reg); \
  178. _retries--; \
  179. } while (unlikely(_old != _new) && _retries); \
  180. \
  181. WARN_ON_ONCE(!_retries); \
  182. _new; \
  183. })
  184. static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
  185. {
  186. return __fsl_a008585_read_reg(cntp_tval_el0);
  187. }
  188. static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
  189. {
  190. return __fsl_a008585_read_reg(cntv_tval_el0);
  191. }
  192. static u64 notrace fsl_a008585_read_cntpct_el0(void)
  193. {
  194. return __fsl_a008585_read_reg(cntpct_el0);
  195. }
  196. static u64 notrace fsl_a008585_read_cntvct_el0(void)
  197. {
  198. return __fsl_a008585_read_reg(cntvct_el0);
  199. }
  200. #endif
  201. #ifdef CONFIG_HISILICON_ERRATUM_161010101
  202. /*
  203. * Verify whether the value of the second read is larger than the first by
  204. * less than 32 is the only way to confirm the value is correct, so clear the
  205. * lower 5 bits to check whether the difference is greater than 32 or not.
  206. * Theoretically the erratum should not occur more than twice in succession
  207. * when reading the system counter, but it is possible that some interrupts
  208. * may lead to more than twice read errors, triggering the warning, so setting
  209. * the number of retries far beyond the number of iterations the loop has been
  210. * observed to take.
  211. */
  212. #define __hisi_161010101_read_reg(reg) ({ \
  213. u64 _old, _new; \
  214. int _retries = 50; \
  215. \
  216. do { \
  217. _old = read_sysreg(reg); \
  218. _new = read_sysreg(reg); \
  219. _retries--; \
  220. } while (unlikely((_new - _old) >> 5) && _retries); \
  221. \
  222. WARN_ON_ONCE(!_retries); \
  223. _new; \
  224. })
  225. static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
  226. {
  227. return __hisi_161010101_read_reg(cntp_tval_el0);
  228. }
  229. static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
  230. {
  231. return __hisi_161010101_read_reg(cntv_tval_el0);
  232. }
  233. static u64 notrace hisi_161010101_read_cntpct_el0(void)
  234. {
  235. return __hisi_161010101_read_reg(cntpct_el0);
  236. }
  237. static u64 notrace hisi_161010101_read_cntvct_el0(void)
  238. {
  239. return __hisi_161010101_read_reg(cntvct_el0);
  240. }
  241. static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
  242. /*
  243. * Note that trailing spaces are required to properly match
  244. * the OEM table information.
  245. */
  246. {
  247. .oem_id = "HISI ",
  248. .oem_table_id = "HIP05 ",
  249. .oem_revision = 0,
  250. },
  251. {
  252. .oem_id = "HISI ",
  253. .oem_table_id = "HIP06 ",
  254. .oem_revision = 0,
  255. },
  256. {
  257. .oem_id = "HISI ",
  258. .oem_table_id = "HIP07 ",
  259. .oem_revision = 0,
  260. },
  261. { /* Sentinel indicating the end of the OEM array */ },
  262. };
  263. #endif
  264. #ifdef CONFIG_ARM64_ERRATUM_858921
  265. static u64 notrace arm64_858921_read_cntpct_el0(void)
  266. {
  267. u64 old, new;
  268. old = read_sysreg(cntpct_el0);
  269. new = read_sysreg(cntpct_el0);
  270. return (((old ^ new) >> 32) & 1) ? old : new;
  271. }
  272. static u64 notrace arm64_858921_read_cntvct_el0(void)
  273. {
  274. u64 old, new;
  275. old = read_sysreg(cntvct_el0);
  276. new = read_sysreg(cntvct_el0);
  277. return (((old ^ new) >> 32) & 1) ? old : new;
  278. }
  279. #endif
  280. #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
  281. /*
  282. * The low bits of the counter registers are indeterminate while bit 10 or
  283. * greater is rolling over. Since the counter value can jump both backward
  284. * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
  285. * with all ones or all zeros in the low bits. Bound the loop by the maximum
  286. * number of CPU cycles in 3 consecutive 24 MHz counter periods.
  287. */
  288. #define __sun50i_a64_read_reg(reg) ({ \
  289. u64 _val; \
  290. int _retries = 150; \
  291. \
  292. do { \
  293. _val = read_sysreg(reg); \
  294. _retries--; \
  295. } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
  296. \
  297. WARN_ON_ONCE(!_retries); \
  298. _val; \
  299. })
  300. static u64 notrace sun50i_a64_read_cntpct_el0(void)
  301. {
  302. return __sun50i_a64_read_reg(cntpct_el0);
  303. }
  304. static u64 notrace sun50i_a64_read_cntvct_el0(void)
  305. {
  306. return __sun50i_a64_read_reg(cntvct_el0);
  307. }
  308. static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
  309. {
  310. return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
  311. }
  312. static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
  313. {
  314. return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
  315. }
  316. #endif
  317. #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
  318. DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
  319. EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
  320. DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
  321. EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
  322. static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
  323. struct clock_event_device *clk)
  324. {
  325. unsigned long ctrl;
  326. u64 cval;
  327. ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
  328. ctrl |= ARCH_TIMER_CTRL_ENABLE;
  329. ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
  330. if (access == ARCH_TIMER_PHYS_ACCESS) {
  331. cval = evt + arch_counter_get_cntpct();
  332. write_sysreg(cval, cntp_cval_el0);
  333. } else {
  334. cval = evt + arch_counter_get_cntvct();
  335. write_sysreg(cval, cntv_cval_el0);
  336. }
  337. arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
  338. }
  339. static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt,
  340. struct clock_event_device *clk)
  341. {
  342. erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
  343. return 0;
  344. }
  345. static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt,
  346. struct clock_event_device *clk)
  347. {
  348. erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
  349. return 0;
  350. }
  351. static const struct arch_timer_erratum_workaround ool_workarounds[] = {
  352. #ifdef CONFIG_FSL_ERRATUM_A008585
  353. {
  354. .match_type = ate_match_dt,
  355. .id = "fsl,erratum-a008585",
  356. .desc = "Freescale erratum a005858",
  357. .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
  358. .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
  359. .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
  360. .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
  361. .set_next_event_phys = erratum_set_next_event_tval_phys,
  362. .set_next_event_virt = erratum_set_next_event_tval_virt,
  363. },
  364. #endif
  365. #ifdef CONFIG_HISILICON_ERRATUM_161010101
  366. {
  367. .match_type = ate_match_dt,
  368. .id = "hisilicon,erratum-161010101",
  369. .desc = "HiSilicon erratum 161010101",
  370. .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
  371. .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
  372. .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
  373. .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
  374. .set_next_event_phys = erratum_set_next_event_tval_phys,
  375. .set_next_event_virt = erratum_set_next_event_tval_virt,
  376. },
  377. {
  378. .match_type = ate_match_acpi_oem_info,
  379. .id = hisi_161010101_oem_info,
  380. .desc = "HiSilicon erratum 161010101",
  381. .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
  382. .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
  383. .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
  384. .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
  385. .set_next_event_phys = erratum_set_next_event_tval_phys,
  386. .set_next_event_virt = erratum_set_next_event_tval_virt,
  387. },
  388. #endif
  389. #ifdef CONFIG_ARM64_ERRATUM_858921
  390. {
  391. .match_type = ate_match_local_cap_id,
  392. .id = (void *)ARM64_WORKAROUND_858921,
  393. .desc = "ARM erratum 858921",
  394. .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
  395. .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
  396. },
  397. #endif
  398. #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
  399. {
  400. .match_type = ate_match_dt,
  401. .id = "allwinner,erratum-unknown1",
  402. .desc = "Allwinner erratum UNKNOWN1",
  403. .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
  404. .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
  405. .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
  406. .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
  407. .set_next_event_phys = erratum_set_next_event_tval_phys,
  408. .set_next_event_virt = erratum_set_next_event_tval_virt,
  409. },
  410. #endif
  411. };
  412. typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
  413. const void *);
  414. static
  415. bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
  416. const void *arg)
  417. {
  418. const struct device_node *np = arg;
  419. return of_property_read_bool(np, wa->id);
  420. }
  421. static
  422. bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
  423. const void *arg)
  424. {
  425. return this_cpu_has_cap((uintptr_t)wa->id);
  426. }
  427. static
  428. bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
  429. const void *arg)
  430. {
  431. static const struct ate_acpi_oem_info empty_oem_info = {};
  432. const struct ate_acpi_oem_info *info = wa->id;
  433. const struct acpi_table_header *table = arg;
  434. /* Iterate over the ACPI OEM info array, looking for a match */
  435. while (memcmp(info, &empty_oem_info, sizeof(*info))) {
  436. if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
  437. !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
  438. info->oem_revision == table->oem_revision)
  439. return true;
  440. info++;
  441. }
  442. return false;
  443. }
  444. static const struct arch_timer_erratum_workaround *
  445. arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
  446. ate_match_fn_t match_fn,
  447. void *arg)
  448. {
  449. int i;
  450. for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
  451. if (ool_workarounds[i].match_type != type)
  452. continue;
  453. if (match_fn(&ool_workarounds[i], arg))
  454. return &ool_workarounds[i];
  455. }
  456. return NULL;
  457. }
  458. static
  459. void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
  460. bool local)
  461. {
  462. int i;
  463. if (local) {
  464. __this_cpu_write(timer_unstable_counter_workaround, wa);
  465. } else {
  466. for_each_possible_cpu(i)
  467. per_cpu(timer_unstable_counter_workaround, i) = wa;
  468. }
  469. /*
  470. * Use the locked version, as we're called from the CPU
  471. * hotplug framework. Otherwise, we end-up in deadlock-land.
  472. */
  473. static_branch_enable_cpuslocked(&arch_timer_read_ool_enabled);
  474. /*
  475. * Don't use the vdso fastpath if errata require using the
  476. * out-of-line counter accessor. We may change our mind pretty
  477. * late in the game (with a per-CPU erratum, for example), so
  478. * change both the default value and the vdso itself.
  479. */
  480. if (wa->read_cntvct_el0) {
  481. clocksource_counter.archdata.vdso_direct = false;
  482. vdso_default = false;
  483. }
  484. }
  485. static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
  486. void *arg)
  487. {
  488. const struct arch_timer_erratum_workaround *wa;
  489. ate_match_fn_t match_fn = NULL;
  490. bool local = false;
  491. switch (type) {
  492. case ate_match_dt:
  493. match_fn = arch_timer_check_dt_erratum;
  494. break;
  495. case ate_match_local_cap_id:
  496. match_fn = arch_timer_check_local_cap_erratum;
  497. local = true;
  498. break;
  499. case ate_match_acpi_oem_info:
  500. match_fn = arch_timer_check_acpi_oem_erratum;
  501. break;
  502. default:
  503. WARN_ON(1);
  504. return;
  505. }
  506. wa = arch_timer_iterate_errata(type, match_fn, arg);
  507. if (!wa)
  508. return;
  509. if (needs_unstable_timer_counter_workaround()) {
  510. const struct arch_timer_erratum_workaround *__wa;
  511. __wa = __this_cpu_read(timer_unstable_counter_workaround);
  512. if (__wa && wa != __wa)
  513. pr_warn("Can't enable workaround for %s (clashes with %s\n)",
  514. wa->desc, __wa->desc);
  515. if (__wa)
  516. return;
  517. }
  518. arch_timer_enable_workaround(wa, local);
  519. pr_info("Enabling %s workaround for %s\n",
  520. local ? "local" : "global", wa->desc);
  521. }
  522. #define erratum_handler(fn, r, ...) \
  523. ({ \
  524. bool __val; \
  525. if (needs_unstable_timer_counter_workaround()) { \
  526. const struct arch_timer_erratum_workaround *__wa; \
  527. __wa = __this_cpu_read(timer_unstable_counter_workaround); \
  528. if (__wa && __wa->fn) { \
  529. r = __wa->fn(__VA_ARGS__); \
  530. __val = true; \
  531. } else { \
  532. __val = false; \
  533. } \
  534. } else { \
  535. __val = false; \
  536. } \
  537. __val; \
  538. })
  539. static bool arch_timer_this_cpu_has_cntvct_wa(void)
  540. {
  541. const struct arch_timer_erratum_workaround *wa;
  542. wa = __this_cpu_read(timer_unstable_counter_workaround);
  543. return wa && wa->read_cntvct_el0;
  544. }
  545. #else
  546. #define arch_timer_check_ool_workaround(t,a) do { } while(0)
  547. #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;})
  548. #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;})
  549. #define erratum_handler(fn, r, ...) ({false;})
  550. #define arch_timer_this_cpu_has_cntvct_wa() ({false;})
  551. #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
  552. static __always_inline irqreturn_t timer_handler(const int access,
  553. struct clock_event_device *evt)
  554. {
  555. unsigned long ctrl;
  556. ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
  557. if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
  558. ctrl |= ARCH_TIMER_CTRL_IT_MASK;
  559. arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
  560. evt->event_handler(evt);
  561. return IRQ_HANDLED;
  562. }
  563. return IRQ_NONE;
  564. }
  565. static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
  566. {
  567. struct clock_event_device *evt = dev_id;
  568. return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
  569. }
  570. static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
  571. {
  572. struct clock_event_device *evt = dev_id;
  573. return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
  574. }
  575. static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
  576. {
  577. struct clock_event_device *evt = dev_id;
  578. return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
  579. }
  580. static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
  581. {
  582. struct clock_event_device *evt = dev_id;
  583. return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
  584. }
  585. static __always_inline int timer_shutdown(const int access,
  586. struct clock_event_device *clk)
  587. {
  588. unsigned long ctrl;
  589. ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
  590. ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
  591. arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
  592. return 0;
  593. }
  594. static int arch_timer_shutdown_virt(struct clock_event_device *clk)
  595. {
  596. return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
  597. }
  598. static int arch_timer_shutdown_phys(struct clock_event_device *clk)
  599. {
  600. return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
  601. }
  602. static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
  603. {
  604. return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
  605. }
  606. static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
  607. {
  608. return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
  609. }
  610. static __always_inline void set_next_event(const int access, unsigned long evt,
  611. struct clock_event_device *clk)
  612. {
  613. unsigned long ctrl;
  614. ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
  615. ctrl |= ARCH_TIMER_CTRL_ENABLE;
  616. ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
  617. arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
  618. arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
  619. }
  620. static int arch_timer_set_next_event_virt(unsigned long evt,
  621. struct clock_event_device *clk)
  622. {
  623. int ret;
  624. if (erratum_handler(set_next_event_virt, ret, evt, clk))
  625. return ret;
  626. set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
  627. return 0;
  628. }
  629. static int arch_timer_set_next_event_phys(unsigned long evt,
  630. struct clock_event_device *clk)
  631. {
  632. int ret;
  633. if (erratum_handler(set_next_event_phys, ret, evt, clk))
  634. return ret;
  635. set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
  636. return 0;
  637. }
  638. static int arch_timer_set_next_event_virt_mem(unsigned long evt,
  639. struct clock_event_device *clk)
  640. {
  641. set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
  642. return 0;
  643. }
  644. static int arch_timer_set_next_event_phys_mem(unsigned long evt,
  645. struct clock_event_device *clk)
  646. {
  647. set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
  648. return 0;
  649. }
  650. static void __arch_timer_setup(unsigned type,
  651. struct clock_event_device *clk)
  652. {
  653. clk->features = CLOCK_EVT_FEAT_ONESHOT;
  654. if (type == ARCH_TIMER_TYPE_CP15) {
  655. if (arch_timer_c3stop)
  656. clk->features |= CLOCK_EVT_FEAT_C3STOP;
  657. clk->name = "arch_sys_timer";
  658. clk->rating = 450;
  659. clk->cpumask = cpumask_of(smp_processor_id());
  660. clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
  661. switch (arch_timer_uses_ppi) {
  662. case ARCH_TIMER_VIRT_PPI:
  663. clk->set_state_shutdown = arch_timer_shutdown_virt;
  664. clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
  665. clk->set_next_event = arch_timer_set_next_event_virt;
  666. break;
  667. case ARCH_TIMER_PHYS_SECURE_PPI:
  668. case ARCH_TIMER_PHYS_NONSECURE_PPI:
  669. case ARCH_TIMER_HYP_PPI:
  670. clk->set_state_shutdown = arch_timer_shutdown_phys;
  671. clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
  672. clk->set_next_event = arch_timer_set_next_event_phys;
  673. break;
  674. default:
  675. BUG();
  676. }
  677. arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
  678. } else {
  679. clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
  680. clk->name = "arch_mem_timer";
  681. clk->rating = 400;
  682. clk->cpumask = cpu_possible_mask;
  683. if (arch_timer_mem_use_virtual) {
  684. clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
  685. clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
  686. clk->set_next_event =
  687. arch_timer_set_next_event_virt_mem;
  688. } else {
  689. clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
  690. clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
  691. clk->set_next_event =
  692. arch_timer_set_next_event_phys_mem;
  693. }
  694. }
  695. clk->set_state_shutdown(clk);
  696. clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
  697. }
  698. static void arch_timer_evtstrm_enable(int divider)
  699. {
  700. u32 cntkctl = arch_timer_get_cntkctl();
  701. cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
  702. /* Set the divider and enable virtual event stream */
  703. cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
  704. | ARCH_TIMER_VIRT_EVT_EN;
  705. arch_timer_set_cntkctl(cntkctl);
  706. elf_hwcap |= HWCAP_EVTSTRM;
  707. #ifdef CONFIG_COMPAT
  708. compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
  709. #endif
  710. cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
  711. }
  712. static void arch_timer_configure_evtstream(void)
  713. {
  714. int evt_stream_div, lsb;
  715. /*
  716. * As the event stream can at most be generated at half the frequency
  717. * of the counter, use half the frequency when computing the divider.
  718. */
  719. evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
  720. /*
  721. * Find the closest power of two to the divisor. If the adjacent bit
  722. * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
  723. */
  724. lsb = fls(evt_stream_div) - 1;
  725. if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
  726. lsb++;
  727. /* enable event stream */
  728. arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
  729. }
  730. static void arch_counter_set_user_access(void)
  731. {
  732. u32 cntkctl = arch_timer_get_cntkctl();
  733. /* Disable user access to the timers and both counters */
  734. /* Also disable virtual event stream */
  735. cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
  736. | ARCH_TIMER_USR_VT_ACCESS_EN
  737. | ARCH_TIMER_USR_VCT_ACCESS_EN
  738. | ARCH_TIMER_VIRT_EVT_EN
  739. | ARCH_TIMER_USR_PCT_ACCESS_EN);
  740. /*
  741. * Enable user access to the virtual counter if it doesn't
  742. * need to be workaround. The vdso may have been already
  743. * disabled though.
  744. */
  745. if (arch_timer_this_cpu_has_cntvct_wa())
  746. pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
  747. else
  748. cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
  749. arch_timer_set_cntkctl(cntkctl);
  750. }
  751. static bool arch_timer_has_nonsecure_ppi(void)
  752. {
  753. return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
  754. arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
  755. }
  756. static u32 check_ppi_trigger(int irq)
  757. {
  758. u32 flags = irq_get_trigger_type(irq);
  759. if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
  760. pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
  761. pr_warn("WARNING: Please fix your firmware\n");
  762. flags = IRQF_TRIGGER_LOW;
  763. }
  764. return flags;
  765. }
  766. static int arch_timer_starting_cpu(unsigned int cpu)
  767. {
  768. struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
  769. u32 flags;
  770. __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
  771. flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
  772. enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
  773. if (arch_timer_has_nonsecure_ppi()) {
  774. flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
  775. enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
  776. flags);
  777. }
  778. arch_counter_set_user_access();
  779. if (evtstrm_enable)
  780. arch_timer_configure_evtstream();
  781. return 0;
  782. }
  783. /*
  784. * For historical reasons, when probing with DT we use whichever (non-zero)
  785. * rate was probed first, and don't verify that others match. If the first node
  786. * probed has a clock-frequency property, this overrides the HW register.
  787. */
  788. static void arch_timer_of_configure_rate(u32 rate, struct device_node *np)
  789. {
  790. /* Who has more than one independent system counter? */
  791. if (arch_timer_rate)
  792. return;
  793. if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
  794. arch_timer_rate = rate;
  795. /* Check the timer frequency. */
  796. if (arch_timer_rate == 0)
  797. pr_warn("frequency not available\n");
  798. }
  799. static void arch_timer_banner(unsigned type)
  800. {
  801. pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
  802. type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
  803. type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
  804. " and " : "",
  805. type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
  806. (unsigned long)arch_timer_rate / 1000000,
  807. (unsigned long)(arch_timer_rate / 10000) % 100,
  808. type & ARCH_TIMER_TYPE_CP15 ?
  809. (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
  810. "",
  811. type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
  812. type & ARCH_TIMER_TYPE_MEM ?
  813. arch_timer_mem_use_virtual ? "virt" : "phys" :
  814. "");
  815. }
  816. u32 arch_timer_get_rate(void)
  817. {
  818. return arch_timer_rate;
  819. }
  820. bool arch_timer_evtstrm_available(void)
  821. {
  822. /*
  823. * We might get called from a preemptible context. This is fine
  824. * because availability of the event stream should be always the same
  825. * for a preemptible context and context where we might resume a task.
  826. */
  827. return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
  828. }
  829. static u64 arch_counter_get_cntvct_mem(void)
  830. {
  831. u32 vct_lo, vct_hi, tmp_hi;
  832. do {
  833. vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
  834. vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
  835. tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
  836. } while (vct_hi != tmp_hi);
  837. return ((u64) vct_hi << 32) | vct_lo;
  838. }
  839. static struct arch_timer_kvm_info arch_timer_kvm_info;
  840. struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
  841. {
  842. return &arch_timer_kvm_info;
  843. }
  844. static void __init arch_counter_register(unsigned type)
  845. {
  846. u64 start_count;
  847. /* Register the CP15 based counter if we have one */
  848. if (type & ARCH_TIMER_TYPE_CP15) {
  849. if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
  850. arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
  851. arch_timer_read_counter = arch_counter_get_cntvct;
  852. else
  853. arch_timer_read_counter = arch_counter_get_cntpct;
  854. clocksource_counter.archdata.vdso_direct = vdso_default;
  855. } else {
  856. arch_timer_read_counter = arch_counter_get_cntvct_mem;
  857. }
  858. if (!arch_counter_suspend_stop)
  859. clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
  860. start_count = arch_timer_read_counter();
  861. clocksource_register_hz(&clocksource_counter, arch_timer_rate);
  862. cyclecounter.mult = clocksource_counter.mult;
  863. cyclecounter.shift = clocksource_counter.shift;
  864. timecounter_init(&arch_timer_kvm_info.timecounter,
  865. &cyclecounter, start_count);
  866. /* 56 bits minimum, so we assume worst case rollover */
  867. sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
  868. }
  869. static void arch_timer_stop(struct clock_event_device *clk)
  870. {
  871. pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
  872. disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
  873. if (arch_timer_has_nonsecure_ppi())
  874. disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
  875. clk->set_state_shutdown(clk);
  876. }
  877. static int arch_timer_dying_cpu(unsigned int cpu)
  878. {
  879. struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
  880. cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
  881. arch_timer_stop(clk);
  882. return 0;
  883. }
  884. #ifdef CONFIG_CPU_PM
  885. static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
  886. static int arch_timer_cpu_pm_notify(struct notifier_block *self,
  887. unsigned long action, void *hcpu)
  888. {
  889. if (action == CPU_PM_ENTER) {
  890. __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
  891. cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
  892. } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
  893. arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
  894. if (elf_hwcap & HWCAP_EVTSTRM)
  895. cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
  896. }
  897. return NOTIFY_OK;
  898. }
  899. static struct notifier_block arch_timer_cpu_pm_notifier = {
  900. .notifier_call = arch_timer_cpu_pm_notify,
  901. };
  902. static int __init arch_timer_cpu_pm_init(void)
  903. {
  904. return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
  905. }
  906. static void __init arch_timer_cpu_pm_deinit(void)
  907. {
  908. WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
  909. }
  910. #else
  911. static int __init arch_timer_cpu_pm_init(void)
  912. {
  913. return 0;
  914. }
  915. static void __init arch_timer_cpu_pm_deinit(void)
  916. {
  917. }
  918. #endif
  919. static int __init arch_timer_register(void)
  920. {
  921. int err;
  922. int ppi;
  923. arch_timer_evt = alloc_percpu(struct clock_event_device);
  924. if (!arch_timer_evt) {
  925. err = -ENOMEM;
  926. goto out;
  927. }
  928. ppi = arch_timer_ppi[arch_timer_uses_ppi];
  929. switch (arch_timer_uses_ppi) {
  930. case ARCH_TIMER_VIRT_PPI:
  931. err = request_percpu_irq(ppi, arch_timer_handler_virt,
  932. "arch_timer", arch_timer_evt);
  933. break;
  934. case ARCH_TIMER_PHYS_SECURE_PPI:
  935. case ARCH_TIMER_PHYS_NONSECURE_PPI:
  936. err = request_percpu_irq(ppi, arch_timer_handler_phys,
  937. "arch_timer", arch_timer_evt);
  938. if (!err && arch_timer_has_nonsecure_ppi()) {
  939. ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
  940. err = request_percpu_irq(ppi, arch_timer_handler_phys,
  941. "arch_timer", arch_timer_evt);
  942. if (err)
  943. free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
  944. arch_timer_evt);
  945. }
  946. break;
  947. case ARCH_TIMER_HYP_PPI:
  948. err = request_percpu_irq(ppi, arch_timer_handler_phys,
  949. "arch_timer", arch_timer_evt);
  950. break;
  951. default:
  952. BUG();
  953. }
  954. if (err) {
  955. pr_err("can't register interrupt %d (%d)\n", ppi, err);
  956. goto out_free;
  957. }
  958. err = arch_timer_cpu_pm_init();
  959. if (err)
  960. goto out_unreg_notify;
  961. /* Register and immediately configure the timer on the boot CPU */
  962. err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
  963. "clockevents/arm/arch_timer:starting",
  964. arch_timer_starting_cpu, arch_timer_dying_cpu);
  965. if (err)
  966. goto out_unreg_cpupm;
  967. return 0;
  968. out_unreg_cpupm:
  969. arch_timer_cpu_pm_deinit();
  970. out_unreg_notify:
  971. free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
  972. if (arch_timer_has_nonsecure_ppi())
  973. free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
  974. arch_timer_evt);
  975. out_free:
  976. free_percpu(arch_timer_evt);
  977. out:
  978. return err;
  979. }
  980. static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
  981. {
  982. int ret;
  983. irq_handler_t func;
  984. struct arch_timer *t;
  985. t = kzalloc(sizeof(*t), GFP_KERNEL);
  986. if (!t)
  987. return -ENOMEM;
  988. t->base = base;
  989. t->evt.irq = irq;
  990. __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
  991. if (arch_timer_mem_use_virtual)
  992. func = arch_timer_handler_virt_mem;
  993. else
  994. func = arch_timer_handler_phys_mem;
  995. ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
  996. if (ret) {
  997. pr_err("Failed to request mem timer irq\n");
  998. kfree(t);
  999. }
  1000. return ret;
  1001. }
  1002. static const struct of_device_id arch_timer_of_match[] __initconst = {
  1003. { .compatible = "arm,armv7-timer", },
  1004. { .compatible = "arm,armv8-timer", },
  1005. {},
  1006. };
  1007. static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
  1008. { .compatible = "arm,armv7-timer-mem", },
  1009. {},
  1010. };
  1011. static bool __init arch_timer_needs_of_probing(void)
  1012. {
  1013. struct device_node *dn;
  1014. bool needs_probing = false;
  1015. unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
  1016. /* We have two timers, and both device-tree nodes are probed. */
  1017. if ((arch_timers_present & mask) == mask)
  1018. return false;
  1019. /*
  1020. * Only one type of timer is probed,
  1021. * check if we have another type of timer node in device-tree.
  1022. */
  1023. if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
  1024. dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
  1025. else
  1026. dn = of_find_matching_node(NULL, arch_timer_of_match);
  1027. if (dn && of_device_is_available(dn))
  1028. needs_probing = true;
  1029. of_node_put(dn);
  1030. return needs_probing;
  1031. }
  1032. static int __init arch_timer_common_init(void)
  1033. {
  1034. arch_timer_banner(arch_timers_present);
  1035. arch_counter_register(arch_timers_present);
  1036. return arch_timer_arch_init();
  1037. }
  1038. /**
  1039. * arch_timer_select_ppi() - Select suitable PPI for the current system.
  1040. *
  1041. * If HYP mode is available, we know that the physical timer
  1042. * has been configured to be accessible from PL1. Use it, so
  1043. * that a guest can use the virtual timer instead.
  1044. *
  1045. * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
  1046. * accesses to CNTP_*_EL1 registers are silently redirected to
  1047. * their CNTHP_*_EL2 counterparts, and use a different PPI
  1048. * number.
  1049. *
  1050. * If no interrupt provided for virtual timer, we'll have to
  1051. * stick to the physical timer. It'd better be accessible...
  1052. * For arm64 we never use the secure interrupt.
  1053. *
  1054. * Return: a suitable PPI type for the current system.
  1055. */
  1056. static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
  1057. {
  1058. if (is_kernel_in_hyp_mode())
  1059. return ARCH_TIMER_HYP_PPI;
  1060. if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
  1061. return ARCH_TIMER_VIRT_PPI;
  1062. if (IS_ENABLED(CONFIG_ARM64))
  1063. return ARCH_TIMER_PHYS_NONSECURE_PPI;
  1064. return ARCH_TIMER_PHYS_SECURE_PPI;
  1065. }
  1066. static int __init arch_timer_of_init(struct device_node *np)
  1067. {
  1068. int i, ret;
  1069. u32 rate;
  1070. if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
  1071. pr_warn("multiple nodes in dt, skipping\n");
  1072. return 0;
  1073. }
  1074. arch_timers_present |= ARCH_TIMER_TYPE_CP15;
  1075. for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
  1076. arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
  1077. arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
  1078. rate = arch_timer_get_cntfrq();
  1079. arch_timer_of_configure_rate(rate, np);
  1080. arch_timer_c3stop = !of_property_read_bool(np, "always-on");
  1081. /* Check for globally applicable workarounds */
  1082. arch_timer_check_ool_workaround(ate_match_dt, np);
  1083. /*
  1084. * If we cannot rely on firmware initializing the timer registers then
  1085. * we should use the physical timers instead.
  1086. */
  1087. if (IS_ENABLED(CONFIG_ARM) &&
  1088. of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
  1089. arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
  1090. else
  1091. arch_timer_uses_ppi = arch_timer_select_ppi();
  1092. if (!arch_timer_ppi[arch_timer_uses_ppi]) {
  1093. pr_err("No interrupt available, giving up\n");
  1094. return -EINVAL;
  1095. }
  1096. /* On some systems, the counter stops ticking when in suspend. */
  1097. arch_counter_suspend_stop = of_property_read_bool(np,
  1098. "arm,no-tick-in-suspend");
  1099. ret = arch_timer_register();
  1100. if (ret)
  1101. return ret;
  1102. if (arch_timer_needs_of_probing())
  1103. return 0;
  1104. return arch_timer_common_init();
  1105. }
  1106. TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
  1107. TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
  1108. static u32 __init
  1109. arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
  1110. {
  1111. void __iomem *base;
  1112. u32 rate;
  1113. base = ioremap(frame->cntbase, frame->size);
  1114. if (!base) {
  1115. pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
  1116. return 0;
  1117. }
  1118. rate = readl_relaxed(base + CNTFRQ);
  1119. iounmap(base);
  1120. return rate;
  1121. }
  1122. static struct arch_timer_mem_frame * __init
  1123. arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
  1124. {
  1125. struct arch_timer_mem_frame *frame, *best_frame = NULL;
  1126. void __iomem *cntctlbase;
  1127. u32 cnttidr;
  1128. int i;
  1129. cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
  1130. if (!cntctlbase) {
  1131. pr_err("Can't map CNTCTLBase @ %pa\n",
  1132. &timer_mem->cntctlbase);
  1133. return NULL;
  1134. }
  1135. cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
  1136. /*
  1137. * Try to find a virtual capable frame. Otherwise fall back to a
  1138. * physical capable frame.
  1139. */
  1140. for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
  1141. u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
  1142. CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
  1143. frame = &timer_mem->frame[i];
  1144. if (!frame->valid)
  1145. continue;
  1146. /* Try enabling everything, and see what sticks */
  1147. writel_relaxed(cntacr, cntctlbase + CNTACR(i));
  1148. cntacr = readl_relaxed(cntctlbase + CNTACR(i));
  1149. if ((cnttidr & CNTTIDR_VIRT(i)) &&
  1150. !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
  1151. best_frame = frame;
  1152. arch_timer_mem_use_virtual = true;
  1153. break;
  1154. }
  1155. if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
  1156. continue;
  1157. best_frame = frame;
  1158. }
  1159. iounmap(cntctlbase);
  1160. return best_frame;
  1161. }
  1162. static int __init
  1163. arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
  1164. {
  1165. void __iomem *base;
  1166. int ret, irq = 0;
  1167. if (arch_timer_mem_use_virtual)
  1168. irq = frame->virt_irq;
  1169. else
  1170. irq = frame->phys_irq;
  1171. if (!irq) {
  1172. pr_err("Frame missing %s irq.\n",
  1173. arch_timer_mem_use_virtual ? "virt" : "phys");
  1174. return -EINVAL;
  1175. }
  1176. if (!request_mem_region(frame->cntbase, frame->size,
  1177. "arch_mem_timer"))
  1178. return -EBUSY;
  1179. base = ioremap(frame->cntbase, frame->size);
  1180. if (!base) {
  1181. pr_err("Can't map frame's registers\n");
  1182. return -ENXIO;
  1183. }
  1184. ret = arch_timer_mem_register(base, irq);
  1185. if (ret) {
  1186. iounmap(base);
  1187. return ret;
  1188. }
  1189. arch_counter_base = base;
  1190. arch_timers_present |= ARCH_TIMER_TYPE_MEM;
  1191. return 0;
  1192. }
  1193. static int __init arch_timer_mem_of_init(struct device_node *np)
  1194. {
  1195. struct arch_timer_mem *timer_mem;
  1196. struct arch_timer_mem_frame *frame;
  1197. struct device_node *frame_node;
  1198. struct resource res;
  1199. int ret = -EINVAL;
  1200. u32 rate;
  1201. timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
  1202. if (!timer_mem)
  1203. return -ENOMEM;
  1204. if (of_address_to_resource(np, 0, &res))
  1205. goto out;
  1206. timer_mem->cntctlbase = res.start;
  1207. timer_mem->size = resource_size(&res);
  1208. for_each_available_child_of_node(np, frame_node) {
  1209. u32 n;
  1210. struct arch_timer_mem_frame *frame;
  1211. if (of_property_read_u32(frame_node, "frame-number", &n)) {
  1212. pr_err(FW_BUG "Missing frame-number.\n");
  1213. of_node_put(frame_node);
  1214. goto out;
  1215. }
  1216. if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
  1217. pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
  1218. ARCH_TIMER_MEM_MAX_FRAMES - 1);
  1219. of_node_put(frame_node);
  1220. goto out;
  1221. }
  1222. frame = &timer_mem->frame[n];
  1223. if (frame->valid) {
  1224. pr_err(FW_BUG "Duplicated frame-number.\n");
  1225. of_node_put(frame_node);
  1226. goto out;
  1227. }
  1228. if (of_address_to_resource(frame_node, 0, &res)) {
  1229. of_node_put(frame_node);
  1230. goto out;
  1231. }
  1232. frame->cntbase = res.start;
  1233. frame->size = resource_size(&res);
  1234. frame->virt_irq = irq_of_parse_and_map(frame_node,
  1235. ARCH_TIMER_VIRT_SPI);
  1236. frame->phys_irq = irq_of_parse_and_map(frame_node,
  1237. ARCH_TIMER_PHYS_SPI);
  1238. frame->valid = true;
  1239. }
  1240. frame = arch_timer_mem_find_best_frame(timer_mem);
  1241. if (!frame) {
  1242. pr_err("Unable to find a suitable frame in timer @ %pa\n",
  1243. &timer_mem->cntctlbase);
  1244. ret = -EINVAL;
  1245. goto out;
  1246. }
  1247. rate = arch_timer_mem_frame_get_cntfrq(frame);
  1248. arch_timer_of_configure_rate(rate, np);
  1249. ret = arch_timer_mem_frame_register(frame);
  1250. if (!ret && !arch_timer_needs_of_probing())
  1251. ret = arch_timer_common_init();
  1252. out:
  1253. kfree(timer_mem);
  1254. return ret;
  1255. }
  1256. TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
  1257. arch_timer_mem_of_init);
  1258. #ifdef CONFIG_ACPI_GTDT
  1259. static int __init
  1260. arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
  1261. {
  1262. struct arch_timer_mem_frame *frame;
  1263. u32 rate;
  1264. int i;
  1265. for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
  1266. frame = &timer_mem->frame[i];
  1267. if (!frame->valid)
  1268. continue;
  1269. rate = arch_timer_mem_frame_get_cntfrq(frame);
  1270. if (rate == arch_timer_rate)
  1271. continue;
  1272. pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
  1273. &frame->cntbase,
  1274. (unsigned long)rate, (unsigned long)arch_timer_rate);
  1275. return -EINVAL;
  1276. }
  1277. return 0;
  1278. }
  1279. static int __init arch_timer_mem_acpi_init(int platform_timer_count)
  1280. {
  1281. struct arch_timer_mem *timers, *timer;
  1282. struct arch_timer_mem_frame *frame, *best_frame = NULL;
  1283. int timer_count, i, ret = 0;
  1284. timers = kcalloc(platform_timer_count, sizeof(*timers),
  1285. GFP_KERNEL);
  1286. if (!timers)
  1287. return -ENOMEM;
  1288. ret = acpi_arch_timer_mem_init(timers, &timer_count);
  1289. if (ret || !timer_count)
  1290. goto out;
  1291. /*
  1292. * While unlikely, it's theoretically possible that none of the frames
  1293. * in a timer expose the combination of feature we want.
  1294. */
  1295. for (i = 0; i < timer_count; i++) {
  1296. timer = &timers[i];
  1297. frame = arch_timer_mem_find_best_frame(timer);
  1298. if (!best_frame)
  1299. best_frame = frame;
  1300. ret = arch_timer_mem_verify_cntfrq(timer);
  1301. if (ret) {
  1302. pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
  1303. goto out;
  1304. }
  1305. if (!best_frame) /* implies !frame */
  1306. /*
  1307. * Only complain about missing suitable frames if we
  1308. * haven't already found one in a previous iteration.
  1309. */
  1310. pr_err("Unable to find a suitable frame in timer @ %pa\n",
  1311. &timer->cntctlbase);
  1312. }
  1313. if (best_frame)
  1314. ret = arch_timer_mem_frame_register(best_frame);
  1315. out:
  1316. kfree(timers);
  1317. return ret;
  1318. }
  1319. /* Initialize per-processor generic timer and memory-mapped timer(if present) */
  1320. static int __init arch_timer_acpi_init(struct acpi_table_header *table)
  1321. {
  1322. int ret, platform_timer_count;
  1323. if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
  1324. pr_warn("already initialized, skipping\n");
  1325. return -EINVAL;
  1326. }
  1327. arch_timers_present |= ARCH_TIMER_TYPE_CP15;
  1328. ret = acpi_gtdt_init(table, &platform_timer_count);
  1329. if (ret) {
  1330. pr_err("Failed to init GTDT table.\n");
  1331. return ret;
  1332. }
  1333. arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
  1334. acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
  1335. arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
  1336. acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
  1337. arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
  1338. acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
  1339. arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
  1340. /*
  1341. * When probing via ACPI, we have no mechanism to override the sysreg
  1342. * CNTFRQ value. This *must* be correct.
  1343. */
  1344. arch_timer_rate = arch_timer_get_cntfrq();
  1345. if (!arch_timer_rate) {
  1346. pr_err(FW_BUG "frequency not available.\n");
  1347. return -EINVAL;
  1348. }
  1349. arch_timer_uses_ppi = arch_timer_select_ppi();
  1350. if (!arch_timer_ppi[arch_timer_uses_ppi]) {
  1351. pr_err("No interrupt available, giving up\n");
  1352. return -EINVAL;
  1353. }
  1354. /* Always-on capability */
  1355. arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
  1356. /* Check for globally applicable workarounds */
  1357. arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
  1358. ret = arch_timer_register();
  1359. if (ret)
  1360. return ret;
  1361. if (platform_timer_count &&
  1362. arch_timer_mem_acpi_init(platform_timer_count))
  1363. pr_err("Failed to initialize memory-mapped timer.\n");
  1364. return arch_timer_common_init();
  1365. }
  1366. TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
  1367. #endif