h8300_timer8.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/h8300/kernel/cpu/timer/timer8.c
  4. *
  5. * Yoshinori Sato <ysato@users.sourcefoge.jp>
  6. *
  7. * 8bit Timer driver
  8. *
  9. */
  10. #include <linux/errno.h>
  11. #include <linux/kernel.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/init.h>
  14. #include <linux/clockchips.h>
  15. #include <linux/clk.h>
  16. #include <linux/io.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_irq.h>
  20. #define _8TCR 0
  21. #define _8TCSR 2
  22. #define TCORA 4
  23. #define TCORB 6
  24. #define _8TCNT 8
  25. #define CMIEA 6
  26. #define CMFA 6
  27. #define FLAG_STARTED (1 << 3)
  28. #define SCALE 64
  29. #define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
  30. #define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
  31. struct timer8_priv {
  32. struct clock_event_device ced;
  33. void __iomem *mapbase;
  34. unsigned long flags;
  35. unsigned int rate;
  36. };
  37. static irqreturn_t timer8_interrupt(int irq, void *dev_id)
  38. {
  39. struct timer8_priv *p = dev_id;
  40. if (clockevent_state_oneshot(&p->ced))
  41. iowrite16be(0x0000, p->mapbase + _8TCR);
  42. p->ced.event_handler(&p->ced);
  43. bclr(CMFA, p->mapbase + _8TCSR);
  44. return IRQ_HANDLED;
  45. }
  46. static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
  47. {
  48. if (delta >= 0x10000)
  49. pr_warn("delta out of range\n");
  50. bclr(CMIEA, p->mapbase + _8TCR);
  51. iowrite16be(delta, p->mapbase + TCORA);
  52. iowrite16be(0x0000, p->mapbase + _8TCNT);
  53. bclr(CMFA, p->mapbase + _8TCSR);
  54. bset(CMIEA, p->mapbase + _8TCR);
  55. }
  56. static int timer8_enable(struct timer8_priv *p)
  57. {
  58. iowrite16be(0xffff, p->mapbase + TCORA);
  59. iowrite16be(0x0000, p->mapbase + _8TCNT);
  60. iowrite16be(0x0c02, p->mapbase + _8TCR);
  61. return 0;
  62. }
  63. static int timer8_start(struct timer8_priv *p)
  64. {
  65. int ret;
  66. if ((p->flags & FLAG_STARTED))
  67. return 0;
  68. ret = timer8_enable(p);
  69. if (!ret)
  70. p->flags |= FLAG_STARTED;
  71. return ret;
  72. }
  73. static void timer8_stop(struct timer8_priv *p)
  74. {
  75. iowrite16be(0x0000, p->mapbase + _8TCR);
  76. }
  77. static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
  78. {
  79. return container_of(ced, struct timer8_priv, ced);
  80. }
  81. static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
  82. {
  83. timer8_start(p);
  84. timer8_set_next(p, delta);
  85. }
  86. static int timer8_clock_event_shutdown(struct clock_event_device *ced)
  87. {
  88. timer8_stop(ced_to_priv(ced));
  89. return 0;
  90. }
  91. static int timer8_clock_event_periodic(struct clock_event_device *ced)
  92. {
  93. struct timer8_priv *p = ced_to_priv(ced);
  94. pr_info("%s: used for periodic clock events\n", ced->name);
  95. timer8_stop(p);
  96. timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
  97. return 0;
  98. }
  99. static int timer8_clock_event_oneshot(struct clock_event_device *ced)
  100. {
  101. struct timer8_priv *p = ced_to_priv(ced);
  102. pr_info("%s: used for oneshot clock events\n", ced->name);
  103. timer8_stop(p);
  104. timer8_clock_event_start(p, 0x10000);
  105. return 0;
  106. }
  107. static int timer8_clock_event_next(unsigned long delta,
  108. struct clock_event_device *ced)
  109. {
  110. struct timer8_priv *p = ced_to_priv(ced);
  111. BUG_ON(!clockevent_state_oneshot(ced));
  112. timer8_set_next(p, delta - 1);
  113. return 0;
  114. }
  115. static struct timer8_priv timer8_priv = {
  116. .ced = {
  117. .name = "h8300_8timer",
  118. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  119. .rating = 200,
  120. .set_next_event = timer8_clock_event_next,
  121. .set_state_shutdown = timer8_clock_event_shutdown,
  122. .set_state_periodic = timer8_clock_event_periodic,
  123. .set_state_oneshot = timer8_clock_event_oneshot,
  124. },
  125. };
  126. static int __init h8300_8timer_init(struct device_node *node)
  127. {
  128. void __iomem *base;
  129. int irq, ret;
  130. struct clk *clk;
  131. clk = of_clk_get(node, 0);
  132. if (IS_ERR(clk)) {
  133. pr_err("failed to get clock for clockevent\n");
  134. return PTR_ERR(clk);
  135. }
  136. ret = -ENXIO;
  137. base = of_iomap(node, 0);
  138. if (!base) {
  139. pr_err("failed to map registers for clockevent\n");
  140. goto free_clk;
  141. }
  142. ret = -EINVAL;
  143. irq = irq_of_parse_and_map(node, 0);
  144. if (!irq) {
  145. pr_err("failed to get irq for clockevent\n");
  146. goto unmap_reg;
  147. }
  148. timer8_priv.mapbase = base;
  149. timer8_priv.rate = clk_get_rate(clk) / SCALE;
  150. if (!timer8_priv.rate) {
  151. pr_err("Failed to get rate for the clocksource\n");
  152. goto unmap_reg;
  153. }
  154. if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
  155. timer8_priv.ced.name, &timer8_priv) < 0) {
  156. pr_err("failed to request irq %d for clockevent\n", irq);
  157. goto unmap_reg;
  158. }
  159. clockevents_config_and_register(&timer8_priv.ced,
  160. timer8_priv.rate, 1, 0x0000ffff);
  161. return 0;
  162. unmap_reg:
  163. iounmap(base);
  164. free_clk:
  165. clk_put(clk);
  166. return ret;
  167. }
  168. TIMER_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);