mxs_timer.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright (C) 2000-2001 Deep Blue Solutions
  4. // Copyright (C) 2002 Shane Nay (shane@minirl.com)
  5. // Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
  6. // Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  7. // Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
  8. #include <linux/err.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/irq.h>
  11. #include <linux/clockchips.h>
  12. #include <linux/clk.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/stmp_device.h>
  17. #include <linux/sched_clock.h>
  18. /*
  19. * There are 2 versions of the timrot on Freescale MXS-based SoCs.
  20. * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
  21. * extends the counter to 32 bits.
  22. *
  23. * The implementation uses two timers, one for clock_event and
  24. * another for clocksource. MX28 uses timrot 0 and 1, while MX23
  25. * uses 0 and 2.
  26. */
  27. #define MX23_TIMROT_VERSION_OFFSET 0x0a0
  28. #define MX28_TIMROT_VERSION_OFFSET 0x120
  29. #define BP_TIMROT_MAJOR_VERSION 24
  30. #define BV_TIMROT_VERSION_1 0x01
  31. #define BV_TIMROT_VERSION_2 0x02
  32. #define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
  33. /*
  34. * There are 4 registers for each timrotv2 instance, and 2 registers
  35. * for each timrotv1. So address step 0x40 in macros below strides
  36. * one instance of timrotv2 while two instances of timrotv1.
  37. *
  38. * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
  39. * on MX28 while timrot2 on MX23.
  40. */
  41. /* common between v1 and v2 */
  42. #define HW_TIMROT_ROTCTRL 0x00
  43. #define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
  44. /* v1 only */
  45. #define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
  46. /* v2 only */
  47. #define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
  48. #define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
  49. #define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
  50. #define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
  51. #define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
  52. #define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
  53. #define BP_TIMROT_TIMCTRLn_SELECT 0
  54. #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
  55. #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
  56. #define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf
  57. static struct clock_event_device mxs_clockevent_device;
  58. static void __iomem *mxs_timrot_base;
  59. static u32 timrot_major_version;
  60. static inline void timrot_irq_disable(void)
  61. {
  62. __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
  63. HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
  64. }
  65. static inline void timrot_irq_enable(void)
  66. {
  67. __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
  68. HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
  69. }
  70. static void timrot_irq_acknowledge(void)
  71. {
  72. __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
  73. HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
  74. }
  75. static u64 timrotv1_get_cycles(struct clocksource *cs)
  76. {
  77. return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
  78. & 0xffff0000) >> 16);
  79. }
  80. static int timrotv1_set_next_event(unsigned long evt,
  81. struct clock_event_device *dev)
  82. {
  83. /* timrot decrements the count */
  84. __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
  85. return 0;
  86. }
  87. static int timrotv2_set_next_event(unsigned long evt,
  88. struct clock_event_device *dev)
  89. {
  90. /* timrot decrements the count */
  91. __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
  92. return 0;
  93. }
  94. static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
  95. {
  96. struct clock_event_device *evt = dev_id;
  97. timrot_irq_acknowledge();
  98. evt->event_handler(evt);
  99. return IRQ_HANDLED;
  100. }
  101. static struct irqaction mxs_timer_irq = {
  102. .name = "MXS Timer Tick",
  103. .dev_id = &mxs_clockevent_device,
  104. .flags = IRQF_TIMER | IRQF_IRQPOLL,
  105. .handler = mxs_timer_interrupt,
  106. };
  107. static void mxs_irq_clear(char *state)
  108. {
  109. /* Disable interrupt in timer module */
  110. timrot_irq_disable();
  111. /* Set event time into the furthest future */
  112. if (timrot_is_v1())
  113. __raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
  114. else
  115. __raw_writel(0xffffffff,
  116. mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
  117. /* Clear pending interrupt */
  118. timrot_irq_acknowledge();
  119. pr_debug("%s: changing mode to %s\n", __func__, state);
  120. }
  121. static int mxs_shutdown(struct clock_event_device *evt)
  122. {
  123. mxs_irq_clear("shutdown");
  124. return 0;
  125. }
  126. static int mxs_set_oneshot(struct clock_event_device *evt)
  127. {
  128. if (clockevent_state_oneshot(evt))
  129. mxs_irq_clear("oneshot");
  130. timrot_irq_enable();
  131. return 0;
  132. }
  133. static struct clock_event_device mxs_clockevent_device = {
  134. .name = "mxs_timrot",
  135. .features = CLOCK_EVT_FEAT_ONESHOT,
  136. .set_state_shutdown = mxs_shutdown,
  137. .set_state_oneshot = mxs_set_oneshot,
  138. .tick_resume = mxs_shutdown,
  139. .set_next_event = timrotv2_set_next_event,
  140. .rating = 200,
  141. };
  142. static int __init mxs_clockevent_init(struct clk *timer_clk)
  143. {
  144. if (timrot_is_v1())
  145. mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
  146. mxs_clockevent_device.cpumask = cpumask_of(0);
  147. clockevents_config_and_register(&mxs_clockevent_device,
  148. clk_get_rate(timer_clk),
  149. timrot_is_v1() ? 0xf : 0x2,
  150. timrot_is_v1() ? 0xfffe : 0xfffffffe);
  151. return 0;
  152. }
  153. static struct clocksource clocksource_mxs = {
  154. .name = "mxs_timer",
  155. .rating = 200,
  156. .read = timrotv1_get_cycles,
  157. .mask = CLOCKSOURCE_MASK(16),
  158. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  159. };
  160. static u64 notrace mxs_read_sched_clock_v2(void)
  161. {
  162. return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
  163. }
  164. static int __init mxs_clocksource_init(struct clk *timer_clk)
  165. {
  166. unsigned int c = clk_get_rate(timer_clk);
  167. if (timrot_is_v1())
  168. clocksource_register_hz(&clocksource_mxs, c);
  169. else {
  170. clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
  171. "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
  172. sched_clock_register(mxs_read_sched_clock_v2, 32, c);
  173. }
  174. return 0;
  175. }
  176. static int __init mxs_timer_init(struct device_node *np)
  177. {
  178. struct clk *timer_clk;
  179. int irq, ret;
  180. mxs_timrot_base = of_iomap(np, 0);
  181. WARN_ON(!mxs_timrot_base);
  182. timer_clk = of_clk_get(np, 0);
  183. if (IS_ERR(timer_clk)) {
  184. pr_err("%s: failed to get clk\n", __func__);
  185. return PTR_ERR(timer_clk);
  186. }
  187. ret = clk_prepare_enable(timer_clk);
  188. if (ret)
  189. return ret;
  190. /*
  191. * Initialize timers to a known state
  192. */
  193. stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
  194. /* get timrot version */
  195. timrot_major_version = __raw_readl(mxs_timrot_base +
  196. (of_device_is_compatible(np, "fsl,imx23-timrot") ?
  197. MX23_TIMROT_VERSION_OFFSET :
  198. MX28_TIMROT_VERSION_OFFSET));
  199. timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
  200. /* one for clock_event */
  201. __raw_writel((timrot_is_v1() ?
  202. BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
  203. BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
  204. BM_TIMROT_TIMCTRLn_UPDATE |
  205. BM_TIMROT_TIMCTRLn_IRQ_EN,
  206. mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
  207. /* another for clocksource */
  208. __raw_writel((timrot_is_v1() ?
  209. BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
  210. BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
  211. BM_TIMROT_TIMCTRLn_RELOAD,
  212. mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
  213. /* set clocksource timer fixed count to the maximum */
  214. if (timrot_is_v1())
  215. __raw_writel(0xffff,
  216. mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
  217. else
  218. __raw_writel(0xffffffff,
  219. mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
  220. /* init and register the timer to the framework */
  221. ret = mxs_clocksource_init(timer_clk);
  222. if (ret)
  223. return ret;
  224. ret = mxs_clockevent_init(timer_clk);
  225. if (ret)
  226. return ret;
  227. /* Make irqs happen */
  228. irq = irq_of_parse_and_map(np, 0);
  229. if (irq <= 0)
  230. return -EINVAL;
  231. return setup_irq(irq, &mxs_timer_irq);
  232. }
  233. TIMER_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);