timer-nps.c 7.4 KB

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  1. /*
  2. * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/interrupt.h>
  33. #include <linux/clocksource.h>
  34. #include <linux/clockchips.h>
  35. #include <linux/clk.h>
  36. #include <linux/of.h>
  37. #include <linux/of_irq.h>
  38. #include <linux/cpu.h>
  39. #include <soc/nps/common.h>
  40. #define NPS_MSU_TICK_LOW 0xC8
  41. #define NPS_CLUSTER_OFFSET 8
  42. #define NPS_CLUSTER_NUM 16
  43. /* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
  44. static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
  45. static int __init nps_get_timer_clk(struct device_node *node,
  46. unsigned long *timer_freq,
  47. struct clk **clk)
  48. {
  49. int ret;
  50. *clk = of_clk_get(node, 0);
  51. ret = PTR_ERR_OR_ZERO(*clk);
  52. if (ret) {
  53. pr_err("timer missing clk\n");
  54. return ret;
  55. }
  56. ret = clk_prepare_enable(*clk);
  57. if (ret) {
  58. pr_err("Couldn't enable parent clk\n");
  59. clk_put(*clk);
  60. return ret;
  61. }
  62. *timer_freq = clk_get_rate(*clk);
  63. if (!(*timer_freq)) {
  64. pr_err("Couldn't get clk rate\n");
  65. clk_disable_unprepare(*clk);
  66. clk_put(*clk);
  67. return -EINVAL;
  68. }
  69. return 0;
  70. }
  71. static u64 nps_clksrc_read(struct clocksource *clksrc)
  72. {
  73. int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
  74. return (u64)ioread32be(nps_msu_reg_low_addr[cluster]);
  75. }
  76. static int __init nps_setup_clocksource(struct device_node *node)
  77. {
  78. int ret, cluster;
  79. struct clk *clk;
  80. unsigned long nps_timer1_freq;
  81. for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
  82. nps_msu_reg_low_addr[cluster] =
  83. nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
  84. NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
  85. ret = nps_get_timer_clk(node, &nps_timer1_freq, &clk);
  86. if (ret)
  87. return ret;
  88. ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick",
  89. nps_timer1_freq, 300, 32, nps_clksrc_read);
  90. if (ret) {
  91. pr_err("Couldn't register clock source.\n");
  92. clk_disable_unprepare(clk);
  93. }
  94. return ret;
  95. }
  96. TIMER_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
  97. nps_setup_clocksource);
  98. TIMER_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
  99. nps_setup_clocksource);
  100. #ifdef CONFIG_EZNPS_MTM_EXT
  101. #include <soc/nps/mtm.h>
  102. /* Timer related Aux registers */
  103. #define NPS_REG_TIMER0_TSI 0xFFFFF850
  104. #define NPS_REG_TIMER0_LIMIT 0x23
  105. #define NPS_REG_TIMER0_CTRL 0x22
  106. #define NPS_REG_TIMER0_CNT 0x21
  107. /*
  108. * Interrupt Enabled (IE) - re-arm the timer
  109. * Not Halted (NH) - is cleared when working with JTAG (for debug)
  110. */
  111. #define TIMER0_CTRL_IE BIT(0)
  112. #define TIMER0_CTRL_NH BIT(1)
  113. static unsigned long nps_timer0_freq;
  114. static unsigned long nps_timer0_irq;
  115. static void nps_clkevent_rm_thread(void)
  116. {
  117. int thread;
  118. unsigned int cflags, enabled_threads;
  119. hw_schd_save(&cflags);
  120. enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
  121. /* remove thread from TSI1 */
  122. thread = read_aux_reg(CTOP_AUX_THREAD_ID);
  123. enabled_threads &= ~(1 << thread);
  124. write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
  125. /* Acknowledge and if needed re-arm the timer */
  126. if (!enabled_threads)
  127. write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH);
  128. else
  129. write_aux_reg(NPS_REG_TIMER0_CTRL,
  130. TIMER0_CTRL_IE | TIMER0_CTRL_NH);
  131. hw_schd_restore(cflags);
  132. }
  133. static void nps_clkevent_add_thread(unsigned long delta)
  134. {
  135. int thread;
  136. unsigned int cflags, enabled_threads;
  137. hw_schd_save(&cflags);
  138. /* add thread to TSI1 */
  139. thread = read_aux_reg(CTOP_AUX_THREAD_ID);
  140. enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
  141. enabled_threads |= (1 << thread);
  142. write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads);
  143. /* set next timer event */
  144. write_aux_reg(NPS_REG_TIMER0_LIMIT, delta);
  145. write_aux_reg(NPS_REG_TIMER0_CNT, 0);
  146. write_aux_reg(NPS_REG_TIMER0_CTRL,
  147. TIMER0_CTRL_IE | TIMER0_CTRL_NH);
  148. hw_schd_restore(cflags);
  149. }
  150. /*
  151. * Whenever anyone tries to change modes, we just mask interrupts
  152. * and wait for the next event to get set.
  153. */
  154. static int nps_clkevent_set_state(struct clock_event_device *dev)
  155. {
  156. nps_clkevent_rm_thread();
  157. disable_percpu_irq(nps_timer0_irq);
  158. return 0;
  159. }
  160. static int nps_clkevent_set_next_event(unsigned long delta,
  161. struct clock_event_device *dev)
  162. {
  163. nps_clkevent_add_thread(delta);
  164. enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
  165. return 0;
  166. }
  167. static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
  168. .name = "NPS Timer0",
  169. .features = CLOCK_EVT_FEAT_ONESHOT,
  170. .rating = 300,
  171. .set_next_event = nps_clkevent_set_next_event,
  172. .set_state_oneshot = nps_clkevent_set_state,
  173. .set_state_oneshot_stopped = nps_clkevent_set_state,
  174. .set_state_shutdown = nps_clkevent_set_state,
  175. .tick_resume = nps_clkevent_set_state,
  176. };
  177. static irqreturn_t timer_irq_handler(int irq, void *dev_id)
  178. {
  179. struct clock_event_device *evt = dev_id;
  180. nps_clkevent_rm_thread();
  181. evt->event_handler(evt);
  182. return IRQ_HANDLED;
  183. }
  184. static int nps_timer_starting_cpu(unsigned int cpu)
  185. {
  186. struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
  187. evt->cpumask = cpumask_of(smp_processor_id());
  188. clockevents_config_and_register(evt, nps_timer0_freq, 0, ULONG_MAX);
  189. enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE);
  190. return 0;
  191. }
  192. static int nps_timer_dying_cpu(unsigned int cpu)
  193. {
  194. disable_percpu_irq(nps_timer0_irq);
  195. return 0;
  196. }
  197. static int __init nps_setup_clockevent(struct device_node *node)
  198. {
  199. struct clk *clk;
  200. int ret;
  201. nps_timer0_irq = irq_of_parse_and_map(node, 0);
  202. if (nps_timer0_irq <= 0) {
  203. pr_err("clockevent: missing irq\n");
  204. return -EINVAL;
  205. }
  206. ret = nps_get_timer_clk(node, &nps_timer0_freq, &clk);
  207. if (ret)
  208. return ret;
  209. /* Needs apriori irq_set_percpu_devid() done in intc map function */
  210. ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler,
  211. "Timer0 (per-cpu-tick)",
  212. &nps_clockevent_device);
  213. if (ret) {
  214. pr_err("Couldn't request irq\n");
  215. clk_disable_unprepare(clk);
  216. return ret;
  217. }
  218. ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
  219. "clockevents/nps:starting",
  220. nps_timer_starting_cpu,
  221. nps_timer_dying_cpu);
  222. if (ret) {
  223. pr_err("Failed to setup hotplug state\n");
  224. clk_disable_unprepare(clk);
  225. free_percpu_irq(nps_timer0_irq, &nps_clockevent_device);
  226. return ret;
  227. }
  228. return 0;
  229. }
  230. TIMER_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
  231. nps_setup_clockevent);
  232. #endif /* CONFIG_EZNPS_MTM_EXT */