mali_l2_cache.h 3.6 KB

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  1. /*
  2. * This confidential and proprietary software may be used only as
  3. * authorised by a licensing agreement from ARM Limited
  4. * (C) COPYRIGHT 2008-2013 ARM Limited
  5. * ALL RIGHTS RESERVED
  6. * The entire notice above must be reproduced on all authorised
  7. * copies and copies may only be made to the extent permitted
  8. * by a licensing agreement from ARM Limited.
  9. */
  10. #ifndef __MALI_KERNEL_L2_CACHE_H__
  11. #define __MALI_KERNEL_L2_CACHE_H__
  12. #include "mali_osk.h"
  13. #include "mali_hw_core.h"
  14. #define MALI_MAX_NUMBER_OF_L2_CACHE_CORES 3
  15. /* Maximum 1 GP and 4 PP for an L2 cache core (Mali-400 Quad-core) */
  16. #define MALI_MAX_NUMBER_OF_GROUPS_PER_L2_CACHE 5
  17. struct mali_group;
  18. struct mali_pm_domain;
  19. /* Flags describing state of the L2 */
  20. typedef enum mali_l2_power_status {
  21. MALI_L2_NORMAL, /**< L2 is in normal state and operational */
  22. MALI_L2_PAUSE, /**< L2 may not be accessed and may be powered off */
  23. } mali_l2_power_status;
  24. /**
  25. * Definition of the L2 cache core struct
  26. * Used to track a L2 cache unit in the system.
  27. * Contains information about the mapping of the registers
  28. */
  29. struct mali_l2_cache_core {
  30. struct mali_hw_core hw_core; /**< Common for all HW cores */
  31. u32 core_id; /**< Unique core ID */
  32. #ifdef MALI_UPPER_HALF_SCHEDULING
  33. _mali_osk_spinlock_irq_t *command_lock; /**< Serialize all L2 cache commands */
  34. _mali_osk_spinlock_irq_t *counter_lock; /**< Synchronize L2 cache counter access */
  35. #else
  36. _mali_osk_spinlock_t *command_lock;
  37. _mali_osk_spinlock_t *counter_lock;
  38. #endif
  39. u32 counter_src0; /**< Performance counter 0, MALI_HW_CORE_NO_COUNTER for disabled */
  40. u32 counter_src1; /**< Performance counter 1, MALI_HW_CORE_NO_COUNTER for disabled */
  41. u32 last_invalidated_id;
  42. struct mali_pm_domain *pm_domain;
  43. mali_l2_power_status mali_l2_status; /**< Indicate whether the L2 is paused or not */
  44. };
  45. _mali_osk_errcode_t mali_l2_cache_initialize(void);
  46. void mali_l2_cache_terminate(void);
  47. /**
  48. * L2 pause is just a status that the L2 can't be accessed temporarily.
  49. */
  50. void mali_l2_cache_pause_all(mali_bool pause);
  51. struct mali_l2_cache_core *mali_l2_cache_create(_mali_osk_resource_t * resource);
  52. void mali_l2_cache_delete(struct mali_l2_cache_core *cache);
  53. MALI_STATIC_INLINE void mali_l2_cache_set_pm_domain(struct mali_l2_cache_core *cache, struct mali_pm_domain *domain)
  54. {
  55. cache->pm_domain = domain;
  56. }
  57. u32 mali_l2_cache_get_id(struct mali_l2_cache_core *cache);
  58. void mali_l2_cache_core_set_counter_src0(struct mali_l2_cache_core *cache, u32 counter);
  59. void mali_l2_cache_core_set_counter_src1(struct mali_l2_cache_core *cache, u32 counter);
  60. u32 mali_l2_cache_core_get_counter_src0(struct mali_l2_cache_core *cache);
  61. u32 mali_l2_cache_core_get_counter_src1(struct mali_l2_cache_core *cache);
  62. void mali_l2_cache_core_get_counter_values(struct mali_l2_cache_core *cache, u32 *src0, u32 *value0, u32 *src1, u32 *value1);
  63. struct mali_l2_cache_core *mali_l2_cache_core_get_glob_l2_core(u32 index);
  64. u32 mali_l2_cache_core_get_glob_num_l2_cores(void);
  65. void mali_l2_cache_reset(struct mali_l2_cache_core *cache);
  66. void mali_l2_cache_reset_all(void);
  67. struct mali_group *mali_l2_cache_get_group(struct mali_l2_cache_core *cache, u32 index);
  68. void mali_l2_cache_invalidate(struct mali_l2_cache_core *cache);
  69. mali_bool mali_l2_cache_invalidate_conditional(struct mali_l2_cache_core *cache, u32 id);
  70. void mali_l2_cache_invalidate_all(void);
  71. void mali_l2_cache_invalidate_all_pages(u32 *pages, u32 num_pages);
  72. mali_bool mali_l2_cache_lock_power_state(struct mali_l2_cache_core *cache);
  73. void mali_l2_cache_unlock_power_state(struct mali_l2_cache_core *cache);
  74. #endif /* __MALI_KERNEL_L2_CACHE_H__ */