debug_hw.c 6.3 KB

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  1. /*
  2. * Copyright (C) 2010 Google, Inc.
  3. * Author: Erik Gilling <konkers@android.com>
  4. *
  5. * Copyright (C) 2011-2013 NVIDIA Corporation
  6. *
  7. * This software is licensed under the terms of the GNU General Public
  8. * License version 2, as published by the Free Software Foundation, and
  9. * may be copied, distributed, and modified under those terms.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. */
  17. #include "../dev.h"
  18. #include "../debug.h"
  19. #include "../cdma.h"
  20. #include "../channel.h"
  21. #define HOST1X_DEBUG_MAX_PAGE_OFFSET 102400
  22. enum {
  23. HOST1X_OPCODE_SETCLASS = 0x00,
  24. HOST1X_OPCODE_INCR = 0x01,
  25. HOST1X_OPCODE_NONINCR = 0x02,
  26. HOST1X_OPCODE_MASK = 0x03,
  27. HOST1X_OPCODE_IMM = 0x04,
  28. HOST1X_OPCODE_RESTART = 0x05,
  29. HOST1X_OPCODE_GATHER = 0x06,
  30. HOST1X_OPCODE_SETSTRMID = 0x07,
  31. HOST1X_OPCODE_SETAPPID = 0x08,
  32. HOST1X_OPCODE_SETPYLD = 0x09,
  33. HOST1X_OPCODE_INCR_W = 0x0a,
  34. HOST1X_OPCODE_NONINCR_W = 0x0b,
  35. HOST1X_OPCODE_GATHER_W = 0x0c,
  36. HOST1X_OPCODE_RESTART_W = 0x0d,
  37. HOST1X_OPCODE_EXTEND = 0x0e,
  38. };
  39. enum {
  40. HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK = 0x00,
  41. HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01,
  42. };
  43. #define INVALID_PAYLOAD 0xffffffff
  44. static unsigned int show_channel_command(struct output *o, u32 val,
  45. u32 *payload)
  46. {
  47. unsigned int mask, subop, num, opcode;
  48. opcode = val >> 28;
  49. switch (opcode) {
  50. case HOST1X_OPCODE_SETCLASS:
  51. mask = val & 0x3f;
  52. if (mask) {
  53. host1x_debug_cont(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [",
  54. val >> 6 & 0x3ff,
  55. val >> 16 & 0xfff, mask);
  56. return hweight8(mask);
  57. }
  58. host1x_debug_cont(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff);
  59. return 0;
  60. case HOST1X_OPCODE_INCR:
  61. num = val & 0xffff;
  62. host1x_debug_cont(o, "INCR(offset=%03x, [",
  63. val >> 16 & 0xfff);
  64. if (!num)
  65. host1x_debug_cont(o, "])\n");
  66. return num;
  67. case HOST1X_OPCODE_NONINCR:
  68. num = val & 0xffff;
  69. host1x_debug_cont(o, "NONINCR(offset=%03x, [",
  70. val >> 16 & 0xfff);
  71. if (!num)
  72. host1x_debug_cont(o, "])\n");
  73. return num;
  74. case HOST1X_OPCODE_MASK:
  75. mask = val & 0xffff;
  76. host1x_debug_cont(o, "MASK(offset=%03x, mask=%03x, [",
  77. val >> 16 & 0xfff, mask);
  78. if (!mask)
  79. host1x_debug_cont(o, "])\n");
  80. return hweight16(mask);
  81. case HOST1X_OPCODE_IMM:
  82. host1x_debug_cont(o, "IMM(offset=%03x, data=%03x)\n",
  83. val >> 16 & 0xfff, val & 0xffff);
  84. return 0;
  85. case HOST1X_OPCODE_RESTART:
  86. host1x_debug_cont(o, "RESTART(offset=%08x)\n", val << 4);
  87. return 0;
  88. case HOST1X_OPCODE_GATHER:
  89. host1x_debug_cont(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[",
  90. val >> 16 & 0xfff, val >> 15 & 0x1,
  91. val >> 14 & 0x1, val & 0x3fff);
  92. return 1;
  93. #if HOST1X_HW >= 6
  94. case HOST1X_OPCODE_SETSTRMID:
  95. host1x_debug_cont(o, "SETSTRMID(offset=%06x)\n",
  96. val & 0x3fffff);
  97. return 0;
  98. case HOST1X_OPCODE_SETAPPID:
  99. host1x_debug_cont(o, "SETAPPID(appid=%02x)\n", val & 0xff);
  100. return 0;
  101. case HOST1X_OPCODE_SETPYLD:
  102. *payload = val & 0xffff;
  103. host1x_debug_cont(o, "SETPYLD(data=%04x)\n", *payload);
  104. return 0;
  105. case HOST1X_OPCODE_INCR_W:
  106. case HOST1X_OPCODE_NONINCR_W:
  107. host1x_debug_cont(o, "%s(offset=%06x, ",
  108. opcode == HOST1X_OPCODE_INCR_W ?
  109. "INCR_W" : "NONINCR_W",
  110. val & 0x3fffff);
  111. if (*payload == 0) {
  112. host1x_debug_cont(o, "[])\n");
  113. return 0;
  114. } else if (*payload == INVALID_PAYLOAD) {
  115. host1x_debug_cont(o, "unknown)\n");
  116. return 0;
  117. } else {
  118. host1x_debug_cont(o, "[");
  119. return *payload;
  120. }
  121. case HOST1X_OPCODE_GATHER_W:
  122. host1x_debug_cont(o, "GATHER_W(count=%04x, addr=[",
  123. val & 0x3fff);
  124. return 2;
  125. #endif
  126. case HOST1X_OPCODE_EXTEND:
  127. subop = val >> 24 & 0xf;
  128. if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)
  129. host1x_debug_cont(o, "ACQUIRE_MLOCK(index=%d)\n",
  130. val & 0xff);
  131. else if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK)
  132. host1x_debug_cont(o, "RELEASE_MLOCK(index=%d)\n",
  133. val & 0xff);
  134. else
  135. host1x_debug_cont(o, "EXTEND_UNKNOWN(%08x)\n", val);
  136. return 0;
  137. default:
  138. host1x_debug_cont(o, "UNKNOWN\n");
  139. return 0;
  140. }
  141. }
  142. static void show_gather(struct output *o, phys_addr_t phys_addr,
  143. unsigned int words, struct host1x_cdma *cdma,
  144. phys_addr_t pin_addr, u32 *map_addr)
  145. {
  146. /* Map dmaget cursor to corresponding mem handle */
  147. u32 offset = phys_addr - pin_addr;
  148. unsigned int data_count = 0, i;
  149. u32 payload = INVALID_PAYLOAD;
  150. /*
  151. * Sometimes we're given different hardware address to the same
  152. * page - in these cases the offset will get an invalid number and
  153. * we just have to bail out.
  154. */
  155. if (offset > HOST1X_DEBUG_MAX_PAGE_OFFSET) {
  156. host1x_debug_output(o, "[address mismatch]\n");
  157. return;
  158. }
  159. for (i = 0; i < words; i++) {
  160. u32 addr = phys_addr + i * 4;
  161. u32 val = *(map_addr + offset / 4 + i);
  162. if (!data_count) {
  163. host1x_debug_output(o, "%08x: %08x: ", addr, val);
  164. data_count = show_channel_command(o, val, &payload);
  165. } else {
  166. host1x_debug_cont(o, "%08x%s", val,
  167. data_count > 1 ? ", " : "])\n");
  168. data_count--;
  169. }
  170. }
  171. }
  172. static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma)
  173. {
  174. struct host1x_job *job;
  175. list_for_each_entry(job, &cdma->sync_queue, list) {
  176. unsigned int i;
  177. host1x_debug_output(o, "\n%p: JOB, syncpt_id=%d, syncpt_val=%d, first_get=%08x, timeout=%d num_slots=%d, num_handles=%d\n",
  178. job, job->syncpt_id, job->syncpt_end,
  179. job->first_get, job->timeout,
  180. job->num_slots, job->num_unpins);
  181. for (i = 0; i < job->num_gathers; i++) {
  182. struct host1x_job_gather *g = &job->gathers[i];
  183. u32 *mapped;
  184. if (job->gather_copy_mapped)
  185. mapped = (u32 *)job->gather_copy_mapped;
  186. else
  187. mapped = host1x_bo_mmap(g->bo);
  188. if (!mapped) {
  189. host1x_debug_output(o, "[could not mmap]\n");
  190. continue;
  191. }
  192. host1x_debug_output(o, " GATHER at %pad+%#x, %d words\n",
  193. &g->base, g->offset, g->words);
  194. show_gather(o, g->base + g->offset, g->words, cdma,
  195. g->base, mapped);
  196. if (!job->gather_copy_mapped)
  197. host1x_bo_munmap(g->bo, mapped);
  198. }
  199. }
  200. }
  201. #if HOST1X_HW >= 6
  202. #include "debug_hw_1x06.c"
  203. #else
  204. #include "debug_hw_1x01.c"
  205. #endif
  206. static const struct host1x_debug_ops host1x_debug_ops = {
  207. .show_channel_cdma = host1x_debug_show_channel_cdma,
  208. .show_channel_fifo = host1x_debug_show_channel_fifo,
  209. .show_mlocks = host1x_debug_show_mlocks,
  210. };