hns_roce_common.h 14 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #ifndef _HNS_ROCE_COMMON_H
  33. #define _HNS_ROCE_COMMON_H
  34. #ifndef assert
  35. #define assert(cond)
  36. #endif
  37. #define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg))
  38. #define roce_read(dev, reg) readl((dev)->reg_base + (reg))
  39. #define roce_raw_write(value, addr) \
  40. __raw_writel((__force u32)cpu_to_le32(value), (addr))
  41. #define roce_get_field(origin, mask, shift) \
  42. (((le32_to_cpu(origin)) & (mask)) >> (shift))
  43. #define roce_get_bit(origin, shift) \
  44. roce_get_field((origin), (1ul << (shift)), (shift))
  45. #define roce_set_field(origin, mask, shift, val) \
  46. do { \
  47. (origin) &= ~cpu_to_le32(mask); \
  48. (origin) |= cpu_to_le32(((u32)(val) << (shift)) & (mask)); \
  49. } while (0)
  50. #define roce_set_bit(origin, shift, val) \
  51. roce_set_field((origin), (1ul << (shift)), (shift), (val))
  52. /*
  53. * roce_hw_index_cmp_lt - Compare two hardware index values in hisilicon
  54. * SOC, check if a is less than b.
  55. * @a: hardware index value
  56. * @b: hardware index value
  57. * @bits: the number of bits of a and b, range: 0~31.
  58. *
  59. * Hardware index increases continuously till max value, and then restart
  60. * from zero, again and again. Because the bits of reg field is often
  61. * limited, the reg field can only hold the low bits of the hardware index
  62. * in hisilicon SOC.
  63. * In some scenes we need to compare two values(a,b) getted from two reg
  64. * fields in this driver, for example:
  65. * If a equals 0xfffe, b equals 0x1 and bits equals 16, we think b has
  66. * incresed from 0xffff to 0x1 and a is less than b.
  67. * If a equals 0xfffe, b equals 0x0xf001 and bits equals 16, we think a
  68. * is bigger than b.
  69. *
  70. * Return true on a less than b, otherwise false.
  71. */
  72. #define roce_hw_index_mask(bits) ((1ul << (bits)) - 1)
  73. #define roce_hw_index_shift(bits) (32 - (bits))
  74. #define roce_hw_index_cmp_lt(a, b, bits) \
  75. ((int)((((a) - (b)) & roce_hw_index_mask(bits)) << \
  76. roce_hw_index_shift(bits)) < 0)
  77. #define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3
  78. #define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4
  79. #define ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S 5
  80. #define ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S 6
  81. #define ROCEE_GLB_CFG_ROCEE_PORT_ST_S 10
  82. #define ROCEE_GLB_CFG_ROCEE_PORT_ST_M \
  83. (((1UL << 6) - 1) << ROCEE_GLB_CFG_ROCEE_PORT_ST_S)
  84. #define ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S 16
  85. #define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S 0
  86. #define ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M \
  87. (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S)
  88. #define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S 24
  89. #define ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M \
  90. (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S)
  91. #define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S 0
  92. #define ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M \
  93. (((1UL << 24) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S)
  94. #define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S 24
  95. #define ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M \
  96. (((1UL << 4) - 1) << ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S)
  97. #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S 0
  98. #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M \
  99. (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S)
  100. #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S 16
  101. #define ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M \
  102. (((1UL << 16) - 1) << ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S)
  103. #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S 0
  104. #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M \
  105. (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S)
  106. #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S 16
  107. #define ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M \
  108. (((1UL << 16) - 1) << ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S)
  109. #define ROCEE_RAQ_WL_ROCEE_RAQ_WL_S 0
  110. #define ROCEE_RAQ_WL_ROCEE_RAQ_WL_M \
  111. (((1UL << 8) - 1) << ROCEE_RAQ_WL_ROCEE_RAQ_WL_S)
  112. #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S 0
  113. #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M \
  114. (((1UL << 15) - 1) << \
  115. ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S)
  116. #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S 16
  117. #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M \
  118. (((1UL << 4) - 1) << \
  119. ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S)
  120. #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S 20
  121. #define ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE 21
  122. #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S 0
  123. #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M \
  124. (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S)
  125. #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S 5
  126. #define ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M \
  127. (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S)
  128. #define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S 0
  129. #define ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M \
  130. (((1UL << 5) - 1) << ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S)
  131. #define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S 5
  132. #define ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M \
  133. (((1UL << 5) - 1) << ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S)
  134. #define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S 0
  135. #define ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M \
  136. (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S)
  137. #define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S 8
  138. #define ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M \
  139. (((1UL << 5) - 1) << ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S)
  140. #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S 0
  141. #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M \
  142. (((1UL << 19) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S)
  143. #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_S 19
  144. #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S 20
  145. #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M \
  146. (((1UL << 2) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S)
  147. #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S 22
  148. #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M \
  149. (((1UL << 5) - 1) << ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S)
  150. #define ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S 31
  151. #define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S 0
  152. #define ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M \
  153. (((1UL << 3) - 1) << ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S)
  154. #define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S 0
  155. #define ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M \
  156. (((1UL << 15) - 1) << ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S)
  157. #define ROCEE_MB6_ROCEE_MB_CMD_S 0
  158. #define ROCEE_MB6_ROCEE_MB_CMD_M \
  159. (((1UL << 8) - 1) << ROCEE_MB6_ROCEE_MB_CMD_S)
  160. #define ROCEE_MB6_ROCEE_MB_CMD_MDF_S 8
  161. #define ROCEE_MB6_ROCEE_MB_CMD_MDF_M \
  162. (((1UL << 4) - 1) << ROCEE_MB6_ROCEE_MB_CMD_MDF_S)
  163. #define ROCEE_MB6_ROCEE_MB_EVENT_S 14
  164. #define ROCEE_MB6_ROCEE_MB_HW_RUN_S 15
  165. #define ROCEE_MB6_ROCEE_MB_TOKEN_S 16
  166. #define ROCEE_MB6_ROCEE_MB_TOKEN_M \
  167. (((1UL << 16) - 1) << ROCEE_MB6_ROCEE_MB_TOKEN_S)
  168. #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S 0
  169. #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M \
  170. (((1UL << 24) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S)
  171. #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S 24
  172. #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M \
  173. (((1UL << 4) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S)
  174. #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S 28
  175. #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M \
  176. (((1UL << 3) - 1) << ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S)
  177. #define ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S 31
  178. #define ROCEE_SMAC_H_ROCEE_SMAC_H_S 0
  179. #define ROCEE_SMAC_H_ROCEE_SMAC_H_M \
  180. (((1UL << 16) - 1) << ROCEE_SMAC_H_ROCEE_SMAC_H_S)
  181. #define ROCEE_SMAC_H_ROCEE_PORT_MTU_S 16
  182. #define ROCEE_SMAC_H_ROCEE_PORT_MTU_M \
  183. (((1UL << 4) - 1) << ROCEE_SMAC_H_ROCEE_PORT_MTU_S)
  184. #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S 0
  185. #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M \
  186. (((1UL << 2) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S)
  187. #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S 8
  188. #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M \
  189. (((1UL << 4) - 1) << ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S)
  190. #define ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S 17
  191. #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S 0
  192. #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M \
  193. (((1UL << 5) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S)
  194. #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S 16
  195. #define ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M \
  196. (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S)
  197. #define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S 0
  198. #define ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M \
  199. (((1UL << 16) - 1) << ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S)
  200. #define ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S 16
  201. #define ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S 1
  202. #define ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S 0
  203. #define ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S 0
  204. #define ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S 1
  205. #define ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S 0
  206. #define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S 0
  207. #define ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M \
  208. (((1UL << 28) - 1) << ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S)
  209. #define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S 0
  210. #define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M \
  211. (((1UL << 28) - 1) << ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)
  212. #define ROCEE_SDB_PTR_CMP_BITS 28
  213. #define ROCEE_SDB_INV_CNT_SDB_INV_CNT_S 0
  214. #define ROCEE_SDB_INV_CNT_SDB_INV_CNT_M \
  215. (((1UL << 16) - 1) << ROCEE_SDB_INV_CNT_SDB_INV_CNT_S)
  216. #define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S 0
  217. #define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M \
  218. (((1UL << 16) - 1) << ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S)
  219. #define ROCEE_SDB_CNT_CMP_BITS 16
  220. #define ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S 20
  221. #define ROCEE_CNT_CLR_CE_CNT_CLR_CE_S 0
  222. /*************ROCEE_REG DEFINITION****************/
  223. #define ROCEE_VENDOR_ID_REG 0x0
  224. #define ROCEE_VENDOR_PART_ID_REG 0x4
  225. #define ROCEE_SYS_IMAGE_GUID_L_REG 0xC
  226. #define ROCEE_SYS_IMAGE_GUID_H_REG 0x10
  227. #define ROCEE_PORT_GID_L_0_REG 0x50
  228. #define ROCEE_PORT_GID_ML_0_REG 0x54
  229. #define ROCEE_PORT_GID_MH_0_REG 0x58
  230. #define ROCEE_PORT_GID_H_0_REG 0x5C
  231. #define ROCEE_BT_CMD_H_REG 0x204
  232. #define ROCEE_SMAC_L_0_REG 0x240
  233. #define ROCEE_SMAC_H_0_REG 0x244
  234. #define ROCEE_QP1C_CFG3_0_REG 0x27C
  235. #define ROCEE_CAEP_AEQE_CONS_IDX_REG 0x3AC
  236. #define ROCEE_CAEP_CEQC_CONS_IDX_0_REG 0x3BC
  237. #define ROCEE_ECC_UCERR_ALM1_REG 0xB38
  238. #define ROCEE_ECC_UCERR_ALM2_REG 0xB3C
  239. #define ROCEE_ECC_CERR_ALM1_REG 0xB44
  240. #define ROCEE_ECC_CERR_ALM2_REG 0xB48
  241. #define ROCEE_ACK_DELAY_REG 0x14
  242. #define ROCEE_GLB_CFG_REG 0x18
  243. #define ROCEE_DMAE_USER_CFG1_REG 0x40
  244. #define ROCEE_DMAE_USER_CFG2_REG 0x44
  245. #define ROCEE_DB_SQ_WL_REG 0x154
  246. #define ROCEE_DB_OTHERS_WL_REG 0x158
  247. #define ROCEE_RAQ_WL_REG 0x15C
  248. #define ROCEE_WRMS_POL_TIME_INTERVAL_REG 0x160
  249. #define ROCEE_EXT_DB_SQ_REG 0x164
  250. #define ROCEE_EXT_DB_SQ_H_REG 0x168
  251. #define ROCEE_EXT_DB_OTH_REG 0x16C
  252. #define ROCEE_EXT_DB_OTH_H_REG 0x170
  253. #define ROCEE_EXT_DB_SQ_WL_EMPTY_REG 0x174
  254. #define ROCEE_EXT_DB_SQ_WL_REG 0x178
  255. #define ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG 0x17C
  256. #define ROCEE_EXT_DB_OTHERS_WL_REG 0x180
  257. #define ROCEE_EXT_RAQ_REG 0x184
  258. #define ROCEE_EXT_RAQ_H_REG 0x188
  259. #define ROCEE_CAEP_CE_INTERVAL_CFG_REG 0x190
  260. #define ROCEE_CAEP_CE_BURST_NUM_CFG_REG 0x194
  261. #define ROCEE_BT_CMD_L_REG 0x200
  262. #define ROCEE_MB1_REG 0x210
  263. #define ROCEE_MB6_REG 0x224
  264. #define ROCEE_DB_SQ_L_0_REG 0x230
  265. #define ROCEE_DB_OTHERS_L_0_REG 0x238
  266. #define ROCEE_QP1C_CFG0_0_REG 0x270
  267. #define ROCEE_CAEP_AEQC_AEQE_SHIFT_REG 0x3A0
  268. #define ROCEE_CAEP_CEQC_SHIFT_0_REG 0x3B0
  269. #define ROCEE_CAEP_CE_IRQ_MASK_0_REG 0x3C0
  270. #define ROCEE_CAEP_CEQ_ALM_OVF_0_REG 0x3C4
  271. #define ROCEE_CAEP_AE_MASK_REG 0x6C8
  272. #define ROCEE_CAEP_AE_ST_REG 0x6CC
  273. #define ROCEE_SDB_ISSUE_PTR_REG 0x758
  274. #define ROCEE_SDB_SEND_PTR_REG 0x75C
  275. #define ROCEE_CAEP_CQE_WCMD_EMPTY 0x850
  276. #define ROCEE_SCAEP_WR_CQE_CNT 0x8D0
  277. #define ROCEE_SDB_INV_CNT_REG 0x9A4
  278. #define ROCEE_SDB_RETRY_CNT_REG 0x9AC
  279. #define ROCEE_TSP_BP_ST_REG 0x9EC
  280. #define ROCEE_ECC_UCERR_ALM0_REG 0xB34
  281. #define ROCEE_ECC_CERR_ALM0_REG 0xB40
  282. /* V2 ROCEE REG */
  283. #define ROCEE_TX_CMQ_BASEADDR_L_REG 0x07000
  284. #define ROCEE_TX_CMQ_BASEADDR_H_REG 0x07004
  285. #define ROCEE_TX_CMQ_DEPTH_REG 0x07008
  286. #define ROCEE_TX_CMQ_TAIL_REG 0x07010
  287. #define ROCEE_TX_CMQ_HEAD_REG 0x07014
  288. #define ROCEE_RX_CMQ_BASEADDR_L_REG 0x07018
  289. #define ROCEE_RX_CMQ_BASEADDR_H_REG 0x0701c
  290. #define ROCEE_RX_CMQ_DEPTH_REG 0x07020
  291. #define ROCEE_RX_CMQ_TAIL_REG 0x07024
  292. #define ROCEE_RX_CMQ_HEAD_REG 0x07028
  293. #define ROCEE_VF_MB_CFG0_REG 0x40
  294. #define ROCEE_VF_MB_STATUS_REG 0x58
  295. #define ROCEE_VF_EQ_DB_CFG0_REG 0x238
  296. #define ROCEE_VF_EQ_DB_CFG1_REG 0x23C
  297. #define ROCEE_VF_ABN_INT_CFG_REG 0x13000
  298. #define ROCEE_VF_ABN_INT_ST_REG 0x13004
  299. #define ROCEE_VF_ABN_INT_EN_REG 0x13008
  300. #define ROCEE_VF_EVENT_INT_EN_REG 0x1300c
  301. #endif /* _HNS_ROCE_COMMON_H */