hns_roce_main.c 24 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/acpi.h>
  34. #include <linux/of_platform.h>
  35. #include <linux/module.h>
  36. #include <rdma/ib_addr.h>
  37. #include <rdma/ib_smi.h>
  38. #include <rdma/ib_user_verbs.h>
  39. #include <rdma/ib_cache.h>
  40. #include "hns_roce_common.h"
  41. #include "hns_roce_device.h"
  42. #include <rdma/hns-abi.h>
  43. #include "hns_roce_hem.h"
  44. /**
  45. * hns_get_gid_index - Get gid index.
  46. * @hr_dev: pointer to structure hns_roce_dev.
  47. * @port: port, value range: 0 ~ MAX
  48. * @gid_index: gid_index, value range: 0 ~ MAX
  49. * Description:
  50. * N ports shared gids, allocation method as follow:
  51. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  52. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  53. * And so on
  54. */
  55. int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
  56. {
  57. return gid_index * hr_dev->caps.num_ports + port;
  58. }
  59. EXPORT_SYMBOL_GPL(hns_get_gid_index);
  60. static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
  61. {
  62. u8 phy_port;
  63. u32 i = 0;
  64. if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
  65. return 0;
  66. for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
  67. hr_dev->dev_addr[port][i] = addr[i];
  68. phy_port = hr_dev->iboe.phy_port[port];
  69. return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  70. }
  71. static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
  72. {
  73. struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  74. u8 port = attr->port_num - 1;
  75. unsigned long flags;
  76. int ret;
  77. if (port >= hr_dev->caps.num_ports)
  78. return -EINVAL;
  79. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  80. ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
  81. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  82. return ret;
  83. }
  84. static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
  85. {
  86. struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  87. struct ib_gid_attr zattr = { };
  88. u8 port = attr->port_num - 1;
  89. unsigned long flags;
  90. int ret;
  91. if (port >= hr_dev->caps.num_ports)
  92. return -EINVAL;
  93. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  94. ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
  95. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  96. return ret;
  97. }
  98. static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
  99. unsigned long event)
  100. {
  101. struct device *dev = hr_dev->dev;
  102. struct net_device *netdev;
  103. int ret = 0;
  104. netdev = hr_dev->iboe.netdevs[port];
  105. if (!netdev) {
  106. dev_err(dev, "port(%d) can't find netdev\n", port);
  107. return -ENODEV;
  108. }
  109. switch (event) {
  110. case NETDEV_UP:
  111. case NETDEV_CHANGE:
  112. case NETDEV_REGISTER:
  113. case NETDEV_CHANGEADDR:
  114. ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
  115. break;
  116. case NETDEV_DOWN:
  117. /*
  118. * In v1 engine, only support all ports closed together.
  119. */
  120. break;
  121. default:
  122. dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
  123. break;
  124. }
  125. return ret;
  126. }
  127. static int hns_roce_netdev_event(struct notifier_block *self,
  128. unsigned long event, void *ptr)
  129. {
  130. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  131. struct hns_roce_ib_iboe *iboe = NULL;
  132. struct hns_roce_dev *hr_dev = NULL;
  133. u8 port = 0;
  134. int ret = 0;
  135. hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
  136. iboe = &hr_dev->iboe;
  137. for (port = 0; port < hr_dev->caps.num_ports; port++) {
  138. if (dev == iboe->netdevs[port]) {
  139. ret = handle_en_event(hr_dev, port, event);
  140. if (ret)
  141. return NOTIFY_DONE;
  142. break;
  143. }
  144. }
  145. return NOTIFY_DONE;
  146. }
  147. static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
  148. {
  149. int ret;
  150. u8 i;
  151. for (i = 0; i < hr_dev->caps.num_ports; i++) {
  152. if (hr_dev->hw->set_mtu)
  153. hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
  154. hr_dev->caps.max_mtu);
  155. ret = hns_roce_set_mac(hr_dev, i,
  156. hr_dev->iboe.netdevs[i]->dev_addr);
  157. if (ret)
  158. return ret;
  159. }
  160. return 0;
  161. }
  162. static int hns_roce_query_device(struct ib_device *ib_dev,
  163. struct ib_device_attr *props,
  164. struct ib_udata *uhw)
  165. {
  166. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  167. memset(props, 0, sizeof(*props));
  168. props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
  169. props->max_mr_size = (u64)(~(0ULL));
  170. props->page_size_cap = hr_dev->caps.page_size_cap;
  171. props->vendor_id = hr_dev->vendor_id;
  172. props->vendor_part_id = hr_dev->vendor_part_id;
  173. props->hw_ver = hr_dev->hw_rev;
  174. props->max_qp = hr_dev->caps.num_qps;
  175. props->max_qp_wr = hr_dev->caps.max_wqes;
  176. props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
  177. IB_DEVICE_RC_RNR_NAK_GEN;
  178. props->max_send_sge = hr_dev->caps.max_sq_sg;
  179. props->max_recv_sge = hr_dev->caps.max_rq_sg;
  180. props->max_sge_rd = 1;
  181. props->max_cq = hr_dev->caps.num_cqs;
  182. props->max_cqe = hr_dev->caps.max_cqes;
  183. props->max_mr = hr_dev->caps.num_mtpts;
  184. props->max_pd = hr_dev->caps.num_pds;
  185. props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
  186. props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
  187. props->atomic_cap = IB_ATOMIC_NONE;
  188. props->max_pkeys = 1;
  189. props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
  190. return 0;
  191. }
  192. static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
  193. u8 port_num)
  194. {
  195. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  196. struct net_device *ndev;
  197. if (port_num < 1 || port_num > hr_dev->caps.num_ports)
  198. return NULL;
  199. rcu_read_lock();
  200. ndev = hr_dev->iboe.netdevs[port_num - 1];
  201. if (ndev)
  202. dev_hold(ndev);
  203. rcu_read_unlock();
  204. return ndev;
  205. }
  206. static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
  207. struct ib_port_attr *props)
  208. {
  209. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  210. struct device *dev = hr_dev->dev;
  211. struct net_device *net_dev;
  212. unsigned long flags;
  213. enum ib_mtu mtu;
  214. u8 port;
  215. assert(port_num > 0);
  216. port = port_num - 1;
  217. /* props being zeroed by the caller, avoid zeroing it here */
  218. props->max_mtu = hr_dev->caps.max_mtu;
  219. props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
  220. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  221. IB_PORT_VENDOR_CLASS_SUP |
  222. IB_PORT_BOOT_MGMT_SUP;
  223. props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
  224. props->pkey_tbl_len = 1;
  225. props->active_width = IB_WIDTH_4X;
  226. props->active_speed = 1;
  227. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  228. net_dev = hr_dev->iboe.netdevs[port];
  229. if (!net_dev) {
  230. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  231. dev_err(dev, "find netdev %d failed!\r\n", port);
  232. return -EINVAL;
  233. }
  234. mtu = iboe_get_mtu(net_dev->mtu);
  235. props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
  236. props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
  237. IB_PORT_ACTIVE : IB_PORT_DOWN;
  238. props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
  239. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  240. return 0;
  241. }
  242. static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
  243. u8 port_num)
  244. {
  245. return IB_LINK_LAYER_ETHERNET;
  246. }
  247. static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
  248. u16 *pkey)
  249. {
  250. *pkey = PKEY_ID;
  251. return 0;
  252. }
  253. static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
  254. struct ib_device_modify *props)
  255. {
  256. unsigned long flags;
  257. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  258. return -EOPNOTSUPP;
  259. if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
  260. spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
  261. memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
  262. spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
  263. }
  264. return 0;
  265. }
  266. static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
  267. struct ib_port_modify *props)
  268. {
  269. return 0;
  270. }
  271. static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
  272. struct ib_udata *udata)
  273. {
  274. int ret = 0;
  275. struct hns_roce_ucontext *context;
  276. struct hns_roce_ib_alloc_ucontext_resp resp = {};
  277. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  278. if (!hr_dev->active)
  279. return ERR_PTR(-EAGAIN);
  280. resp.qp_tab_size = hr_dev->caps.num_qps;
  281. context = kmalloc(sizeof(*context), GFP_KERNEL);
  282. if (!context)
  283. return ERR_PTR(-ENOMEM);
  284. ret = hns_roce_uar_alloc(hr_dev, &context->uar);
  285. if (ret)
  286. goto error_fail_uar_alloc;
  287. INIT_LIST_HEAD(&context->vma_list);
  288. mutex_init(&context->vma_list_mutex);
  289. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
  290. INIT_LIST_HEAD(&context->page_list);
  291. mutex_init(&context->page_mutex);
  292. }
  293. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  294. if (ret)
  295. goto error_fail_copy_to_udata;
  296. return &context->ibucontext;
  297. error_fail_copy_to_udata:
  298. hns_roce_uar_free(hr_dev, &context->uar);
  299. error_fail_uar_alloc:
  300. kfree(context);
  301. return ERR_PTR(ret);
  302. }
  303. static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
  304. {
  305. struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
  306. hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
  307. kfree(context);
  308. return 0;
  309. }
  310. static void hns_roce_vma_open(struct vm_area_struct *vma)
  311. {
  312. vma->vm_ops = NULL;
  313. }
  314. static void hns_roce_vma_close(struct vm_area_struct *vma)
  315. {
  316. struct hns_roce_vma_data *vma_data;
  317. vma_data = (struct hns_roce_vma_data *)vma->vm_private_data;
  318. vma_data->vma = NULL;
  319. mutex_lock(vma_data->vma_list_mutex);
  320. list_del(&vma_data->list);
  321. mutex_unlock(vma_data->vma_list_mutex);
  322. kfree(vma_data);
  323. }
  324. static const struct vm_operations_struct hns_roce_vm_ops = {
  325. .open = hns_roce_vma_open,
  326. .close = hns_roce_vma_close,
  327. };
  328. static int hns_roce_set_vma_data(struct vm_area_struct *vma,
  329. struct hns_roce_ucontext *context)
  330. {
  331. struct list_head *vma_head = &context->vma_list;
  332. struct hns_roce_vma_data *vma_data;
  333. vma_data = kzalloc(sizeof(*vma_data), GFP_KERNEL);
  334. if (!vma_data)
  335. return -ENOMEM;
  336. vma_data->vma = vma;
  337. vma_data->vma_list_mutex = &context->vma_list_mutex;
  338. vma->vm_private_data = vma_data;
  339. vma->vm_ops = &hns_roce_vm_ops;
  340. mutex_lock(&context->vma_list_mutex);
  341. list_add(&vma_data->list, vma_head);
  342. mutex_unlock(&context->vma_list_mutex);
  343. return 0;
  344. }
  345. static int hns_roce_mmap(struct ib_ucontext *context,
  346. struct vm_area_struct *vma)
  347. {
  348. struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
  349. if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
  350. return -EINVAL;
  351. if (vma->vm_pgoff == 0) {
  352. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  353. if (io_remap_pfn_range(vma, vma->vm_start,
  354. to_hr_ucontext(context)->uar.pfn,
  355. PAGE_SIZE, vma->vm_page_prot))
  356. return -EAGAIN;
  357. } else if (vma->vm_pgoff == 1 && hr_dev->tptr_dma_addr &&
  358. hr_dev->tptr_size) {
  359. /* vm_pgoff: 1 -- TPTR */
  360. if (io_remap_pfn_range(vma, vma->vm_start,
  361. hr_dev->tptr_dma_addr >> PAGE_SHIFT,
  362. hr_dev->tptr_size,
  363. vma->vm_page_prot))
  364. return -EAGAIN;
  365. } else
  366. return -EINVAL;
  367. return hns_roce_set_vma_data(vma, to_hr_ucontext(context));
  368. }
  369. static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
  370. struct ib_port_immutable *immutable)
  371. {
  372. struct ib_port_attr attr;
  373. int ret;
  374. ret = ib_query_port(ib_dev, port_num, &attr);
  375. if (ret)
  376. return ret;
  377. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  378. immutable->gid_tbl_len = attr.gid_tbl_len;
  379. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  380. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  381. if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
  382. immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  383. return 0;
  384. }
  385. static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
  386. {
  387. struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
  388. struct hns_roce_vma_data *vma_data, *n;
  389. struct vm_area_struct *vma;
  390. mutex_lock(&context->vma_list_mutex);
  391. list_for_each_entry_safe(vma_data, n, &context->vma_list, list) {
  392. vma = vma_data->vma;
  393. zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
  394. vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
  395. vma->vm_ops = NULL;
  396. list_del(&vma_data->list);
  397. kfree(vma_data);
  398. }
  399. mutex_unlock(&context->vma_list_mutex);
  400. }
  401. static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
  402. {
  403. struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
  404. hr_dev->active = false;
  405. unregister_netdevice_notifier(&iboe->nb);
  406. ib_unregister_device(&hr_dev->ib_dev);
  407. }
  408. static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
  409. {
  410. int ret;
  411. struct hns_roce_ib_iboe *iboe = NULL;
  412. struct ib_device *ib_dev = NULL;
  413. struct device *dev = hr_dev->dev;
  414. iboe = &hr_dev->iboe;
  415. spin_lock_init(&iboe->lock);
  416. ib_dev = &hr_dev->ib_dev;
  417. strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
  418. ib_dev->owner = THIS_MODULE;
  419. ib_dev->node_type = RDMA_NODE_IB_CA;
  420. ib_dev->dev.parent = dev;
  421. ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
  422. ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
  423. ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
  424. ib_dev->uverbs_abi_ver = 1;
  425. ib_dev->uverbs_cmd_mask =
  426. (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
  427. (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  428. (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
  429. (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
  430. (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
  431. (1ULL << IB_USER_VERBS_CMD_REG_MR) |
  432. (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
  433. (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  434. (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
  435. (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
  436. (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
  437. (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
  438. (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
  439. (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
  440. ib_dev->uverbs_ex_cmd_mask |=
  441. (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
  442. /* HCA||device||port */
  443. ib_dev->modify_device = hns_roce_modify_device;
  444. ib_dev->query_device = hns_roce_query_device;
  445. ib_dev->query_port = hns_roce_query_port;
  446. ib_dev->modify_port = hns_roce_modify_port;
  447. ib_dev->get_link_layer = hns_roce_get_link_layer;
  448. ib_dev->get_netdev = hns_roce_get_netdev;
  449. ib_dev->add_gid = hns_roce_add_gid;
  450. ib_dev->del_gid = hns_roce_del_gid;
  451. ib_dev->query_pkey = hns_roce_query_pkey;
  452. ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
  453. ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
  454. ib_dev->mmap = hns_roce_mmap;
  455. /* PD */
  456. ib_dev->alloc_pd = hns_roce_alloc_pd;
  457. ib_dev->dealloc_pd = hns_roce_dealloc_pd;
  458. /* AH */
  459. ib_dev->create_ah = hns_roce_create_ah;
  460. ib_dev->query_ah = hns_roce_query_ah;
  461. ib_dev->destroy_ah = hns_roce_destroy_ah;
  462. /* QP */
  463. ib_dev->create_qp = hns_roce_create_qp;
  464. ib_dev->modify_qp = hns_roce_modify_qp;
  465. ib_dev->query_qp = hr_dev->hw->query_qp;
  466. ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
  467. ib_dev->post_send = hr_dev->hw->post_send;
  468. ib_dev->post_recv = hr_dev->hw->post_recv;
  469. /* CQ */
  470. ib_dev->create_cq = hns_roce_ib_create_cq;
  471. ib_dev->modify_cq = hr_dev->hw->modify_cq;
  472. ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
  473. ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
  474. ib_dev->poll_cq = hr_dev->hw->poll_cq;
  475. /* MR */
  476. ib_dev->get_dma_mr = hns_roce_get_dma_mr;
  477. ib_dev->reg_user_mr = hns_roce_reg_user_mr;
  478. ib_dev->dereg_mr = hns_roce_dereg_mr;
  479. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
  480. ib_dev->rereg_user_mr = hns_roce_rereg_user_mr;
  481. ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
  482. }
  483. /* OTHERS */
  484. ib_dev->get_port_immutable = hns_roce_port_immutable;
  485. ib_dev->disassociate_ucontext = hns_roce_disassociate_ucontext;
  486. ib_dev->driver_id = RDMA_DRIVER_HNS;
  487. ret = ib_register_device(ib_dev, NULL);
  488. if (ret) {
  489. dev_err(dev, "ib_register_device failed!\n");
  490. return ret;
  491. }
  492. ret = hns_roce_setup_mtu_mac(hr_dev);
  493. if (ret) {
  494. dev_err(dev, "setup_mtu_mac failed!\n");
  495. goto error_failed_setup_mtu_mac;
  496. }
  497. iboe->nb.notifier_call = hns_roce_netdev_event;
  498. ret = register_netdevice_notifier(&iboe->nb);
  499. if (ret) {
  500. dev_err(dev, "register_netdevice_notifier failed!\n");
  501. goto error_failed_setup_mtu_mac;
  502. }
  503. hr_dev->active = true;
  504. return 0;
  505. error_failed_setup_mtu_mac:
  506. ib_unregister_device(ib_dev);
  507. return ret;
  508. }
  509. static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
  510. {
  511. int ret;
  512. struct device *dev = hr_dev->dev;
  513. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
  514. HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
  515. hr_dev->caps.num_mtt_segs, 1);
  516. if (ret) {
  517. dev_err(dev, "Failed to init MTT context memory, aborting.\n");
  518. return ret;
  519. }
  520. if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
  521. ret = hns_roce_init_hem_table(hr_dev,
  522. &hr_dev->mr_table.mtt_cqe_table,
  523. HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
  524. hr_dev->caps.num_cqe_segs, 1);
  525. if (ret) {
  526. dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
  527. goto err_unmap_cqe;
  528. }
  529. }
  530. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
  531. HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
  532. hr_dev->caps.num_mtpts, 1);
  533. if (ret) {
  534. dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
  535. goto err_unmap_mtt;
  536. }
  537. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
  538. HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
  539. hr_dev->caps.num_qps, 1);
  540. if (ret) {
  541. dev_err(dev, "Failed to init QP context memory, aborting.\n");
  542. goto err_unmap_dmpt;
  543. }
  544. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
  545. HEM_TYPE_IRRL,
  546. hr_dev->caps.irrl_entry_sz *
  547. hr_dev->caps.max_qp_init_rdma,
  548. hr_dev->caps.num_qps, 1);
  549. if (ret) {
  550. dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
  551. goto err_unmap_qp;
  552. }
  553. if (hr_dev->caps.trrl_entry_sz) {
  554. ret = hns_roce_init_hem_table(hr_dev,
  555. &hr_dev->qp_table.trrl_table,
  556. HEM_TYPE_TRRL,
  557. hr_dev->caps.trrl_entry_sz *
  558. hr_dev->caps.max_qp_dest_rdma,
  559. hr_dev->caps.num_qps, 1);
  560. if (ret) {
  561. dev_err(dev,
  562. "Failed to init trrl_table memory, aborting.\n");
  563. goto err_unmap_irrl;
  564. }
  565. }
  566. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
  567. HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
  568. hr_dev->caps.num_cqs, 1);
  569. if (ret) {
  570. dev_err(dev, "Failed to init CQ context memory, aborting.\n");
  571. goto err_unmap_trrl;
  572. }
  573. return 0;
  574. err_unmap_trrl:
  575. if (hr_dev->caps.trrl_entry_sz)
  576. hns_roce_cleanup_hem_table(hr_dev,
  577. &hr_dev->qp_table.trrl_table);
  578. err_unmap_irrl:
  579. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
  580. err_unmap_qp:
  581. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
  582. err_unmap_dmpt:
  583. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
  584. err_unmap_mtt:
  585. if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
  586. hns_roce_cleanup_hem_table(hr_dev,
  587. &hr_dev->mr_table.mtt_cqe_table);
  588. err_unmap_cqe:
  589. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
  590. return ret;
  591. }
  592. /**
  593. * hns_roce_setup_hca - setup host channel adapter
  594. * @hr_dev: pointer to hns roce device
  595. * Return : int
  596. */
  597. static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
  598. {
  599. int ret;
  600. struct device *dev = hr_dev->dev;
  601. spin_lock_init(&hr_dev->sm_lock);
  602. spin_lock_init(&hr_dev->bt_cmd_lock);
  603. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
  604. INIT_LIST_HEAD(&hr_dev->pgdir_list);
  605. mutex_init(&hr_dev->pgdir_mutex);
  606. }
  607. ret = hns_roce_init_uar_table(hr_dev);
  608. if (ret) {
  609. dev_err(dev, "Failed to initialize uar table. aborting\n");
  610. return ret;
  611. }
  612. ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
  613. if (ret) {
  614. dev_err(dev, "Failed to allocate priv_uar.\n");
  615. goto err_uar_table_free;
  616. }
  617. ret = hns_roce_init_pd_table(hr_dev);
  618. if (ret) {
  619. dev_err(dev, "Failed to init protected domain table.\n");
  620. goto err_uar_alloc_free;
  621. }
  622. ret = hns_roce_init_mr_table(hr_dev);
  623. if (ret) {
  624. dev_err(dev, "Failed to init memory region table.\n");
  625. goto err_pd_table_free;
  626. }
  627. ret = hns_roce_init_cq_table(hr_dev);
  628. if (ret) {
  629. dev_err(dev, "Failed to init completion queue table.\n");
  630. goto err_mr_table_free;
  631. }
  632. ret = hns_roce_init_qp_table(hr_dev);
  633. if (ret) {
  634. dev_err(dev, "Failed to init queue pair table.\n");
  635. goto err_cq_table_free;
  636. }
  637. return 0;
  638. err_cq_table_free:
  639. hns_roce_cleanup_cq_table(hr_dev);
  640. err_mr_table_free:
  641. hns_roce_cleanup_mr_table(hr_dev);
  642. err_pd_table_free:
  643. hns_roce_cleanup_pd_table(hr_dev);
  644. err_uar_alloc_free:
  645. hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
  646. err_uar_table_free:
  647. hns_roce_cleanup_uar_table(hr_dev);
  648. return ret;
  649. }
  650. int hns_roce_init(struct hns_roce_dev *hr_dev)
  651. {
  652. int ret;
  653. struct device *dev = hr_dev->dev;
  654. if (hr_dev->hw->reset) {
  655. ret = hr_dev->hw->reset(hr_dev, true);
  656. if (ret) {
  657. dev_err(dev, "Reset RoCE engine failed!\n");
  658. return ret;
  659. }
  660. }
  661. hr_dev->is_reset = false;
  662. if (hr_dev->hw->cmq_init) {
  663. ret = hr_dev->hw->cmq_init(hr_dev);
  664. if (ret) {
  665. dev_err(dev, "Init RoCE Command Queue failed!\n");
  666. goto error_failed_cmq_init;
  667. }
  668. }
  669. ret = hr_dev->hw->hw_profile(hr_dev);
  670. if (ret) {
  671. dev_err(dev, "Get RoCE engine profile failed!\n");
  672. goto error_failed_cmd_init;
  673. }
  674. ret = hns_roce_cmd_init(hr_dev);
  675. if (ret) {
  676. dev_err(dev, "cmd init failed!\n");
  677. goto error_failed_cmd_init;
  678. }
  679. ret = hr_dev->hw->init_eq(hr_dev);
  680. if (ret) {
  681. dev_err(dev, "eq init failed!\n");
  682. goto error_failed_eq_table;
  683. }
  684. if (hr_dev->cmd_mod) {
  685. ret = hns_roce_cmd_use_events(hr_dev);
  686. if (ret) {
  687. dev_err(dev, "Switch to event-driven cmd failed!\n");
  688. goto error_failed_use_event;
  689. }
  690. }
  691. ret = hns_roce_init_hem(hr_dev);
  692. if (ret) {
  693. dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
  694. goto error_failed_init_hem;
  695. }
  696. ret = hns_roce_setup_hca(hr_dev);
  697. if (ret) {
  698. dev_err(dev, "setup hca failed!\n");
  699. goto error_failed_setup_hca;
  700. }
  701. if (hr_dev->hw->hw_init) {
  702. ret = hr_dev->hw->hw_init(hr_dev);
  703. if (ret) {
  704. dev_err(dev, "hw_init failed!\n");
  705. goto error_failed_engine_init;
  706. }
  707. }
  708. ret = hns_roce_register_device(hr_dev);
  709. if (ret)
  710. goto error_failed_register_device;
  711. return 0;
  712. error_failed_register_device:
  713. if (hr_dev->hw->hw_exit)
  714. hr_dev->hw->hw_exit(hr_dev);
  715. error_failed_engine_init:
  716. hns_roce_cleanup_bitmap(hr_dev);
  717. error_failed_setup_hca:
  718. hns_roce_cleanup_hem(hr_dev);
  719. error_failed_init_hem:
  720. if (hr_dev->cmd_mod)
  721. hns_roce_cmd_use_polling(hr_dev);
  722. error_failed_use_event:
  723. hr_dev->hw->cleanup_eq(hr_dev);
  724. error_failed_eq_table:
  725. hns_roce_cmd_cleanup(hr_dev);
  726. error_failed_cmd_init:
  727. if (hr_dev->hw->cmq_exit)
  728. hr_dev->hw->cmq_exit(hr_dev);
  729. error_failed_cmq_init:
  730. if (hr_dev->hw->reset) {
  731. if (hr_dev->hw->reset(hr_dev, false))
  732. dev_err(dev, "Dereset RoCE engine failed!\n");
  733. }
  734. return ret;
  735. }
  736. EXPORT_SYMBOL_GPL(hns_roce_init);
  737. void hns_roce_exit(struct hns_roce_dev *hr_dev)
  738. {
  739. hns_roce_unregister_device(hr_dev);
  740. if (hr_dev->hw->hw_exit)
  741. hr_dev->hw->hw_exit(hr_dev);
  742. hns_roce_cleanup_bitmap(hr_dev);
  743. hns_roce_cleanup_hem(hr_dev);
  744. if (hr_dev->cmd_mod)
  745. hns_roce_cmd_use_polling(hr_dev);
  746. hr_dev->hw->cleanup_eq(hr_dev);
  747. hns_roce_cmd_cleanup(hr_dev);
  748. if (hr_dev->hw->cmq_exit)
  749. hr_dev->hw->cmq_exit(hr_dev);
  750. if (hr_dev->hw->reset)
  751. hr_dev->hw->reset(hr_dev, false);
  752. }
  753. EXPORT_SYMBOL_GPL(hns_roce_exit);
  754. MODULE_LICENSE("Dual BSD/GPL");
  755. MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
  756. MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
  757. MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
  758. MODULE_DESCRIPTION("HNS RoCE Driver");