hns_roce_qp.c 31 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/pci.h>
  34. #include <linux/platform_device.h>
  35. #include <rdma/ib_addr.h>
  36. #include <rdma/ib_umem.h>
  37. #include "hns_roce_common.h"
  38. #include "hns_roce_device.h"
  39. #include "hns_roce_hem.h"
  40. #include <rdma/hns-abi.h>
  41. #define SQP_NUM (2 * HNS_ROCE_MAX_PORTS)
  42. void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
  43. {
  44. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  45. struct device *dev = hr_dev->dev;
  46. struct hns_roce_qp *qp;
  47. spin_lock(&qp_table->lock);
  48. qp = __hns_roce_qp_lookup(hr_dev, qpn);
  49. if (qp)
  50. atomic_inc(&qp->refcount);
  51. spin_unlock(&qp_table->lock);
  52. if (!qp) {
  53. dev_warn(dev, "Async event for bogus QP %08x\n", qpn);
  54. return;
  55. }
  56. qp->event(qp, (enum hns_roce_event)event_type);
  57. if (atomic_dec_and_test(&qp->refcount))
  58. complete(&qp->free);
  59. }
  60. EXPORT_SYMBOL_GPL(hns_roce_qp_event);
  61. static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
  62. enum hns_roce_event type)
  63. {
  64. struct ib_event event;
  65. struct ib_qp *ibqp = &hr_qp->ibqp;
  66. if (ibqp->event_handler) {
  67. event.device = ibqp->device;
  68. event.element.qp = ibqp;
  69. switch (type) {
  70. case HNS_ROCE_EVENT_TYPE_PATH_MIG:
  71. event.event = IB_EVENT_PATH_MIG;
  72. break;
  73. case HNS_ROCE_EVENT_TYPE_COMM_EST:
  74. event.event = IB_EVENT_COMM_EST;
  75. break;
  76. case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
  77. event.event = IB_EVENT_SQ_DRAINED;
  78. break;
  79. case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
  80. event.event = IB_EVENT_QP_LAST_WQE_REACHED;
  81. break;
  82. case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
  83. event.event = IB_EVENT_QP_FATAL;
  84. break;
  85. case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
  86. event.event = IB_EVENT_PATH_MIG_ERR;
  87. break;
  88. case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
  89. event.event = IB_EVENT_QP_REQ_ERR;
  90. break;
  91. case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
  92. event.event = IB_EVENT_QP_ACCESS_ERR;
  93. break;
  94. default:
  95. dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n",
  96. type, hr_qp->qpn);
  97. return;
  98. }
  99. ibqp->event_handler(&event, ibqp->qp_context);
  100. }
  101. }
  102. static int hns_roce_reserve_range_qp(struct hns_roce_dev *hr_dev, int cnt,
  103. int align, unsigned long *base)
  104. {
  105. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  106. return hns_roce_bitmap_alloc_range(&qp_table->bitmap, cnt, align,
  107. base) ?
  108. -ENOMEM :
  109. 0;
  110. }
  111. enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state)
  112. {
  113. switch (state) {
  114. case IB_QPS_RESET:
  115. return HNS_ROCE_QP_STATE_RST;
  116. case IB_QPS_INIT:
  117. return HNS_ROCE_QP_STATE_INIT;
  118. case IB_QPS_RTR:
  119. return HNS_ROCE_QP_STATE_RTR;
  120. case IB_QPS_RTS:
  121. return HNS_ROCE_QP_STATE_RTS;
  122. case IB_QPS_SQD:
  123. return HNS_ROCE_QP_STATE_SQD;
  124. case IB_QPS_ERR:
  125. return HNS_ROCE_QP_STATE_ERR;
  126. default:
  127. return HNS_ROCE_QP_NUM_STATE;
  128. }
  129. }
  130. EXPORT_SYMBOL_GPL(to_hns_roce_state);
  131. static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
  132. struct hns_roce_qp *hr_qp)
  133. {
  134. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  135. int ret;
  136. if (!qpn)
  137. return -EINVAL;
  138. hr_qp->qpn = qpn;
  139. spin_lock_irq(&qp_table->lock);
  140. ret = radix_tree_insert(&hr_dev->qp_table_tree,
  141. hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
  142. spin_unlock_irq(&qp_table->lock);
  143. if (ret) {
  144. dev_err(hr_dev->dev, "QPC radix_tree_insert failed\n");
  145. goto err_put_irrl;
  146. }
  147. atomic_set(&hr_qp->refcount, 1);
  148. init_completion(&hr_qp->free);
  149. return 0;
  150. err_put_irrl:
  151. return ret;
  152. }
  153. static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
  154. struct hns_roce_qp *hr_qp)
  155. {
  156. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  157. struct device *dev = hr_dev->dev;
  158. int ret;
  159. if (!qpn)
  160. return -EINVAL;
  161. hr_qp->qpn = qpn;
  162. /* Alloc memory for QPC */
  163. ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn);
  164. if (ret) {
  165. dev_err(dev, "QPC table get failed\n");
  166. goto err_out;
  167. }
  168. /* Alloc memory for IRRL */
  169. ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
  170. if (ret) {
  171. dev_err(dev, "IRRL table get failed\n");
  172. goto err_put_qp;
  173. }
  174. if (hr_dev->caps.trrl_entry_sz) {
  175. /* Alloc memory for TRRL */
  176. ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table,
  177. hr_qp->qpn);
  178. if (ret) {
  179. dev_err(dev, "TRRL table get failed\n");
  180. goto err_put_irrl;
  181. }
  182. }
  183. spin_lock_irq(&qp_table->lock);
  184. ret = radix_tree_insert(&hr_dev->qp_table_tree,
  185. hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
  186. spin_unlock_irq(&qp_table->lock);
  187. if (ret) {
  188. dev_err(dev, "QPC radix_tree_insert failed\n");
  189. goto err_put_trrl;
  190. }
  191. atomic_set(&hr_qp->refcount, 1);
  192. init_completion(&hr_qp->free);
  193. return 0;
  194. err_put_trrl:
  195. if (hr_dev->caps.trrl_entry_sz)
  196. hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
  197. err_put_irrl:
  198. hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
  199. err_put_qp:
  200. hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
  201. err_out:
  202. return ret;
  203. }
  204. void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
  205. {
  206. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  207. unsigned long flags;
  208. spin_lock_irqsave(&qp_table->lock, flags);
  209. radix_tree_delete(&hr_dev->qp_table_tree,
  210. hr_qp->qpn & (hr_dev->caps.num_qps - 1));
  211. spin_unlock_irqrestore(&qp_table->lock, flags);
  212. }
  213. EXPORT_SYMBOL_GPL(hns_roce_qp_remove);
  214. void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
  215. {
  216. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  217. if (atomic_dec_and_test(&hr_qp->refcount))
  218. complete(&hr_qp->free);
  219. wait_for_completion(&hr_qp->free);
  220. if ((hr_qp->ibqp.qp_type) != IB_QPT_GSI) {
  221. if (hr_dev->caps.trrl_entry_sz)
  222. hns_roce_table_put(hr_dev, &qp_table->trrl_table,
  223. hr_qp->qpn);
  224. hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
  225. }
  226. }
  227. EXPORT_SYMBOL_GPL(hns_roce_qp_free);
  228. void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
  229. int cnt)
  230. {
  231. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  232. if (base_qpn < SQP_NUM)
  233. return;
  234. hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR);
  235. }
  236. EXPORT_SYMBOL_GPL(hns_roce_release_range_qp);
  237. static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
  238. struct ib_qp_cap *cap, int is_user, int has_srq,
  239. struct hns_roce_qp *hr_qp)
  240. {
  241. struct device *dev = hr_dev->dev;
  242. u32 max_cnt;
  243. /* Check the validity of QP support capacity */
  244. if (cap->max_recv_wr > hr_dev->caps.max_wqes ||
  245. cap->max_recv_sge > hr_dev->caps.max_rq_sg) {
  246. dev_err(dev, "RQ WR or sge error!max_recv_wr=%d max_recv_sge=%d\n",
  247. cap->max_recv_wr, cap->max_recv_sge);
  248. return -EINVAL;
  249. }
  250. /* If srq exit, set zero for relative number of rq */
  251. if (has_srq) {
  252. if (cap->max_recv_wr) {
  253. dev_dbg(dev, "srq no need config max_recv_wr\n");
  254. return -EINVAL;
  255. }
  256. hr_qp->rq.wqe_cnt = hr_qp->rq.max_gs = 0;
  257. } else {
  258. if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) {
  259. dev_err(dev, "user space no need config max_recv_wr max_recv_sge\n");
  260. return -EINVAL;
  261. }
  262. if (hr_dev->caps.min_wqes)
  263. max_cnt = max(cap->max_recv_wr, hr_dev->caps.min_wqes);
  264. else
  265. max_cnt = cap->max_recv_wr;
  266. hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt);
  267. if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) {
  268. dev_err(dev, "while setting rq size, rq.wqe_cnt too large\n");
  269. return -EINVAL;
  270. }
  271. max_cnt = max(1U, cap->max_recv_sge);
  272. hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt);
  273. if (hr_dev->caps.max_rq_sg <= 2)
  274. hr_qp->rq.wqe_shift =
  275. ilog2(hr_dev->caps.max_rq_desc_sz);
  276. else
  277. hr_qp->rq.wqe_shift =
  278. ilog2(hr_dev->caps.max_rq_desc_sz
  279. * hr_qp->rq.max_gs);
  280. }
  281. cap->max_recv_wr = hr_qp->rq.max_post = hr_qp->rq.wqe_cnt;
  282. cap->max_recv_sge = hr_qp->rq.max_gs;
  283. return 0;
  284. }
  285. static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev,
  286. struct ib_qp_cap *cap,
  287. struct hns_roce_qp *hr_qp,
  288. struct hns_roce_ib_create_qp *ucmd)
  289. {
  290. u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz);
  291. u8 max_sq_stride = ilog2(roundup_sq_stride);
  292. u32 page_size;
  293. u32 max_cnt;
  294. /* Sanity check SQ size before proceeding */
  295. if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes ||
  296. ucmd->log_sq_stride > max_sq_stride ||
  297. ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
  298. dev_err(hr_dev->dev, "check SQ size error!\n");
  299. return -EINVAL;
  300. }
  301. if (cap->max_send_sge > hr_dev->caps.max_sq_sg) {
  302. dev_err(hr_dev->dev, "SQ sge error! max_send_sge=%d\n",
  303. cap->max_send_sge);
  304. return -EINVAL;
  305. }
  306. hr_qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
  307. hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
  308. max_cnt = max(1U, cap->max_send_sge);
  309. if (hr_dev->caps.max_sq_sg <= 2)
  310. hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
  311. else
  312. hr_qp->sq.max_gs = max_cnt;
  313. if (hr_qp->sq.max_gs > 2)
  314. hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
  315. (hr_qp->sq.max_gs - 2));
  316. if ((hr_qp->sq.max_gs > 2) && (hr_dev->pci_dev->revision == 0x20)) {
  317. if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) {
  318. dev_err(hr_dev->dev,
  319. "The extended sge cnt error! sge_cnt=%d\n",
  320. hr_qp->sge.sge_cnt);
  321. return -EINVAL;
  322. }
  323. }
  324. hr_qp->sge.sge_shift = 4;
  325. /* Get buf size, SQ and RQ are aligned to page_szie */
  326. if (hr_dev->caps.max_sq_sg <= 2) {
  327. hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
  328. hr_qp->rq.wqe_shift), PAGE_SIZE) +
  329. HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
  330. hr_qp->sq.wqe_shift), PAGE_SIZE);
  331. hr_qp->sq.offset = 0;
  332. hr_qp->rq.offset = HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
  333. hr_qp->sq.wqe_shift), PAGE_SIZE);
  334. } else {
  335. page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
  336. hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
  337. hr_qp->rq.wqe_shift), page_size) +
  338. HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
  339. hr_qp->sge.sge_shift), page_size) +
  340. HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
  341. hr_qp->sq.wqe_shift), page_size);
  342. hr_qp->sq.offset = 0;
  343. if (hr_qp->sge.sge_cnt) {
  344. hr_qp->sge.offset = HNS_ROCE_ALOGN_UP(
  345. (hr_qp->sq.wqe_cnt <<
  346. hr_qp->sq.wqe_shift),
  347. page_size);
  348. hr_qp->rq.offset = hr_qp->sge.offset +
  349. HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
  350. hr_qp->sge.sge_shift),
  351. page_size);
  352. } else {
  353. hr_qp->rq.offset = HNS_ROCE_ALOGN_UP(
  354. (hr_qp->sq.wqe_cnt <<
  355. hr_qp->sq.wqe_shift),
  356. page_size);
  357. }
  358. }
  359. return 0;
  360. }
  361. static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev,
  362. struct ib_qp_cap *cap,
  363. struct hns_roce_qp *hr_qp)
  364. {
  365. struct device *dev = hr_dev->dev;
  366. u32 page_size;
  367. u32 max_cnt;
  368. int size;
  369. if (cap->max_send_wr > hr_dev->caps.max_wqes ||
  370. cap->max_send_sge > hr_dev->caps.max_sq_sg ||
  371. cap->max_inline_data > hr_dev->caps.max_sq_inline) {
  372. dev_err(dev, "SQ WR or sge or inline data error!\n");
  373. return -EINVAL;
  374. }
  375. hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz);
  376. hr_qp->sq_max_wqes_per_wr = 1;
  377. hr_qp->sq_spare_wqes = 0;
  378. if (hr_dev->caps.min_wqes)
  379. max_cnt = max(cap->max_send_wr, hr_dev->caps.min_wqes);
  380. else
  381. max_cnt = cap->max_send_wr;
  382. hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt);
  383. if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) {
  384. dev_err(dev, "while setting kernel sq size, sq.wqe_cnt too large\n");
  385. return -EINVAL;
  386. }
  387. /* Get data_seg numbers */
  388. max_cnt = max(1U, cap->max_send_sge);
  389. if (hr_dev->caps.max_sq_sg <= 2)
  390. hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
  391. else
  392. hr_qp->sq.max_gs = max_cnt;
  393. if (hr_qp->sq.max_gs > 2) {
  394. hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
  395. (hr_qp->sq.max_gs - 2));
  396. hr_qp->sge.sge_shift = 4;
  397. }
  398. /* ud sqwqe's sge use extend sge */
  399. if (hr_dev->caps.max_sq_sg > 2 && hr_qp->ibqp.qp_type == IB_QPT_GSI) {
  400. hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
  401. hr_qp->sq.max_gs);
  402. hr_qp->sge.sge_shift = 4;
  403. }
  404. if ((hr_qp->sq.max_gs > 2) && hr_dev->pci_dev->revision == 0x20) {
  405. if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) {
  406. dev_err(dev, "The extended sge cnt error! sge_cnt=%d\n",
  407. hr_qp->sge.sge_cnt);
  408. return -EINVAL;
  409. }
  410. }
  411. /* Get buf size, SQ and RQ are aligned to PAGE_SIZE */
  412. page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
  413. hr_qp->sq.offset = 0;
  414. size = HNS_ROCE_ALOGN_UP(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift,
  415. page_size);
  416. if (hr_dev->caps.max_sq_sg > 2 && hr_qp->sge.sge_cnt) {
  417. hr_qp->sge.offset = size;
  418. size += HNS_ROCE_ALOGN_UP(hr_qp->sge.sge_cnt <<
  419. hr_qp->sge.sge_shift, page_size);
  420. }
  421. hr_qp->rq.offset = size;
  422. size += HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << hr_qp->rq.wqe_shift),
  423. page_size);
  424. hr_qp->buff_size = size;
  425. /* Get wr and sge number which send */
  426. cap->max_send_wr = hr_qp->sq.max_post = hr_qp->sq.wqe_cnt;
  427. cap->max_send_sge = hr_qp->sq.max_gs;
  428. /* We don't support inline sends for kernel QPs (yet) */
  429. cap->max_inline_data = 0;
  430. return 0;
  431. }
  432. static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr)
  433. {
  434. if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr)
  435. return 0;
  436. return 1;
  437. }
  438. static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr)
  439. {
  440. if (attr->qp_type == IB_QPT_XRC_INI ||
  441. attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
  442. !attr->cap.max_recv_wr)
  443. return 0;
  444. return 1;
  445. }
  446. static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
  447. struct ib_pd *ib_pd,
  448. struct ib_qp_init_attr *init_attr,
  449. struct ib_udata *udata, unsigned long sqpn,
  450. struct hns_roce_qp *hr_qp)
  451. {
  452. struct device *dev = hr_dev->dev;
  453. struct hns_roce_ib_create_qp ucmd;
  454. struct hns_roce_ib_create_qp_resp resp = {};
  455. unsigned long qpn = 0;
  456. int ret = 0;
  457. u32 page_shift;
  458. u32 npages;
  459. int i;
  460. mutex_init(&hr_qp->mutex);
  461. spin_lock_init(&hr_qp->sq.lock);
  462. spin_lock_init(&hr_qp->rq.lock);
  463. hr_qp->state = IB_QPS_RESET;
  464. hr_qp->ibqp.qp_type = init_attr->qp_type;
  465. if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
  466. hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_ALL_WR);
  467. else
  468. hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_REQ_WR);
  469. ret = hns_roce_set_rq_size(hr_dev, &init_attr->cap, !!ib_pd->uobject,
  470. !!init_attr->srq, hr_qp);
  471. if (ret) {
  472. dev_err(dev, "hns_roce_set_rq_size failed\n");
  473. goto err_out;
  474. }
  475. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
  476. /* allocate recv inline buf */
  477. hr_qp->rq_inl_buf.wqe_list = kcalloc(hr_qp->rq.wqe_cnt,
  478. sizeof(struct hns_roce_rinl_wqe),
  479. GFP_KERNEL);
  480. if (!hr_qp->rq_inl_buf.wqe_list) {
  481. ret = -ENOMEM;
  482. goto err_out;
  483. }
  484. hr_qp->rq_inl_buf.wqe_cnt = hr_qp->rq.wqe_cnt;
  485. /* Firstly, allocate a list of sge space buffer */
  486. hr_qp->rq_inl_buf.wqe_list[0].sg_list =
  487. kcalloc(hr_qp->rq_inl_buf.wqe_cnt,
  488. init_attr->cap.max_recv_sge *
  489. sizeof(struct hns_roce_rinl_sge),
  490. GFP_KERNEL);
  491. if (!hr_qp->rq_inl_buf.wqe_list[0].sg_list) {
  492. ret = -ENOMEM;
  493. goto err_wqe_list;
  494. }
  495. for (i = 1; i < hr_qp->rq_inl_buf.wqe_cnt; i++)
  496. /* Secondly, reallocate the buffer */
  497. hr_qp->rq_inl_buf.wqe_list[i].sg_list =
  498. &hr_qp->rq_inl_buf.wqe_list[0].sg_list[i *
  499. init_attr->cap.max_recv_sge];
  500. }
  501. if (ib_pd->uobject) {
  502. if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
  503. dev_err(dev, "ib_copy_from_udata error for create qp\n");
  504. ret = -EFAULT;
  505. goto err_rq_sge_list;
  506. }
  507. ret = hns_roce_set_user_sq_size(hr_dev, &init_attr->cap, hr_qp,
  508. &ucmd);
  509. if (ret) {
  510. dev_err(dev, "hns_roce_set_user_sq_size error for create qp\n");
  511. goto err_rq_sge_list;
  512. }
  513. hr_qp->umem = ib_umem_get(ib_pd->uobject->context,
  514. ucmd.buf_addr, hr_qp->buff_size, 0,
  515. 0);
  516. if (IS_ERR(hr_qp->umem)) {
  517. dev_err(dev, "ib_umem_get error for create qp\n");
  518. ret = PTR_ERR(hr_qp->umem);
  519. goto err_rq_sge_list;
  520. }
  521. hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
  522. if (hr_dev->caps.mtt_buf_pg_sz) {
  523. npages = (ib_umem_page_count(hr_qp->umem) +
  524. (1 << hr_dev->caps.mtt_buf_pg_sz) - 1) /
  525. (1 << hr_dev->caps.mtt_buf_pg_sz);
  526. page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
  527. ret = hns_roce_mtt_init(hr_dev, npages,
  528. page_shift,
  529. &hr_qp->mtt);
  530. } else {
  531. ret = hns_roce_mtt_init(hr_dev,
  532. ib_umem_page_count(hr_qp->umem),
  533. hr_qp->umem->page_shift,
  534. &hr_qp->mtt);
  535. }
  536. if (ret) {
  537. dev_err(dev, "hns_roce_mtt_init error for create qp\n");
  538. goto err_buf;
  539. }
  540. ret = hns_roce_ib_umem_write_mtt(hr_dev, &hr_qp->mtt,
  541. hr_qp->umem);
  542. if (ret) {
  543. dev_err(dev, "hns_roce_ib_umem_write_mtt error for create qp\n");
  544. goto err_mtt;
  545. }
  546. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) &&
  547. (udata->inlen >= sizeof(ucmd)) &&
  548. (udata->outlen >= sizeof(resp)) &&
  549. hns_roce_qp_has_sq(init_attr)) {
  550. ret = hns_roce_db_map_user(
  551. to_hr_ucontext(ib_pd->uobject->context),
  552. ucmd.sdb_addr, &hr_qp->sdb);
  553. if (ret) {
  554. dev_err(dev, "sq record doorbell map failed!\n");
  555. goto err_mtt;
  556. }
  557. /* indicate kernel supports sq record db */
  558. resp.cap_flags |= HNS_ROCE_SUPPORT_SQ_RECORD_DB;
  559. hr_qp->sdb_en = 1;
  560. }
  561. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  562. (udata->outlen >= sizeof(resp)) &&
  563. hns_roce_qp_has_rq(init_attr)) {
  564. ret = hns_roce_db_map_user(
  565. to_hr_ucontext(ib_pd->uobject->context),
  566. ucmd.db_addr, &hr_qp->rdb);
  567. if (ret) {
  568. dev_err(dev, "rq record doorbell map failed!\n");
  569. goto err_sq_dbmap;
  570. }
  571. }
  572. } else {
  573. if (init_attr->create_flags &
  574. IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
  575. dev_err(dev, "init_attr->create_flags error!\n");
  576. ret = -EINVAL;
  577. goto err_rq_sge_list;
  578. }
  579. if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) {
  580. dev_err(dev, "init_attr->create_flags error!\n");
  581. ret = -EINVAL;
  582. goto err_rq_sge_list;
  583. }
  584. /* Set SQ size */
  585. ret = hns_roce_set_kernel_sq_size(hr_dev, &init_attr->cap,
  586. hr_qp);
  587. if (ret) {
  588. dev_err(dev, "hns_roce_set_kernel_sq_size error!\n");
  589. goto err_rq_sge_list;
  590. }
  591. /* QP doorbell register address */
  592. hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset +
  593. DB_REG_OFFSET * hr_dev->priv_uar.index;
  594. hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset +
  595. DB_REG_OFFSET * hr_dev->priv_uar.index;
  596. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  597. hns_roce_qp_has_rq(init_attr)) {
  598. ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0);
  599. if (ret) {
  600. dev_err(dev, "rq record doorbell alloc failed!\n");
  601. goto err_rq_sge_list;
  602. }
  603. *hr_qp->rdb.db_record = 0;
  604. hr_qp->rdb_en = 1;
  605. }
  606. /* Allocate QP buf */
  607. page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
  608. if (hns_roce_buf_alloc(hr_dev, hr_qp->buff_size,
  609. (1 << page_shift) * 2,
  610. &hr_qp->hr_buf, page_shift)) {
  611. dev_err(dev, "hns_roce_buf_alloc error!\n");
  612. ret = -ENOMEM;
  613. goto err_db;
  614. }
  615. hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
  616. /* Write MTT */
  617. ret = hns_roce_mtt_init(hr_dev, hr_qp->hr_buf.npages,
  618. hr_qp->hr_buf.page_shift, &hr_qp->mtt);
  619. if (ret) {
  620. dev_err(dev, "hns_roce_mtt_init error for kernel create qp\n");
  621. goto err_buf;
  622. }
  623. ret = hns_roce_buf_write_mtt(hr_dev, &hr_qp->mtt,
  624. &hr_qp->hr_buf);
  625. if (ret) {
  626. dev_err(dev, "hns_roce_buf_write_mtt error for kernel create qp\n");
  627. goto err_mtt;
  628. }
  629. hr_qp->sq.wrid = kmalloc_array(hr_qp->sq.wqe_cnt, sizeof(u64),
  630. GFP_KERNEL);
  631. hr_qp->rq.wrid = kmalloc_array(hr_qp->rq.wqe_cnt, sizeof(u64),
  632. GFP_KERNEL);
  633. if (!hr_qp->sq.wrid || !hr_qp->rq.wrid) {
  634. ret = -ENOMEM;
  635. goto err_wrid;
  636. }
  637. }
  638. if (sqpn) {
  639. qpn = sqpn;
  640. } else {
  641. /* Get QPN */
  642. ret = hns_roce_reserve_range_qp(hr_dev, 1, 1, &qpn);
  643. if (ret) {
  644. dev_err(dev, "hns_roce_reserve_range_qp alloc qpn error\n");
  645. goto err_wrid;
  646. }
  647. }
  648. if (init_attr->qp_type == IB_QPT_GSI &&
  649. hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
  650. /* In v1 engine, GSI QP context in RoCE engine's register */
  651. ret = hns_roce_gsi_qp_alloc(hr_dev, qpn, hr_qp);
  652. if (ret) {
  653. dev_err(dev, "hns_roce_qp_alloc failed!\n");
  654. goto err_qpn;
  655. }
  656. } else {
  657. ret = hns_roce_qp_alloc(hr_dev, qpn, hr_qp);
  658. if (ret) {
  659. dev_err(dev, "hns_roce_qp_alloc failed!\n");
  660. goto err_qpn;
  661. }
  662. }
  663. if (sqpn)
  664. hr_qp->doorbell_qpn = 1;
  665. else
  666. hr_qp->doorbell_qpn = cpu_to_le64(hr_qp->qpn);
  667. if (ib_pd->uobject && (udata->outlen >= sizeof(resp)) &&
  668. (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)) {
  669. /* indicate kernel supports rq record db */
  670. resp.cap_flags |= HNS_ROCE_SUPPORT_RQ_RECORD_DB;
  671. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  672. if (ret)
  673. goto err_qp;
  674. hr_qp->rdb_en = 1;
  675. }
  676. hr_qp->event = hns_roce_ib_qp_event;
  677. return 0;
  678. err_qp:
  679. if (init_attr->qp_type == IB_QPT_GSI &&
  680. hr_dev->hw_rev == HNS_ROCE_HW_VER1)
  681. hns_roce_qp_remove(hr_dev, hr_qp);
  682. else
  683. hns_roce_qp_free(hr_dev, hr_qp);
  684. err_qpn:
  685. if (!sqpn)
  686. hns_roce_release_range_qp(hr_dev, qpn, 1);
  687. err_wrid:
  688. if (ib_pd->uobject) {
  689. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  690. (udata->outlen >= sizeof(resp)) &&
  691. hns_roce_qp_has_rq(init_attr))
  692. hns_roce_db_unmap_user(
  693. to_hr_ucontext(ib_pd->uobject->context),
  694. &hr_qp->rdb);
  695. } else {
  696. kfree(hr_qp->sq.wrid);
  697. kfree(hr_qp->rq.wrid);
  698. }
  699. err_sq_dbmap:
  700. if (ib_pd->uobject)
  701. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) &&
  702. (udata->inlen >= sizeof(ucmd)) &&
  703. (udata->outlen >= sizeof(resp)) &&
  704. hns_roce_qp_has_sq(init_attr))
  705. hns_roce_db_unmap_user(
  706. to_hr_ucontext(ib_pd->uobject->context),
  707. &hr_qp->sdb);
  708. err_mtt:
  709. hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
  710. err_buf:
  711. if (ib_pd->uobject)
  712. ib_umem_release(hr_qp->umem);
  713. else
  714. hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
  715. err_db:
  716. if (!ib_pd->uobject && hns_roce_qp_has_rq(init_attr) &&
  717. (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB))
  718. hns_roce_free_db(hr_dev, &hr_qp->rdb);
  719. err_rq_sge_list:
  720. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
  721. kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
  722. err_wqe_list:
  723. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
  724. kfree(hr_qp->rq_inl_buf.wqe_list);
  725. err_out:
  726. return ret;
  727. }
  728. struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
  729. struct ib_qp_init_attr *init_attr,
  730. struct ib_udata *udata)
  731. {
  732. struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
  733. struct device *dev = hr_dev->dev;
  734. struct hns_roce_sqp *hr_sqp;
  735. struct hns_roce_qp *hr_qp;
  736. int ret;
  737. switch (init_attr->qp_type) {
  738. case IB_QPT_RC: {
  739. hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
  740. if (!hr_qp)
  741. return ERR_PTR(-ENOMEM);
  742. ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 0,
  743. hr_qp);
  744. if (ret) {
  745. dev_err(dev, "Create RC QP failed\n");
  746. kfree(hr_qp);
  747. return ERR_PTR(ret);
  748. }
  749. hr_qp->ibqp.qp_num = hr_qp->qpn;
  750. break;
  751. }
  752. case IB_QPT_GSI: {
  753. /* Userspace is not allowed to create special QPs: */
  754. if (pd->uobject) {
  755. dev_err(dev, "not support usr space GSI\n");
  756. return ERR_PTR(-EINVAL);
  757. }
  758. hr_sqp = kzalloc(sizeof(*hr_sqp), GFP_KERNEL);
  759. if (!hr_sqp)
  760. return ERR_PTR(-ENOMEM);
  761. hr_qp = &hr_sqp->hr_qp;
  762. hr_qp->port = init_attr->port_num - 1;
  763. hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
  764. /* when hw version is v1, the sqpn is allocated */
  765. if (hr_dev->caps.max_sq_sg <= 2)
  766. hr_qp->ibqp.qp_num = HNS_ROCE_MAX_PORTS +
  767. hr_dev->iboe.phy_port[hr_qp->port];
  768. else
  769. hr_qp->ibqp.qp_num = 1;
  770. ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata,
  771. hr_qp->ibqp.qp_num, hr_qp);
  772. if (ret) {
  773. dev_err(dev, "Create GSI QP failed!\n");
  774. kfree(hr_sqp);
  775. return ERR_PTR(ret);
  776. }
  777. break;
  778. }
  779. default:{
  780. dev_err(dev, "not support QP type %d\n", init_attr->qp_type);
  781. return ERR_PTR(-EINVAL);
  782. }
  783. }
  784. return &hr_qp->ibqp;
  785. }
  786. EXPORT_SYMBOL_GPL(hns_roce_create_qp);
  787. int to_hr_qp_type(int qp_type)
  788. {
  789. int transport_type;
  790. if (qp_type == IB_QPT_RC)
  791. transport_type = SERV_TYPE_RC;
  792. else if (qp_type == IB_QPT_UC)
  793. transport_type = SERV_TYPE_UC;
  794. else if (qp_type == IB_QPT_UD)
  795. transport_type = SERV_TYPE_UD;
  796. else if (qp_type == IB_QPT_GSI)
  797. transport_type = SERV_TYPE_UD;
  798. else
  799. transport_type = -1;
  800. return transport_type;
  801. }
  802. EXPORT_SYMBOL_GPL(to_hr_qp_type);
  803. int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  804. int attr_mask, struct ib_udata *udata)
  805. {
  806. struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  807. struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
  808. enum ib_qp_state cur_state, new_state;
  809. struct device *dev = hr_dev->dev;
  810. int ret = -EINVAL;
  811. int p;
  812. enum ib_mtu active_mtu;
  813. mutex_lock(&hr_qp->mutex);
  814. cur_state = attr_mask & IB_QP_CUR_STATE ?
  815. attr->cur_qp_state : (enum ib_qp_state)hr_qp->state;
  816. new_state = attr_mask & IB_QP_STATE ?
  817. attr->qp_state : cur_state;
  818. if (ibqp->uobject &&
  819. (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) {
  820. if (hr_qp->sdb_en == 1) {
  821. hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
  822. hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
  823. } else {
  824. dev_warn(dev, "flush cqe is not supported in userspace!\n");
  825. goto out;
  826. }
  827. }
  828. if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
  829. IB_LINK_LAYER_ETHERNET)) {
  830. dev_err(dev, "ib_modify_qp_is_ok failed\n");
  831. goto out;
  832. }
  833. if ((attr_mask & IB_QP_PORT) &&
  834. (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) {
  835. dev_err(dev, "attr port_num invalid.attr->port_num=%d\n",
  836. attr->port_num);
  837. goto out;
  838. }
  839. if (attr_mask & IB_QP_PKEY_INDEX) {
  840. p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
  841. if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) {
  842. dev_err(dev, "attr pkey_index invalid.attr->pkey_index=%d\n",
  843. attr->pkey_index);
  844. goto out;
  845. }
  846. }
  847. if (attr_mask & IB_QP_PATH_MTU) {
  848. p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
  849. active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu);
  850. if ((hr_dev->caps.max_mtu == IB_MTU_4096 &&
  851. attr->path_mtu > IB_MTU_4096) ||
  852. (hr_dev->caps.max_mtu == IB_MTU_2048 &&
  853. attr->path_mtu > IB_MTU_2048) ||
  854. attr->path_mtu < IB_MTU_256 ||
  855. attr->path_mtu > active_mtu) {
  856. dev_err(dev, "attr path_mtu(%d)invalid while modify qp",
  857. attr->path_mtu);
  858. goto out;
  859. }
  860. }
  861. if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
  862. attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) {
  863. dev_err(dev, "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n",
  864. attr->max_rd_atomic);
  865. goto out;
  866. }
  867. if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
  868. attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) {
  869. dev_err(dev, "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n",
  870. attr->max_dest_rd_atomic);
  871. goto out;
  872. }
  873. if (cur_state == new_state && cur_state == IB_QPS_RESET) {
  874. if (hr_dev->caps.min_wqes) {
  875. ret = -EPERM;
  876. dev_err(dev, "cur_state=%d new_state=%d\n", cur_state,
  877. new_state);
  878. } else {
  879. ret = 0;
  880. }
  881. goto out;
  882. }
  883. ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state,
  884. new_state);
  885. out:
  886. mutex_unlock(&hr_qp->mutex);
  887. return ret;
  888. }
  889. void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq)
  890. __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
  891. {
  892. if (send_cq == recv_cq) {
  893. spin_lock_irq(&send_cq->lock);
  894. __acquire(&recv_cq->lock);
  895. } else if (send_cq->cqn < recv_cq->cqn) {
  896. spin_lock_irq(&send_cq->lock);
  897. spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
  898. } else {
  899. spin_lock_irq(&recv_cq->lock);
  900. spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
  901. }
  902. }
  903. EXPORT_SYMBOL_GPL(hns_roce_lock_cqs);
  904. void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
  905. struct hns_roce_cq *recv_cq) __releases(&send_cq->lock)
  906. __releases(&recv_cq->lock)
  907. {
  908. if (send_cq == recv_cq) {
  909. __release(&recv_cq->lock);
  910. spin_unlock_irq(&send_cq->lock);
  911. } else if (send_cq->cqn < recv_cq->cqn) {
  912. spin_unlock(&recv_cq->lock);
  913. spin_unlock_irq(&send_cq->lock);
  914. } else {
  915. spin_unlock(&send_cq->lock);
  916. spin_unlock_irq(&recv_cq->lock);
  917. }
  918. }
  919. EXPORT_SYMBOL_GPL(hns_roce_unlock_cqs);
  920. static void *get_wqe(struct hns_roce_qp *hr_qp, int offset)
  921. {
  922. return hns_roce_buf_offset(&hr_qp->hr_buf, offset);
  923. }
  924. void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n)
  925. {
  926. return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift));
  927. }
  928. EXPORT_SYMBOL_GPL(get_recv_wqe);
  929. void *get_send_wqe(struct hns_roce_qp *hr_qp, int n)
  930. {
  931. return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift));
  932. }
  933. EXPORT_SYMBOL_GPL(get_send_wqe);
  934. void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n)
  935. {
  936. return hns_roce_buf_offset(&hr_qp->hr_buf, hr_qp->sge.offset +
  937. (n << hr_qp->sge.sge_shift));
  938. }
  939. EXPORT_SYMBOL_GPL(get_send_extend_sge);
  940. bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
  941. struct ib_cq *ib_cq)
  942. {
  943. struct hns_roce_cq *hr_cq;
  944. u32 cur;
  945. cur = hr_wq->head - hr_wq->tail;
  946. if (likely(cur + nreq < hr_wq->max_post))
  947. return false;
  948. hr_cq = to_hr_cq(ib_cq);
  949. spin_lock(&hr_cq->lock);
  950. cur = hr_wq->head - hr_wq->tail;
  951. spin_unlock(&hr_cq->lock);
  952. return cur + nreq >= hr_wq->max_post;
  953. }
  954. EXPORT_SYMBOL_GPL(hns_roce_wq_overflow);
  955. int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
  956. {
  957. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  958. int reserved_from_top = 0;
  959. int reserved_from_bot;
  960. int ret;
  961. spin_lock_init(&qp_table->lock);
  962. INIT_RADIX_TREE(&hr_dev->qp_table_tree, GFP_ATOMIC);
  963. /* In hw v1, a port include two SQP, six ports total 12 */
  964. if (hr_dev->caps.max_sq_sg <= 2)
  965. reserved_from_bot = SQP_NUM;
  966. else
  967. reserved_from_bot = hr_dev->caps.reserved_qps;
  968. ret = hns_roce_bitmap_init(&qp_table->bitmap, hr_dev->caps.num_qps,
  969. hr_dev->caps.num_qps - 1, reserved_from_bot,
  970. reserved_from_top);
  971. if (ret) {
  972. dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n",
  973. ret);
  974. return ret;
  975. }
  976. return 0;
  977. }
  978. void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev)
  979. {
  980. hns_roce_bitmap_cleanup(&hr_dev->qp_table.bitmap);
  981. }