i40iw_uk.c 33 KB

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  1. /*******************************************************************************
  2. *
  3. * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenFabrics.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. *
  33. *******************************************************************************/
  34. #include "i40iw_osdep.h"
  35. #include "i40iw_status.h"
  36. #include "i40iw_d.h"
  37. #include "i40iw_user.h"
  38. #include "i40iw_register.h"
  39. static u32 nop_signature = 0x55550000;
  40. /**
  41. * i40iw_nop_1 - insert a nop wqe and move head. no post work
  42. * @qp: hw qp ptr
  43. */
  44. static enum i40iw_status_code i40iw_nop_1(struct i40iw_qp_uk *qp)
  45. {
  46. u64 header, *wqe;
  47. u64 *wqe_0 = NULL;
  48. u32 wqe_idx, peek_head;
  49. bool signaled = false;
  50. if (!qp->sq_ring.head)
  51. return I40IW_ERR_PARAM;
  52. wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
  53. wqe = qp->sq_base[wqe_idx].elem;
  54. qp->sq_wrtrk_array[wqe_idx].wqe_size = I40IW_QP_WQE_MIN_SIZE;
  55. peek_head = (qp->sq_ring.head + 1) % qp->sq_ring.size;
  56. wqe_0 = qp->sq_base[peek_head].elem;
  57. if (peek_head)
  58. wqe_0[3] = LS_64(!qp->swqe_polarity, I40IWQPSQ_VALID);
  59. else
  60. wqe_0[3] = LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
  61. set_64bit_val(wqe, 0, 0);
  62. set_64bit_val(wqe, 8, 0);
  63. set_64bit_val(wqe, 16, 0);
  64. header = LS_64(I40IWQP_OP_NOP, I40IWQPSQ_OPCODE) |
  65. LS_64(signaled, I40IWQPSQ_SIGCOMPL) |
  66. LS_64(qp->swqe_polarity, I40IWQPSQ_VALID) | nop_signature++;
  67. wmb(); /* Memory barrier to ensure data is written before valid bit is set */
  68. set_64bit_val(wqe, 24, header);
  69. return 0;
  70. }
  71. /**
  72. * i40iw_qp_post_wr - post wr to hrdware
  73. * @qp: hw qp ptr
  74. */
  75. void i40iw_qp_post_wr(struct i40iw_qp_uk *qp)
  76. {
  77. u64 temp;
  78. u32 hw_sq_tail;
  79. u32 sw_sq_head;
  80. mb(); /* valid bit is written and loads completed before reading shadow */
  81. /* read the doorbell shadow area */
  82. get_64bit_val(qp->shadow_area, 0, &temp);
  83. hw_sq_tail = (u32)RS_64(temp, I40IW_QP_DBSA_HW_SQ_TAIL);
  84. sw_sq_head = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
  85. if (sw_sq_head != hw_sq_tail) {
  86. if (sw_sq_head > qp->initial_ring.head) {
  87. if ((hw_sq_tail >= qp->initial_ring.head) &&
  88. (hw_sq_tail < sw_sq_head)) {
  89. writel(qp->qp_id, qp->wqe_alloc_reg);
  90. }
  91. } else if (sw_sq_head != qp->initial_ring.head) {
  92. if ((hw_sq_tail >= qp->initial_ring.head) ||
  93. (hw_sq_tail < sw_sq_head)) {
  94. writel(qp->qp_id, qp->wqe_alloc_reg);
  95. }
  96. }
  97. }
  98. qp->initial_ring.head = qp->sq_ring.head;
  99. }
  100. /**
  101. * i40iw_qp_ring_push_db - ring qp doorbell
  102. * @qp: hw qp ptr
  103. * @wqe_idx: wqe index
  104. */
  105. static void i40iw_qp_ring_push_db(struct i40iw_qp_uk *qp, u32 wqe_idx)
  106. {
  107. set_32bit_val(qp->push_db, 0, LS_32((wqe_idx >> 2), I40E_PFPE_WQEALLOC_WQE_DESC_INDEX) | qp->qp_id);
  108. qp->initial_ring.head = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
  109. }
  110. /**
  111. * i40iw_qp_get_next_send_wqe - return next wqe ptr
  112. * @qp: hw qp ptr
  113. * @wqe_idx: return wqe index
  114. * @wqe_size: size of sq wqe
  115. */
  116. u64 *i40iw_qp_get_next_send_wqe(struct i40iw_qp_uk *qp,
  117. u32 *wqe_idx,
  118. u8 wqe_size,
  119. u32 total_size,
  120. u64 wr_id
  121. )
  122. {
  123. u64 *wqe = NULL;
  124. u64 wqe_ptr;
  125. u32 peek_head = 0;
  126. u16 offset;
  127. enum i40iw_status_code ret_code = 0;
  128. u8 nop_wqe_cnt = 0, i;
  129. u64 *wqe_0 = NULL;
  130. *wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
  131. if (!*wqe_idx)
  132. qp->swqe_polarity = !qp->swqe_polarity;
  133. wqe_ptr = (uintptr_t)qp->sq_base[*wqe_idx].elem;
  134. offset = (u16)(wqe_ptr) & 0x7F;
  135. if ((offset + wqe_size) > I40IW_QP_WQE_MAX_SIZE) {
  136. nop_wqe_cnt = (u8)(I40IW_QP_WQE_MAX_SIZE - offset) / I40IW_QP_WQE_MIN_SIZE;
  137. for (i = 0; i < nop_wqe_cnt; i++) {
  138. i40iw_nop_1(qp);
  139. I40IW_RING_MOVE_HEAD(qp->sq_ring, ret_code);
  140. if (ret_code)
  141. return NULL;
  142. }
  143. *wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
  144. if (!*wqe_idx)
  145. qp->swqe_polarity = !qp->swqe_polarity;
  146. }
  147. if (((*wqe_idx & 3) == 1) && (wqe_size == I40IW_WQE_SIZE_64)) {
  148. i40iw_nop_1(qp);
  149. I40IW_RING_MOVE_HEAD(qp->sq_ring, ret_code);
  150. if (ret_code)
  151. return NULL;
  152. *wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
  153. if (!*wqe_idx)
  154. qp->swqe_polarity = !qp->swqe_polarity;
  155. }
  156. I40IW_RING_MOVE_HEAD_BY_COUNT(qp->sq_ring,
  157. wqe_size / I40IW_QP_WQE_MIN_SIZE, ret_code);
  158. if (ret_code)
  159. return NULL;
  160. wqe = qp->sq_base[*wqe_idx].elem;
  161. peek_head = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
  162. wqe_0 = qp->sq_base[peek_head].elem;
  163. if (((peek_head & 3) == 1) || ((peek_head & 3) == 3)) {
  164. if (RS_64(wqe_0[3], I40IWQPSQ_VALID) != !qp->swqe_polarity)
  165. wqe_0[3] = LS_64(!qp->swqe_polarity, I40IWQPSQ_VALID);
  166. }
  167. qp->sq_wrtrk_array[*wqe_idx].wrid = wr_id;
  168. qp->sq_wrtrk_array[*wqe_idx].wr_len = total_size;
  169. qp->sq_wrtrk_array[*wqe_idx].wqe_size = wqe_size;
  170. return wqe;
  171. }
  172. /**
  173. * i40iw_set_fragment - set fragment in wqe
  174. * @wqe: wqe for setting fragment
  175. * @offset: offset value
  176. * @sge: sge length and stag
  177. */
  178. static void i40iw_set_fragment(u64 *wqe, u32 offset, struct i40iw_sge *sge)
  179. {
  180. if (sge) {
  181. set_64bit_val(wqe, offset, LS_64(sge->tag_off, I40IWQPSQ_FRAG_TO));
  182. set_64bit_val(wqe, (offset + 8),
  183. (LS_64(sge->len, I40IWQPSQ_FRAG_LEN) |
  184. LS_64(sge->stag, I40IWQPSQ_FRAG_STAG)));
  185. }
  186. }
  187. /**
  188. * i40iw_qp_get_next_recv_wqe - get next qp's rcv wqe
  189. * @qp: hw qp ptr
  190. * @wqe_idx: return wqe index
  191. */
  192. u64 *i40iw_qp_get_next_recv_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx)
  193. {
  194. u64 *wqe = NULL;
  195. enum i40iw_status_code ret_code;
  196. if (I40IW_RING_FULL_ERR(qp->rq_ring))
  197. return NULL;
  198. I40IW_ATOMIC_RING_MOVE_HEAD(qp->rq_ring, *wqe_idx, ret_code);
  199. if (ret_code)
  200. return NULL;
  201. if (!*wqe_idx)
  202. qp->rwqe_polarity = !qp->rwqe_polarity;
  203. /* rq_wqe_size_multiplier is no of qwords in one rq wqe */
  204. wqe = qp->rq_base[*wqe_idx * (qp->rq_wqe_size_multiplier >> 2)].elem;
  205. return wqe;
  206. }
  207. /**
  208. * i40iw_rdma_write - rdma write operation
  209. * @qp: hw qp ptr
  210. * @info: post sq information
  211. * @post_sq: flag to post sq
  212. */
  213. static enum i40iw_status_code i40iw_rdma_write(struct i40iw_qp_uk *qp,
  214. struct i40iw_post_sq_info *info,
  215. bool post_sq)
  216. {
  217. u64 header;
  218. u64 *wqe;
  219. struct i40iw_rdma_write *op_info;
  220. u32 i, wqe_idx;
  221. u32 total_size = 0, byte_off;
  222. enum i40iw_status_code ret_code;
  223. bool read_fence = false;
  224. u8 wqe_size;
  225. op_info = &info->op.rdma_write;
  226. if (op_info->num_lo_sges > qp->max_sq_frag_cnt)
  227. return I40IW_ERR_INVALID_FRAG_COUNT;
  228. for (i = 0; i < op_info->num_lo_sges; i++)
  229. total_size += op_info->lo_sg_list[i].len;
  230. if (total_size > I40IW_MAX_OUTBOUND_MESSAGE_SIZE)
  231. return I40IW_ERR_QP_INVALID_MSG_SIZE;
  232. read_fence |= info->read_fence;
  233. ret_code = i40iw_fragcnt_to_wqesize_sq(op_info->num_lo_sges, &wqe_size);
  234. if (ret_code)
  235. return ret_code;
  236. wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, total_size, info->wr_id);
  237. if (!wqe)
  238. return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
  239. set_64bit_val(wqe, 16,
  240. LS_64(op_info->rem_addr.tag_off, I40IWQPSQ_FRAG_TO));
  241. if (!op_info->rem_addr.stag)
  242. return I40IW_ERR_BAD_STAG;
  243. header = LS_64(op_info->rem_addr.stag, I40IWQPSQ_REMSTAG) |
  244. LS_64(I40IWQP_OP_RDMA_WRITE, I40IWQPSQ_OPCODE) |
  245. LS_64((op_info->num_lo_sges > 1 ? (op_info->num_lo_sges - 1) : 0), I40IWQPSQ_ADDFRAGCNT) |
  246. LS_64(read_fence, I40IWQPSQ_READFENCE) |
  247. LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
  248. LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
  249. LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
  250. i40iw_set_fragment(wqe, 0, op_info->lo_sg_list);
  251. for (i = 1, byte_off = 32; i < op_info->num_lo_sges; i++) {
  252. i40iw_set_fragment(wqe, byte_off, &op_info->lo_sg_list[i]);
  253. byte_off += 16;
  254. }
  255. wmb(); /* make sure WQE is populated before valid bit is set */
  256. set_64bit_val(wqe, 24, header);
  257. if (post_sq)
  258. i40iw_qp_post_wr(qp);
  259. return 0;
  260. }
  261. /**
  262. * i40iw_rdma_read - rdma read command
  263. * @qp: hw qp ptr
  264. * @info: post sq information
  265. * @inv_stag: flag for inv_stag
  266. * @post_sq: flag to post sq
  267. */
  268. static enum i40iw_status_code i40iw_rdma_read(struct i40iw_qp_uk *qp,
  269. struct i40iw_post_sq_info *info,
  270. bool inv_stag,
  271. bool post_sq)
  272. {
  273. u64 *wqe;
  274. struct i40iw_rdma_read *op_info;
  275. u64 header;
  276. u32 wqe_idx;
  277. enum i40iw_status_code ret_code;
  278. u8 wqe_size;
  279. bool local_fence = false;
  280. op_info = &info->op.rdma_read;
  281. ret_code = i40iw_fragcnt_to_wqesize_sq(1, &wqe_size);
  282. if (ret_code)
  283. return ret_code;
  284. wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, op_info->lo_addr.len, info->wr_id);
  285. if (!wqe)
  286. return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
  287. local_fence |= info->local_fence;
  288. set_64bit_val(wqe, 16, LS_64(op_info->rem_addr.tag_off, I40IWQPSQ_FRAG_TO));
  289. header = LS_64(op_info->rem_addr.stag, I40IWQPSQ_REMSTAG) |
  290. LS_64((inv_stag ? I40IWQP_OP_RDMA_READ_LOC_INV : I40IWQP_OP_RDMA_READ), I40IWQPSQ_OPCODE) |
  291. LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
  292. LS_64(local_fence, I40IWQPSQ_LOCALFENCE) |
  293. LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
  294. LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
  295. i40iw_set_fragment(wqe, 0, &op_info->lo_addr);
  296. wmb(); /* make sure WQE is populated before valid bit is set */
  297. set_64bit_val(wqe, 24, header);
  298. if (post_sq)
  299. i40iw_qp_post_wr(qp);
  300. return 0;
  301. }
  302. /**
  303. * i40iw_send - rdma send command
  304. * @qp: hw qp ptr
  305. * @info: post sq information
  306. * @stag_to_inv: stag_to_inv value
  307. * @post_sq: flag to post sq
  308. */
  309. static enum i40iw_status_code i40iw_send(struct i40iw_qp_uk *qp,
  310. struct i40iw_post_sq_info *info,
  311. u32 stag_to_inv,
  312. bool post_sq)
  313. {
  314. u64 *wqe;
  315. struct i40iw_post_send *op_info;
  316. u64 header;
  317. u32 i, wqe_idx, total_size = 0, byte_off;
  318. enum i40iw_status_code ret_code;
  319. bool read_fence = false;
  320. u8 wqe_size;
  321. op_info = &info->op.send;
  322. if (qp->max_sq_frag_cnt < op_info->num_sges)
  323. return I40IW_ERR_INVALID_FRAG_COUNT;
  324. for (i = 0; i < op_info->num_sges; i++)
  325. total_size += op_info->sg_list[i].len;
  326. ret_code = i40iw_fragcnt_to_wqesize_sq(op_info->num_sges, &wqe_size);
  327. if (ret_code)
  328. return ret_code;
  329. wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, total_size, info->wr_id);
  330. if (!wqe)
  331. return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
  332. read_fence |= info->read_fence;
  333. set_64bit_val(wqe, 16, 0);
  334. header = LS_64(stag_to_inv, I40IWQPSQ_REMSTAG) |
  335. LS_64(info->op_type, I40IWQPSQ_OPCODE) |
  336. LS_64((op_info->num_sges > 1 ? (op_info->num_sges - 1) : 0),
  337. I40IWQPSQ_ADDFRAGCNT) |
  338. LS_64(read_fence, I40IWQPSQ_READFENCE) |
  339. LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
  340. LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
  341. LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
  342. i40iw_set_fragment(wqe, 0, op_info->sg_list);
  343. for (i = 1, byte_off = 32; i < op_info->num_sges; i++) {
  344. i40iw_set_fragment(wqe, byte_off, &op_info->sg_list[i]);
  345. byte_off += 16;
  346. }
  347. wmb(); /* make sure WQE is populated before valid bit is set */
  348. set_64bit_val(wqe, 24, header);
  349. if (post_sq)
  350. i40iw_qp_post_wr(qp);
  351. return 0;
  352. }
  353. /**
  354. * i40iw_inline_rdma_write - inline rdma write operation
  355. * @qp: hw qp ptr
  356. * @info: post sq information
  357. * @post_sq: flag to post sq
  358. */
  359. static enum i40iw_status_code i40iw_inline_rdma_write(struct i40iw_qp_uk *qp,
  360. struct i40iw_post_sq_info *info,
  361. bool post_sq)
  362. {
  363. u64 *wqe;
  364. u8 *dest, *src;
  365. struct i40iw_inline_rdma_write *op_info;
  366. u64 *push;
  367. u64 header = 0;
  368. u32 wqe_idx;
  369. enum i40iw_status_code ret_code;
  370. bool read_fence = false;
  371. u8 wqe_size;
  372. op_info = &info->op.inline_rdma_write;
  373. if (op_info->len > I40IW_MAX_INLINE_DATA_SIZE)
  374. return I40IW_ERR_INVALID_INLINE_DATA_SIZE;
  375. ret_code = i40iw_inline_data_size_to_wqesize(op_info->len, &wqe_size);
  376. if (ret_code)
  377. return ret_code;
  378. wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, op_info->len, info->wr_id);
  379. if (!wqe)
  380. return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
  381. read_fence |= info->read_fence;
  382. set_64bit_val(wqe, 16,
  383. LS_64(op_info->rem_addr.tag_off, I40IWQPSQ_FRAG_TO));
  384. header = LS_64(op_info->rem_addr.stag, I40IWQPSQ_REMSTAG) |
  385. LS_64(I40IWQP_OP_RDMA_WRITE, I40IWQPSQ_OPCODE) |
  386. LS_64(op_info->len, I40IWQPSQ_INLINEDATALEN) |
  387. LS_64(1, I40IWQPSQ_INLINEDATAFLAG) |
  388. LS_64((qp->push_db ? 1 : 0), I40IWQPSQ_PUSHWQE) |
  389. LS_64(read_fence, I40IWQPSQ_READFENCE) |
  390. LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
  391. LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
  392. LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
  393. dest = (u8 *)wqe;
  394. src = (u8 *)(op_info->data);
  395. if (op_info->len <= 16) {
  396. memcpy(dest, src, op_info->len);
  397. } else {
  398. memcpy(dest, src, 16);
  399. src += 16;
  400. dest = (u8 *)wqe + 32;
  401. memcpy(dest, src, op_info->len - 16);
  402. }
  403. wmb(); /* make sure WQE is populated before valid bit is set */
  404. set_64bit_val(wqe, 24, header);
  405. if (qp->push_db) {
  406. push = (u64 *)((uintptr_t)qp->push_wqe + (wqe_idx & 0x3) * 0x20);
  407. memcpy(push, wqe, (op_info->len > 16) ? op_info->len + 16 : 32);
  408. i40iw_qp_ring_push_db(qp, wqe_idx);
  409. } else {
  410. if (post_sq)
  411. i40iw_qp_post_wr(qp);
  412. }
  413. return 0;
  414. }
  415. /**
  416. * i40iw_inline_send - inline send operation
  417. * @qp: hw qp ptr
  418. * @info: post sq information
  419. * @stag_to_inv: remote stag
  420. * @post_sq: flag to post sq
  421. */
  422. static enum i40iw_status_code i40iw_inline_send(struct i40iw_qp_uk *qp,
  423. struct i40iw_post_sq_info *info,
  424. u32 stag_to_inv,
  425. bool post_sq)
  426. {
  427. u64 *wqe;
  428. u8 *dest, *src;
  429. struct i40iw_post_inline_send *op_info;
  430. u64 header;
  431. u32 wqe_idx;
  432. enum i40iw_status_code ret_code;
  433. bool read_fence = false;
  434. u8 wqe_size;
  435. u64 *push;
  436. op_info = &info->op.inline_send;
  437. if (op_info->len > I40IW_MAX_INLINE_DATA_SIZE)
  438. return I40IW_ERR_INVALID_INLINE_DATA_SIZE;
  439. ret_code = i40iw_inline_data_size_to_wqesize(op_info->len, &wqe_size);
  440. if (ret_code)
  441. return ret_code;
  442. wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, op_info->len, info->wr_id);
  443. if (!wqe)
  444. return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
  445. read_fence |= info->read_fence;
  446. header = LS_64(stag_to_inv, I40IWQPSQ_REMSTAG) |
  447. LS_64(info->op_type, I40IWQPSQ_OPCODE) |
  448. LS_64(op_info->len, I40IWQPSQ_INLINEDATALEN) |
  449. LS_64(1, I40IWQPSQ_INLINEDATAFLAG) |
  450. LS_64((qp->push_db ? 1 : 0), I40IWQPSQ_PUSHWQE) |
  451. LS_64(read_fence, I40IWQPSQ_READFENCE) |
  452. LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
  453. LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
  454. LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
  455. dest = (u8 *)wqe;
  456. src = (u8 *)(op_info->data);
  457. if (op_info->len <= 16) {
  458. memcpy(dest, src, op_info->len);
  459. } else {
  460. memcpy(dest, src, 16);
  461. src += 16;
  462. dest = (u8 *)wqe + 32;
  463. memcpy(dest, src, op_info->len - 16);
  464. }
  465. wmb(); /* make sure WQE is populated before valid bit is set */
  466. set_64bit_val(wqe, 24, header);
  467. if (qp->push_db) {
  468. push = (u64 *)((uintptr_t)qp->push_wqe + (wqe_idx & 0x3) * 0x20);
  469. memcpy(push, wqe, (op_info->len > 16) ? op_info->len + 16 : 32);
  470. i40iw_qp_ring_push_db(qp, wqe_idx);
  471. } else {
  472. if (post_sq)
  473. i40iw_qp_post_wr(qp);
  474. }
  475. return 0;
  476. }
  477. /**
  478. * i40iw_stag_local_invalidate - stag invalidate operation
  479. * @qp: hw qp ptr
  480. * @info: post sq information
  481. * @post_sq: flag to post sq
  482. */
  483. static enum i40iw_status_code i40iw_stag_local_invalidate(struct i40iw_qp_uk *qp,
  484. struct i40iw_post_sq_info *info,
  485. bool post_sq)
  486. {
  487. u64 *wqe;
  488. struct i40iw_inv_local_stag *op_info;
  489. u64 header;
  490. u32 wqe_idx;
  491. bool local_fence = false;
  492. op_info = &info->op.inv_local_stag;
  493. local_fence = info->local_fence;
  494. wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, I40IW_QP_WQE_MIN_SIZE, 0, info->wr_id);
  495. if (!wqe)
  496. return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
  497. set_64bit_val(wqe, 0, 0);
  498. set_64bit_val(wqe, 8,
  499. LS_64(op_info->target_stag, I40IWQPSQ_LOCSTAG));
  500. set_64bit_val(wqe, 16, 0);
  501. header = LS_64(I40IW_OP_TYPE_INV_STAG, I40IWQPSQ_OPCODE) |
  502. LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
  503. LS_64(local_fence, I40IWQPSQ_LOCALFENCE) |
  504. LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
  505. LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
  506. wmb(); /* make sure WQE is populated before valid bit is set */
  507. set_64bit_val(wqe, 24, header);
  508. if (post_sq)
  509. i40iw_qp_post_wr(qp);
  510. return 0;
  511. }
  512. /**
  513. * i40iw_mw_bind - Memory Window bind operation
  514. * @qp: hw qp ptr
  515. * @info: post sq information
  516. * @post_sq: flag to post sq
  517. */
  518. static enum i40iw_status_code i40iw_mw_bind(struct i40iw_qp_uk *qp,
  519. struct i40iw_post_sq_info *info,
  520. bool post_sq)
  521. {
  522. u64 *wqe;
  523. struct i40iw_bind_window *op_info;
  524. u64 header;
  525. u32 wqe_idx;
  526. bool local_fence = false;
  527. op_info = &info->op.bind_window;
  528. local_fence |= info->local_fence;
  529. wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, I40IW_QP_WQE_MIN_SIZE, 0, info->wr_id);
  530. if (!wqe)
  531. return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
  532. set_64bit_val(wqe, 0, (uintptr_t)op_info->va);
  533. set_64bit_val(wqe, 8,
  534. LS_64(op_info->mr_stag, I40IWQPSQ_PARENTMRSTAG) |
  535. LS_64(op_info->mw_stag, I40IWQPSQ_MWSTAG));
  536. set_64bit_val(wqe, 16, op_info->bind_length);
  537. header = LS_64(I40IW_OP_TYPE_BIND_MW, I40IWQPSQ_OPCODE) |
  538. LS_64(((op_info->enable_reads << 2) |
  539. (op_info->enable_writes << 3)),
  540. I40IWQPSQ_STAGRIGHTS) |
  541. LS_64((op_info->addressing_type == I40IW_ADDR_TYPE_VA_BASED ? 1 : 0),
  542. I40IWQPSQ_VABASEDTO) |
  543. LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
  544. LS_64(local_fence, I40IWQPSQ_LOCALFENCE) |
  545. LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
  546. LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
  547. wmb(); /* make sure WQE is populated before valid bit is set */
  548. set_64bit_val(wqe, 24, header);
  549. if (post_sq)
  550. i40iw_qp_post_wr(qp);
  551. return 0;
  552. }
  553. /**
  554. * i40iw_post_receive - post receive wqe
  555. * @qp: hw qp ptr
  556. * @info: post rq information
  557. */
  558. static enum i40iw_status_code i40iw_post_receive(struct i40iw_qp_uk *qp,
  559. struct i40iw_post_rq_info *info)
  560. {
  561. u64 *wqe;
  562. u64 header;
  563. u32 total_size = 0, wqe_idx, i, byte_off;
  564. if (qp->max_rq_frag_cnt < info->num_sges)
  565. return I40IW_ERR_INVALID_FRAG_COUNT;
  566. for (i = 0; i < info->num_sges; i++)
  567. total_size += info->sg_list[i].len;
  568. wqe = i40iw_qp_get_next_recv_wqe(qp, &wqe_idx);
  569. if (!wqe)
  570. return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
  571. qp->rq_wrid_array[wqe_idx] = info->wr_id;
  572. set_64bit_val(wqe, 16, 0);
  573. header = LS_64((info->num_sges > 1 ? (info->num_sges - 1) : 0),
  574. I40IWQPSQ_ADDFRAGCNT) |
  575. LS_64(qp->rwqe_polarity, I40IWQPSQ_VALID);
  576. i40iw_set_fragment(wqe, 0, info->sg_list);
  577. for (i = 1, byte_off = 32; i < info->num_sges; i++) {
  578. i40iw_set_fragment(wqe, byte_off, &info->sg_list[i]);
  579. byte_off += 16;
  580. }
  581. wmb(); /* make sure WQE is populated before valid bit is set */
  582. set_64bit_val(wqe, 24, header);
  583. return 0;
  584. }
  585. /**
  586. * i40iw_cq_request_notification - cq notification request (door bell)
  587. * @cq: hw cq
  588. * @cq_notify: notification type
  589. */
  590. static void i40iw_cq_request_notification(struct i40iw_cq_uk *cq,
  591. enum i40iw_completion_notify cq_notify)
  592. {
  593. u64 temp_val;
  594. u16 sw_cq_sel;
  595. u8 arm_next_se = 0;
  596. u8 arm_next = 0;
  597. u8 arm_seq_num;
  598. get_64bit_val(cq->shadow_area, 32, &temp_val);
  599. arm_seq_num = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_SEQ_NUM);
  600. arm_seq_num++;
  601. sw_cq_sel = (u16)RS_64(temp_val, I40IW_CQ_DBSA_SW_CQ_SELECT);
  602. arm_next_se = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_NEXT_SE);
  603. arm_next_se |= 1;
  604. if (cq_notify == IW_CQ_COMPL_EVENT)
  605. arm_next = 1;
  606. temp_val = LS_64(arm_seq_num, I40IW_CQ_DBSA_ARM_SEQ_NUM) |
  607. LS_64(sw_cq_sel, I40IW_CQ_DBSA_SW_CQ_SELECT) |
  608. LS_64(arm_next_se, I40IW_CQ_DBSA_ARM_NEXT_SE) |
  609. LS_64(arm_next, I40IW_CQ_DBSA_ARM_NEXT);
  610. set_64bit_val(cq->shadow_area, 32, temp_val);
  611. wmb(); /* make sure WQE is populated before valid bit is set */
  612. writel(cq->cq_id, cq->cqe_alloc_reg);
  613. }
  614. /**
  615. * i40iw_cq_post_entries - update tail in shadow memory
  616. * @cq: hw cq
  617. * @count: # of entries processed
  618. */
  619. static enum i40iw_status_code i40iw_cq_post_entries(struct i40iw_cq_uk *cq,
  620. u8 count)
  621. {
  622. I40IW_RING_MOVE_TAIL_BY_COUNT(cq->cq_ring, count);
  623. set_64bit_val(cq->shadow_area, 0,
  624. I40IW_RING_GETCURRENT_HEAD(cq->cq_ring));
  625. return 0;
  626. }
  627. /**
  628. * i40iw_cq_poll_completion - get cq completion info
  629. * @cq: hw cq
  630. * @info: cq poll information returned
  631. * @post_cq: update cq tail
  632. */
  633. static enum i40iw_status_code i40iw_cq_poll_completion(struct i40iw_cq_uk *cq,
  634. struct i40iw_cq_poll_info *info)
  635. {
  636. u64 comp_ctx, qword0, qword2, qword3, wqe_qword;
  637. u64 *cqe, *sw_wqe;
  638. struct i40iw_qp_uk *qp;
  639. struct i40iw_ring *pring = NULL;
  640. u32 wqe_idx, q_type, array_idx = 0;
  641. enum i40iw_status_code ret_code = 0;
  642. bool move_cq_head = true;
  643. u8 polarity;
  644. u8 addl_wqes = 0;
  645. if (cq->avoid_mem_cflct)
  646. cqe = (u64 *)I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(cq);
  647. else
  648. cqe = (u64 *)I40IW_GET_CURRENT_CQ_ELEMENT(cq);
  649. get_64bit_val(cqe, 24, &qword3);
  650. polarity = (u8)RS_64(qword3, I40IW_CQ_VALID);
  651. if (polarity != cq->polarity)
  652. return I40IW_ERR_QUEUE_EMPTY;
  653. q_type = (u8)RS_64(qword3, I40IW_CQ_SQ);
  654. info->error = (bool)RS_64(qword3, I40IW_CQ_ERROR);
  655. info->push_dropped = (bool)RS_64(qword3, I40IWCQ_PSHDROP);
  656. if (info->error) {
  657. info->comp_status = I40IW_COMPL_STATUS_FLUSHED;
  658. info->major_err = (bool)RS_64(qword3, I40IW_CQ_MAJERR);
  659. info->minor_err = (bool)RS_64(qword3, I40IW_CQ_MINERR);
  660. } else {
  661. info->comp_status = I40IW_COMPL_STATUS_SUCCESS;
  662. }
  663. get_64bit_val(cqe, 0, &qword0);
  664. get_64bit_val(cqe, 16, &qword2);
  665. info->tcp_seq_num = (u32)RS_64(qword0, I40IWCQ_TCPSEQNUM);
  666. info->qp_id = (u32)RS_64(qword2, I40IWCQ_QPID);
  667. get_64bit_val(cqe, 8, &comp_ctx);
  668. info->solicited_event = (bool)RS_64(qword3, I40IWCQ_SOEVENT);
  669. info->is_srq = (bool)RS_64(qword3, I40IWCQ_SRQ);
  670. qp = (struct i40iw_qp_uk *)(unsigned long)comp_ctx;
  671. if (!qp) {
  672. ret_code = I40IW_ERR_QUEUE_DESTROYED;
  673. goto exit;
  674. }
  675. wqe_idx = (u32)RS_64(qword3, I40IW_CQ_WQEIDX);
  676. info->qp_handle = (i40iw_qp_handle)(unsigned long)qp;
  677. if (q_type == I40IW_CQE_QTYPE_RQ) {
  678. array_idx = (wqe_idx * 4) / qp->rq_wqe_size_multiplier;
  679. if (info->comp_status == I40IW_COMPL_STATUS_FLUSHED) {
  680. info->wr_id = qp->rq_wrid_array[qp->rq_ring.tail];
  681. array_idx = qp->rq_ring.tail;
  682. } else {
  683. info->wr_id = qp->rq_wrid_array[array_idx];
  684. }
  685. info->op_type = I40IW_OP_TYPE_REC;
  686. if (qword3 & I40IWCQ_STAG_MASK) {
  687. info->stag_invalid_set = true;
  688. info->inv_stag = (u32)RS_64(qword2, I40IWCQ_INVSTAG);
  689. } else {
  690. info->stag_invalid_set = false;
  691. }
  692. info->bytes_xfered = (u32)RS_64(qword0, I40IWCQ_PAYLDLEN);
  693. I40IW_RING_SET_TAIL(qp->rq_ring, array_idx + 1);
  694. pring = &qp->rq_ring;
  695. } else {
  696. if (qp->first_sq_wq) {
  697. qp->first_sq_wq = false;
  698. if (!wqe_idx && (qp->sq_ring.head == qp->sq_ring.tail)) {
  699. I40IW_RING_MOVE_HEAD_NOCHECK(cq->cq_ring);
  700. I40IW_RING_MOVE_TAIL(cq->cq_ring);
  701. set_64bit_val(cq->shadow_area, 0,
  702. I40IW_RING_GETCURRENT_HEAD(cq->cq_ring));
  703. memset(info, 0, sizeof(struct i40iw_cq_poll_info));
  704. return i40iw_cq_poll_completion(cq, info);
  705. }
  706. }
  707. if (info->comp_status != I40IW_COMPL_STATUS_FLUSHED) {
  708. info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid;
  709. info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len;
  710. info->op_type = (u8)RS_64(qword3, I40IWCQ_OP);
  711. sw_wqe = qp->sq_base[wqe_idx].elem;
  712. get_64bit_val(sw_wqe, 24, &wqe_qword);
  713. addl_wqes = qp->sq_wrtrk_array[wqe_idx].wqe_size / I40IW_QP_WQE_MIN_SIZE;
  714. I40IW_RING_SET_TAIL(qp->sq_ring, (wqe_idx + addl_wqes));
  715. } else {
  716. do {
  717. u8 op_type;
  718. u32 tail;
  719. tail = qp->sq_ring.tail;
  720. sw_wqe = qp->sq_base[tail].elem;
  721. get_64bit_val(sw_wqe, 24, &wqe_qword);
  722. op_type = (u8)RS_64(wqe_qword, I40IWQPSQ_OPCODE);
  723. info->op_type = op_type;
  724. addl_wqes = qp->sq_wrtrk_array[tail].wqe_size / I40IW_QP_WQE_MIN_SIZE;
  725. I40IW_RING_SET_TAIL(qp->sq_ring, (tail + addl_wqes));
  726. if (op_type != I40IWQP_OP_NOP) {
  727. info->wr_id = qp->sq_wrtrk_array[tail].wrid;
  728. info->bytes_xfered = qp->sq_wrtrk_array[tail].wr_len;
  729. break;
  730. }
  731. } while (1);
  732. }
  733. pring = &qp->sq_ring;
  734. }
  735. ret_code = 0;
  736. exit:
  737. if (!ret_code &&
  738. (info->comp_status == I40IW_COMPL_STATUS_FLUSHED))
  739. if (pring && (I40IW_RING_MORE_WORK(*pring)))
  740. move_cq_head = false;
  741. if (move_cq_head) {
  742. I40IW_RING_MOVE_HEAD_NOCHECK(cq->cq_ring);
  743. if (I40IW_RING_GETCURRENT_HEAD(cq->cq_ring) == 0)
  744. cq->polarity ^= 1;
  745. I40IW_RING_MOVE_TAIL(cq->cq_ring);
  746. set_64bit_val(cq->shadow_area, 0,
  747. I40IW_RING_GETCURRENT_HEAD(cq->cq_ring));
  748. } else {
  749. if (info->is_srq)
  750. return ret_code;
  751. qword3 &= ~I40IW_CQ_WQEIDX_MASK;
  752. qword3 |= LS_64(pring->tail, I40IW_CQ_WQEIDX);
  753. set_64bit_val(cqe, 24, qword3);
  754. }
  755. return ret_code;
  756. }
  757. /**
  758. * i40iw_get_wqe_shift - get shift count for maximum wqe size
  759. * @sge: Maximum Scatter Gather Elements wqe
  760. * @inline_data: Maximum inline data size
  761. * @shift: Returns the shift needed based on sge
  762. *
  763. * Shift can be used to left shift the wqe size based on number of SGEs and inlind data size.
  764. * For 1 SGE or inline data <= 16, shift = 0 (wqe size of 32 bytes).
  765. * For 2 or 3 SGEs or inline data <= 48, shift = 1 (wqe size of 64 bytes).
  766. * Shift of 2 otherwise (wqe size of 128 bytes).
  767. */
  768. void i40iw_get_wqe_shift(u32 sge, u32 inline_data, u8 *shift)
  769. {
  770. *shift = 0;
  771. if (sge > 1 || inline_data > 16)
  772. *shift = (sge < 4 && inline_data <= 48) ? 1 : 2;
  773. }
  774. /*
  775. * i40iw_get_sqdepth - get SQ depth (quantas)
  776. * @sq_size: SQ size
  777. * @shift: shift which determines size of WQE
  778. * @sqdepth: depth of SQ
  779. *
  780. */
  781. enum i40iw_status_code i40iw_get_sqdepth(u32 sq_size, u8 shift, u32 *sqdepth)
  782. {
  783. *sqdepth = roundup_pow_of_two((sq_size << shift) + I40IW_SQ_RSVD);
  784. if (*sqdepth < (I40IW_QP_SW_MIN_WQSIZE << shift))
  785. *sqdepth = I40IW_QP_SW_MIN_WQSIZE << shift;
  786. else if (*sqdepth > I40IW_QP_SW_MAX_SQ_QUANTAS)
  787. return I40IW_ERR_INVALID_SIZE;
  788. return 0;
  789. }
  790. /*
  791. * i40iw_get_rq_depth - get RQ depth (quantas)
  792. * @rq_size: RQ size
  793. * @shift: shift which determines size of WQE
  794. * @rqdepth: depth of RQ
  795. *
  796. */
  797. enum i40iw_status_code i40iw_get_rqdepth(u32 rq_size, u8 shift, u32 *rqdepth)
  798. {
  799. *rqdepth = roundup_pow_of_two((rq_size << shift) + I40IW_RQ_RSVD);
  800. if (*rqdepth < (I40IW_QP_SW_MIN_WQSIZE << shift))
  801. *rqdepth = I40IW_QP_SW_MIN_WQSIZE << shift;
  802. else if (*rqdepth > I40IW_QP_SW_MAX_RQ_QUANTAS)
  803. return I40IW_ERR_INVALID_SIZE;
  804. return 0;
  805. }
  806. static const struct i40iw_qp_uk_ops iw_qp_uk_ops = {
  807. .iw_qp_post_wr = i40iw_qp_post_wr,
  808. .iw_qp_ring_push_db = i40iw_qp_ring_push_db,
  809. .iw_rdma_write = i40iw_rdma_write,
  810. .iw_rdma_read = i40iw_rdma_read,
  811. .iw_send = i40iw_send,
  812. .iw_inline_rdma_write = i40iw_inline_rdma_write,
  813. .iw_inline_send = i40iw_inline_send,
  814. .iw_stag_local_invalidate = i40iw_stag_local_invalidate,
  815. .iw_mw_bind = i40iw_mw_bind,
  816. .iw_post_receive = i40iw_post_receive,
  817. .iw_post_nop = i40iw_nop
  818. };
  819. static const struct i40iw_cq_ops iw_cq_ops = {
  820. .iw_cq_request_notification = i40iw_cq_request_notification,
  821. .iw_cq_poll_completion = i40iw_cq_poll_completion,
  822. .iw_cq_post_entries = i40iw_cq_post_entries,
  823. .iw_cq_clean = i40iw_clean_cq
  824. };
  825. static const struct i40iw_device_uk_ops iw_device_uk_ops = {
  826. .iwarp_cq_uk_init = i40iw_cq_uk_init,
  827. .iwarp_qp_uk_init = i40iw_qp_uk_init,
  828. };
  829. /**
  830. * i40iw_qp_uk_init - initialize shared qp
  831. * @qp: hw qp (user and kernel)
  832. * @info: qp initialization info
  833. *
  834. * initializes the vars used in both user and kernel mode.
  835. * size of the wqe depends on numbers of max. fragements
  836. * allowed. Then size of wqe * the number of wqes should be the
  837. * amount of memory allocated for sq and rq. If srq is used,
  838. * then rq_base will point to one rq wqe only (not the whole
  839. * array of wqes)
  840. */
  841. enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
  842. struct i40iw_qp_uk_init_info *info)
  843. {
  844. enum i40iw_status_code ret_code = 0;
  845. u32 sq_ring_size;
  846. u8 sqshift, rqshift;
  847. if (info->max_sq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT)
  848. return I40IW_ERR_INVALID_FRAG_COUNT;
  849. if (info->max_rq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT)
  850. return I40IW_ERR_INVALID_FRAG_COUNT;
  851. i40iw_get_wqe_shift(info->max_sq_frag_cnt, info->max_inline_data, &sqshift);
  852. qp->sq_base = info->sq;
  853. qp->rq_base = info->rq;
  854. qp->shadow_area = info->shadow_area;
  855. qp->sq_wrtrk_array = info->sq_wrtrk_array;
  856. qp->rq_wrid_array = info->rq_wrid_array;
  857. qp->wqe_alloc_reg = info->wqe_alloc_reg;
  858. qp->qp_id = info->qp_id;
  859. qp->sq_size = info->sq_size;
  860. qp->push_db = info->push_db;
  861. qp->push_wqe = info->push_wqe;
  862. qp->max_sq_frag_cnt = info->max_sq_frag_cnt;
  863. sq_ring_size = qp->sq_size << sqshift;
  864. I40IW_RING_INIT(qp->sq_ring, sq_ring_size);
  865. I40IW_RING_INIT(qp->initial_ring, sq_ring_size);
  866. I40IW_RING_MOVE_HEAD(qp->sq_ring, ret_code);
  867. I40IW_RING_MOVE_TAIL(qp->sq_ring);
  868. I40IW_RING_MOVE_HEAD(qp->initial_ring, ret_code);
  869. qp->swqe_polarity = 1;
  870. qp->first_sq_wq = true;
  871. qp->swqe_polarity_deferred = 1;
  872. qp->rwqe_polarity = 0;
  873. if (!qp->use_srq) {
  874. qp->rq_size = info->rq_size;
  875. qp->max_rq_frag_cnt = info->max_rq_frag_cnt;
  876. I40IW_RING_INIT(qp->rq_ring, qp->rq_size);
  877. switch (info->abi_ver) {
  878. case 4:
  879. i40iw_get_wqe_shift(info->max_rq_frag_cnt, 0, &rqshift);
  880. break;
  881. case 5: /* fallthrough until next ABI version */
  882. default:
  883. rqshift = I40IW_MAX_RQ_WQE_SHIFT;
  884. break;
  885. }
  886. qp->rq_wqe_size = rqshift;
  887. qp->rq_wqe_size_multiplier = 4 << rqshift;
  888. }
  889. qp->ops = iw_qp_uk_ops;
  890. return ret_code;
  891. }
  892. /**
  893. * i40iw_cq_uk_init - initialize shared cq (user and kernel)
  894. * @cq: hw cq
  895. * @info: hw cq initialization info
  896. */
  897. enum i40iw_status_code i40iw_cq_uk_init(struct i40iw_cq_uk *cq,
  898. struct i40iw_cq_uk_init_info *info)
  899. {
  900. if ((info->cq_size < I40IW_MIN_CQ_SIZE) ||
  901. (info->cq_size > I40IW_MAX_CQ_SIZE))
  902. return I40IW_ERR_INVALID_SIZE;
  903. cq->cq_base = (struct i40iw_cqe *)info->cq_base;
  904. cq->cq_id = info->cq_id;
  905. cq->cq_size = info->cq_size;
  906. cq->cqe_alloc_reg = info->cqe_alloc_reg;
  907. cq->shadow_area = info->shadow_area;
  908. cq->avoid_mem_cflct = info->avoid_mem_cflct;
  909. I40IW_RING_INIT(cq->cq_ring, cq->cq_size);
  910. cq->polarity = 1;
  911. cq->ops = iw_cq_ops;
  912. return 0;
  913. }
  914. /**
  915. * i40iw_device_init_uk - setup routines for iwarp shared device
  916. * @dev: iwarp shared (user and kernel)
  917. */
  918. void i40iw_device_init_uk(struct i40iw_dev_uk *dev)
  919. {
  920. dev->ops_uk = iw_device_uk_ops;
  921. }
  922. /**
  923. * i40iw_clean_cq - clean cq entries
  924. * @ queue completion context
  925. * @cq: cq to clean
  926. */
  927. void i40iw_clean_cq(void *queue, struct i40iw_cq_uk *cq)
  928. {
  929. u64 *cqe;
  930. u64 qword3, comp_ctx;
  931. u32 cq_head;
  932. u8 polarity, temp;
  933. cq_head = cq->cq_ring.head;
  934. temp = cq->polarity;
  935. do {
  936. if (cq->avoid_mem_cflct)
  937. cqe = (u64 *)&(((struct i40iw_extended_cqe *)cq->cq_base)[cq_head]);
  938. else
  939. cqe = (u64 *)&cq->cq_base[cq_head];
  940. get_64bit_val(cqe, 24, &qword3);
  941. polarity = (u8)RS_64(qword3, I40IW_CQ_VALID);
  942. if (polarity != temp)
  943. break;
  944. get_64bit_val(cqe, 8, &comp_ctx);
  945. if ((void *)(unsigned long)comp_ctx == queue)
  946. set_64bit_val(cqe, 8, 0);
  947. cq_head = (cq_head + 1) % cq->cq_ring.size;
  948. if (!cq_head)
  949. temp ^= 1;
  950. } while (true);
  951. }
  952. /**
  953. * i40iw_nop - send a nop
  954. * @qp: hw qp ptr
  955. * @wr_id: work request id
  956. * @signaled: flag if signaled for completion
  957. * @post_sq: flag to post sq
  958. */
  959. enum i40iw_status_code i40iw_nop(struct i40iw_qp_uk *qp,
  960. u64 wr_id,
  961. bool signaled,
  962. bool post_sq)
  963. {
  964. u64 header, *wqe;
  965. u32 wqe_idx;
  966. wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, I40IW_QP_WQE_MIN_SIZE, 0, wr_id);
  967. if (!wqe)
  968. return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
  969. set_64bit_val(wqe, 0, 0);
  970. set_64bit_val(wqe, 8, 0);
  971. set_64bit_val(wqe, 16, 0);
  972. header = LS_64(I40IWQP_OP_NOP, I40IWQPSQ_OPCODE) |
  973. LS_64(signaled, I40IWQPSQ_SIGCOMPL) |
  974. LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
  975. wmb(); /* make sure WQE is populated before valid bit is set */
  976. set_64bit_val(wqe, 24, header);
  977. if (post_sq)
  978. i40iw_qp_post_wr(qp);
  979. return 0;
  980. }
  981. /**
  982. * i40iw_fragcnt_to_wqesize_sq - calculate wqe size based on fragment count for SQ
  983. * @frag_cnt: number of fragments
  984. * @wqe_size: size of sq wqe returned
  985. */
  986. enum i40iw_status_code i40iw_fragcnt_to_wqesize_sq(u32 frag_cnt, u8 *wqe_size)
  987. {
  988. switch (frag_cnt) {
  989. case 0:
  990. case 1:
  991. *wqe_size = I40IW_QP_WQE_MIN_SIZE;
  992. break;
  993. case 2:
  994. case 3:
  995. *wqe_size = 64;
  996. break;
  997. case 4:
  998. case 5:
  999. *wqe_size = 96;
  1000. break;
  1001. case 6:
  1002. case 7:
  1003. *wqe_size = 128;
  1004. break;
  1005. default:
  1006. return I40IW_ERR_INVALID_FRAG_COUNT;
  1007. }
  1008. return 0;
  1009. }
  1010. /**
  1011. * i40iw_fragcnt_to_wqesize_rq - calculate wqe size based on fragment count for RQ
  1012. * @frag_cnt: number of fragments
  1013. * @wqe_size: size of rq wqe returned
  1014. */
  1015. enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u32 frag_cnt, u8 *wqe_size)
  1016. {
  1017. switch (frag_cnt) {
  1018. case 0:
  1019. case 1:
  1020. *wqe_size = 32;
  1021. break;
  1022. case 2:
  1023. case 3:
  1024. *wqe_size = 64;
  1025. break;
  1026. case 4:
  1027. case 5:
  1028. case 6:
  1029. case 7:
  1030. *wqe_size = 128;
  1031. break;
  1032. default:
  1033. return I40IW_ERR_INVALID_FRAG_COUNT;
  1034. }
  1035. return 0;
  1036. }
  1037. /**
  1038. * i40iw_inline_data_size_to_wqesize - based on inline data, wqe size
  1039. * @data_size: data size for inline
  1040. * @wqe_size: size of sq wqe returned
  1041. */
  1042. enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size,
  1043. u8 *wqe_size)
  1044. {
  1045. if (data_size > I40IW_MAX_INLINE_DATA_SIZE)
  1046. return I40IW_ERR_INVALID_INLINE_DATA_SIZE;
  1047. if (data_size <= 16)
  1048. *wqe_size = I40IW_QP_WQE_MIN_SIZE;
  1049. else
  1050. *wqe_size = 64;
  1051. return 0;
  1052. }