i40iw_verbs.c 78 KB

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  1. /*******************************************************************************
  2. *
  3. * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenFabrics.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. *
  33. *******************************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/moduleparam.h>
  36. #include <linux/random.h>
  37. #include <linux/highmem.h>
  38. #include <linux/time.h>
  39. #include <linux/hugetlb.h>
  40. #include <linux/irq.h>
  41. #include <asm/byteorder.h>
  42. #include <net/ip.h>
  43. #include <rdma/ib_verbs.h>
  44. #include <rdma/iw_cm.h>
  45. #include <rdma/ib_user_verbs.h>
  46. #include <rdma/ib_umem.h>
  47. #include "i40iw.h"
  48. /**
  49. * i40iw_query_device - get device attributes
  50. * @ibdev: device pointer from stack
  51. * @props: returning device attributes
  52. * @udata: user data
  53. */
  54. static int i40iw_query_device(struct ib_device *ibdev,
  55. struct ib_device_attr *props,
  56. struct ib_udata *udata)
  57. {
  58. struct i40iw_device *iwdev = to_iwdev(ibdev);
  59. if (udata->inlen || udata->outlen)
  60. return -EINVAL;
  61. memset(props, 0, sizeof(*props));
  62. ether_addr_copy((u8 *)&props->sys_image_guid, iwdev->netdev->dev_addr);
  63. props->fw_ver = I40IW_FW_VERSION;
  64. props->device_cap_flags = iwdev->device_cap_flags;
  65. props->vendor_id = iwdev->ldev->pcidev->vendor;
  66. props->vendor_part_id = iwdev->ldev->pcidev->device;
  67. props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
  68. props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
  69. props->max_qp = iwdev->max_qp - iwdev->used_qps;
  70. props->max_qp_wr = I40IW_MAX_QP_WRS;
  71. props->max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  72. props->max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  73. props->max_cq = iwdev->max_cq - iwdev->used_cqs;
  74. props->max_cqe = iwdev->max_cqe;
  75. props->max_mr = iwdev->max_mr - iwdev->used_mrs;
  76. props->max_pd = iwdev->max_pd - iwdev->used_pds;
  77. props->max_sge_rd = I40IW_MAX_SGE_RD;
  78. props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
  79. props->max_qp_init_rd_atom = props->max_qp_rd_atom;
  80. props->atomic_cap = IB_ATOMIC_NONE;
  81. props->max_map_per_fmr = 1;
  82. props->max_fast_reg_page_list_len = I40IW_MAX_PAGES_PER_FMR;
  83. return 0;
  84. }
  85. /**
  86. * i40iw_query_port - get port attrubutes
  87. * @ibdev: device pointer from stack
  88. * @port: port number for query
  89. * @props: returning device attributes
  90. */
  91. static int i40iw_query_port(struct ib_device *ibdev,
  92. u8 port,
  93. struct ib_port_attr *props)
  94. {
  95. struct i40iw_device *iwdev = to_iwdev(ibdev);
  96. struct net_device *netdev = iwdev->netdev;
  97. /* props being zeroed by the caller, avoid zeroing it here */
  98. props->max_mtu = IB_MTU_4096;
  99. props->active_mtu = ib_mtu_int_to_enum(netdev->mtu);
  100. props->lid = 1;
  101. if (netif_carrier_ok(iwdev->netdev))
  102. props->state = IB_PORT_ACTIVE;
  103. else
  104. props->state = IB_PORT_DOWN;
  105. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  106. IB_PORT_VENDOR_CLASS_SUP | IB_PORT_BOOT_MGMT_SUP;
  107. props->gid_tbl_len = 1;
  108. props->pkey_tbl_len = 1;
  109. props->active_width = IB_WIDTH_4X;
  110. props->active_speed = 1;
  111. props->max_msg_sz = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
  112. return 0;
  113. }
  114. /**
  115. * i40iw_alloc_ucontext - Allocate the user context data structure
  116. * @ibdev: device pointer from stack
  117. * @udata: user data
  118. *
  119. * This keeps track of all objects associated with a particular
  120. * user-mode client.
  121. */
  122. static struct ib_ucontext *i40iw_alloc_ucontext(struct ib_device *ibdev,
  123. struct ib_udata *udata)
  124. {
  125. struct i40iw_device *iwdev = to_iwdev(ibdev);
  126. struct i40iw_alloc_ucontext_req req;
  127. struct i40iw_alloc_ucontext_resp uresp;
  128. struct i40iw_ucontext *ucontext;
  129. if (ib_copy_from_udata(&req, udata, sizeof(req)))
  130. return ERR_PTR(-EINVAL);
  131. if (req.userspace_ver < 4 || req.userspace_ver > I40IW_ABI_VER) {
  132. i40iw_pr_err("Unsupported provider library version %u.\n", req.userspace_ver);
  133. return ERR_PTR(-EINVAL);
  134. }
  135. memset(&uresp, 0, sizeof(uresp));
  136. uresp.max_qps = iwdev->max_qp;
  137. uresp.max_pds = iwdev->max_pd;
  138. uresp.wq_size = iwdev->max_qp_wr * 2;
  139. uresp.kernel_ver = req.userspace_ver;
  140. ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL);
  141. if (!ucontext)
  142. return ERR_PTR(-ENOMEM);
  143. ucontext->iwdev = iwdev;
  144. ucontext->abi_ver = req.userspace_ver;
  145. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  146. kfree(ucontext);
  147. return ERR_PTR(-EFAULT);
  148. }
  149. INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
  150. spin_lock_init(&ucontext->cq_reg_mem_list_lock);
  151. INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
  152. spin_lock_init(&ucontext->qp_reg_mem_list_lock);
  153. return &ucontext->ibucontext;
  154. }
  155. /**
  156. * i40iw_dealloc_ucontext - deallocate the user context data structure
  157. * @context: user context created during alloc
  158. */
  159. static int i40iw_dealloc_ucontext(struct ib_ucontext *context)
  160. {
  161. struct i40iw_ucontext *ucontext = to_ucontext(context);
  162. unsigned long flags;
  163. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  164. if (!list_empty(&ucontext->cq_reg_mem_list)) {
  165. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  166. return -EBUSY;
  167. }
  168. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  169. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  170. if (!list_empty(&ucontext->qp_reg_mem_list)) {
  171. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  172. return -EBUSY;
  173. }
  174. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  175. kfree(ucontext);
  176. return 0;
  177. }
  178. /**
  179. * i40iw_mmap - user memory map
  180. * @context: context created during alloc
  181. * @vma: kernel info for user memory map
  182. */
  183. static int i40iw_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  184. {
  185. struct i40iw_ucontext *ucontext = to_ucontext(context);
  186. u64 dbaddr;
  187. if (vma->vm_pgoff || vma->vm_end - vma->vm_start != PAGE_SIZE)
  188. return -EINVAL;
  189. dbaddr = I40IW_DB_ADDR_OFFSET + pci_resource_start(ucontext->iwdev->ldev->pcidev, 0);
  190. if (io_remap_pfn_range(vma, vma->vm_start, dbaddr >> PAGE_SHIFT, PAGE_SIZE,
  191. pgprot_noncached(vma->vm_page_prot)))
  192. return -EAGAIN;
  193. return 0;
  194. }
  195. /**
  196. * i40iw_alloc_push_page - allocate a push page for qp
  197. * @iwdev: iwarp device
  198. * @qp: hardware control qp
  199. */
  200. static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  201. {
  202. struct i40iw_cqp_request *cqp_request;
  203. struct cqp_commands_info *cqp_info;
  204. enum i40iw_status_code status;
  205. if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX)
  206. return;
  207. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  208. if (!cqp_request)
  209. return;
  210. atomic_inc(&cqp_request->refcount);
  211. cqp_info = &cqp_request->info;
  212. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  213. cqp_info->post_sq = 1;
  214. cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
  215. cqp_info->in.u.manage_push_page.info.free_page = 0;
  216. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  217. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  218. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  219. if (!status)
  220. qp->push_idx = cqp_request->compl_info.op_ret_val;
  221. else
  222. i40iw_pr_err("CQP-OP Push page fail");
  223. i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
  224. }
  225. /**
  226. * i40iw_dealloc_push_page - free a push page for qp
  227. * @iwdev: iwarp device
  228. * @qp: hardware control qp
  229. */
  230. static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp *qp)
  231. {
  232. struct i40iw_cqp_request *cqp_request;
  233. struct cqp_commands_info *cqp_info;
  234. enum i40iw_status_code status;
  235. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX)
  236. return;
  237. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
  238. if (!cqp_request)
  239. return;
  240. cqp_info = &cqp_request->info;
  241. cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
  242. cqp_info->post_sq = 1;
  243. cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
  244. cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
  245. cqp_info->in.u.manage_push_page.info.free_page = 1;
  246. cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
  247. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  248. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  249. if (!status)
  250. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  251. else
  252. i40iw_pr_err("CQP-OP Push page fail");
  253. }
  254. /**
  255. * i40iw_alloc_pd - allocate protection domain
  256. * @ibdev: device pointer from stack
  257. * @context: user context created during alloc
  258. * @udata: user data
  259. */
  260. static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev,
  261. struct ib_ucontext *context,
  262. struct ib_udata *udata)
  263. {
  264. struct i40iw_pd *iwpd;
  265. struct i40iw_device *iwdev = to_iwdev(ibdev);
  266. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  267. struct i40iw_alloc_pd_resp uresp;
  268. struct i40iw_sc_pd *sc_pd;
  269. struct i40iw_ucontext *ucontext;
  270. u32 pd_id = 0;
  271. int err;
  272. if (iwdev->closing)
  273. return ERR_PTR(-ENODEV);
  274. err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
  275. iwdev->max_pd, &pd_id, &iwdev->next_pd);
  276. if (err) {
  277. i40iw_pr_err("alloc resource failed\n");
  278. return ERR_PTR(err);
  279. }
  280. iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL);
  281. if (!iwpd) {
  282. err = -ENOMEM;
  283. goto free_res;
  284. }
  285. sc_pd = &iwpd->sc_pd;
  286. if (context) {
  287. ucontext = to_ucontext(context);
  288. dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, ucontext->abi_ver);
  289. memset(&uresp, 0, sizeof(uresp));
  290. uresp.pd_id = pd_id;
  291. if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
  292. err = -EFAULT;
  293. goto error;
  294. }
  295. } else {
  296. dev->iw_pd_ops->pd_init(dev, sc_pd, pd_id, -1);
  297. }
  298. i40iw_add_pdusecount(iwpd);
  299. return &iwpd->ibpd;
  300. error:
  301. kfree(iwpd);
  302. free_res:
  303. i40iw_free_resource(iwdev, iwdev->allocated_pds, pd_id);
  304. return ERR_PTR(err);
  305. }
  306. /**
  307. * i40iw_dealloc_pd - deallocate pd
  308. * @ibpd: ptr of pd to be deallocated
  309. */
  310. static int i40iw_dealloc_pd(struct ib_pd *ibpd)
  311. {
  312. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  313. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  314. i40iw_rem_pdusecount(iwpd, iwdev);
  315. return 0;
  316. }
  317. /**
  318. * i40iw_get_pbl - Retrieve pbl from a list given a virtual
  319. * address
  320. * @va: user virtual address
  321. * @pbl_list: pbl list to search in (QP's or CQ's)
  322. */
  323. static struct i40iw_pbl *i40iw_get_pbl(unsigned long va,
  324. struct list_head *pbl_list)
  325. {
  326. struct i40iw_pbl *iwpbl;
  327. list_for_each_entry(iwpbl, pbl_list, list) {
  328. if (iwpbl->user_base == va) {
  329. iwpbl->on_list = false;
  330. list_del(&iwpbl->list);
  331. return iwpbl;
  332. }
  333. }
  334. return NULL;
  335. }
  336. /**
  337. * i40iw_free_qp_resources - free up memory resources for qp
  338. * @iwdev: iwarp device
  339. * @iwqp: qp ptr (user or kernel)
  340. * @qp_num: qp number assigned
  341. */
  342. void i40iw_free_qp_resources(struct i40iw_device *iwdev,
  343. struct i40iw_qp *iwqp,
  344. u32 qp_num)
  345. {
  346. struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
  347. i40iw_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp);
  348. i40iw_dealloc_push_page(iwdev, &iwqp->sc_qp);
  349. if (qp_num)
  350. i40iw_free_resource(iwdev, iwdev->allocated_qps, qp_num);
  351. if (iwpbl->pbl_allocated)
  352. i40iw_free_pble(iwdev->pble_rsrc, &iwpbl->pble_alloc);
  353. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->q2_ctx_mem);
  354. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwqp->kqp.dma_mem);
  355. kfree(iwqp->kqp.wrid_mem);
  356. iwqp->kqp.wrid_mem = NULL;
  357. kfree(iwqp->allocated_buffer);
  358. }
  359. /**
  360. * i40iw_clean_cqes - clean cq entries for qp
  361. * @iwqp: qp ptr (user or kernel)
  362. * @iwcq: cq ptr
  363. */
  364. static void i40iw_clean_cqes(struct i40iw_qp *iwqp, struct i40iw_cq *iwcq)
  365. {
  366. struct i40iw_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
  367. ukcq->ops.iw_cq_clean(&iwqp->sc_qp.qp_uk, ukcq);
  368. }
  369. /**
  370. * i40iw_destroy_qp - destroy qp
  371. * @ibqp: qp's ib pointer also to get to device's qp address
  372. */
  373. static int i40iw_destroy_qp(struct ib_qp *ibqp)
  374. {
  375. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  376. iwqp->destroyed = 1;
  377. if (iwqp->ibqp_state >= IB_QPS_INIT && iwqp->ibqp_state < IB_QPS_RTS)
  378. i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 0, 0, 0);
  379. if (!iwqp->user_mode) {
  380. if (iwqp->iwscq) {
  381. i40iw_clean_cqes(iwqp, iwqp->iwscq);
  382. if (iwqp->iwrcq != iwqp->iwscq)
  383. i40iw_clean_cqes(iwqp, iwqp->iwrcq);
  384. }
  385. }
  386. i40iw_rem_ref(&iwqp->ibqp);
  387. return 0;
  388. }
  389. /**
  390. * i40iw_setup_virt_qp - setup for allocation of virtual qp
  391. * @dev: iwarp device
  392. * @qp: qp ptr
  393. * @init_info: initialize info to return
  394. */
  395. static int i40iw_setup_virt_qp(struct i40iw_device *iwdev,
  396. struct i40iw_qp *iwqp,
  397. struct i40iw_qp_init_info *init_info)
  398. {
  399. struct i40iw_pbl *iwpbl = &iwqp->iwpbl;
  400. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  401. iwqp->page = qpmr->sq_page;
  402. init_info->shadow_area_pa = cpu_to_le64(qpmr->shadow);
  403. if (iwpbl->pbl_allocated) {
  404. init_info->virtual_map = true;
  405. init_info->sq_pa = qpmr->sq_pbl.idx;
  406. init_info->rq_pa = qpmr->rq_pbl.idx;
  407. } else {
  408. init_info->sq_pa = qpmr->sq_pbl.addr;
  409. init_info->rq_pa = qpmr->rq_pbl.addr;
  410. }
  411. return 0;
  412. }
  413. /**
  414. * i40iw_setup_kmode_qp - setup initialization for kernel mode qp
  415. * @iwdev: iwarp device
  416. * @iwqp: qp ptr (user or kernel)
  417. * @info: initialize info to return
  418. */
  419. static int i40iw_setup_kmode_qp(struct i40iw_device *iwdev,
  420. struct i40iw_qp *iwqp,
  421. struct i40iw_qp_init_info *info)
  422. {
  423. struct i40iw_dma_mem *mem = &iwqp->kqp.dma_mem;
  424. u32 sqdepth, rqdepth;
  425. u8 sqshift;
  426. u32 size;
  427. enum i40iw_status_code status;
  428. struct i40iw_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
  429. i40iw_get_wqe_shift(ukinfo->max_sq_frag_cnt, ukinfo->max_inline_data, &sqshift);
  430. status = i40iw_get_sqdepth(ukinfo->sq_size, sqshift, &sqdepth);
  431. if (status)
  432. return -ENOMEM;
  433. status = i40iw_get_rqdepth(ukinfo->rq_size, I40IW_MAX_RQ_WQE_SHIFT, &rqdepth);
  434. if (status)
  435. return -ENOMEM;
  436. size = sqdepth * sizeof(struct i40iw_sq_uk_wr_trk_info) + (rqdepth << 3);
  437. iwqp->kqp.wrid_mem = kzalloc(size, GFP_KERNEL);
  438. ukinfo->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)iwqp->kqp.wrid_mem;
  439. if (!ukinfo->sq_wrtrk_array)
  440. return -ENOMEM;
  441. ukinfo->rq_wrid_array = (u64 *)&ukinfo->sq_wrtrk_array[sqdepth];
  442. size = (sqdepth + rqdepth) * I40IW_QP_WQE_MIN_SIZE;
  443. size += (I40IW_SHADOW_AREA_SIZE << 3);
  444. status = i40iw_allocate_dma_mem(iwdev->sc_dev.hw, mem, size, 256);
  445. if (status) {
  446. kfree(ukinfo->sq_wrtrk_array);
  447. ukinfo->sq_wrtrk_array = NULL;
  448. return -ENOMEM;
  449. }
  450. ukinfo->sq = mem->va;
  451. info->sq_pa = mem->pa;
  452. ukinfo->rq = &ukinfo->sq[sqdepth];
  453. info->rq_pa = info->sq_pa + (sqdepth * I40IW_QP_WQE_MIN_SIZE);
  454. ukinfo->shadow_area = ukinfo->rq[rqdepth].elem;
  455. info->shadow_area_pa = info->rq_pa + (rqdepth * I40IW_QP_WQE_MIN_SIZE);
  456. ukinfo->sq_size = sqdepth >> sqshift;
  457. ukinfo->rq_size = rqdepth >> I40IW_MAX_RQ_WQE_SHIFT;
  458. ukinfo->qp_id = iwqp->ibqp.qp_num;
  459. return 0;
  460. }
  461. /**
  462. * i40iw_create_qp - create qp
  463. * @ibpd: ptr of pd
  464. * @init_attr: attributes for qp
  465. * @udata: user data for create qp
  466. */
  467. static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
  468. struct ib_qp_init_attr *init_attr,
  469. struct ib_udata *udata)
  470. {
  471. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  472. struct i40iw_device *iwdev = to_iwdev(ibpd->device);
  473. struct i40iw_cqp *iwcqp = &iwdev->cqp;
  474. struct i40iw_qp *iwqp;
  475. struct i40iw_ucontext *ucontext;
  476. struct i40iw_create_qp_req req;
  477. struct i40iw_create_qp_resp uresp;
  478. u32 qp_num = 0;
  479. void *mem;
  480. enum i40iw_status_code ret;
  481. int err_code;
  482. int sq_size;
  483. int rq_size;
  484. struct i40iw_sc_qp *qp;
  485. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  486. struct i40iw_qp_init_info init_info;
  487. struct i40iw_create_qp_info *qp_info;
  488. struct i40iw_cqp_request *cqp_request;
  489. struct cqp_commands_info *cqp_info;
  490. struct i40iw_qp_host_ctx_info *ctx_info;
  491. struct i40iwarp_offload_info *iwarp_info;
  492. unsigned long flags;
  493. if (iwdev->closing)
  494. return ERR_PTR(-ENODEV);
  495. if (init_attr->create_flags)
  496. return ERR_PTR(-EINVAL);
  497. if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
  498. init_attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  499. if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
  500. init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  501. if (init_attr->cap.max_recv_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
  502. init_attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  503. memset(&init_info, 0, sizeof(init_info));
  504. sq_size = init_attr->cap.max_send_wr;
  505. rq_size = init_attr->cap.max_recv_wr;
  506. init_info.vsi = &iwdev->vsi;
  507. init_info.qp_uk_init_info.sq_size = sq_size;
  508. init_info.qp_uk_init_info.rq_size = rq_size;
  509. init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
  510. init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
  511. init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
  512. mem = kzalloc(sizeof(*iwqp), GFP_KERNEL);
  513. if (!mem)
  514. return ERR_PTR(-ENOMEM);
  515. iwqp = (struct i40iw_qp *)mem;
  516. iwqp->allocated_buffer = mem;
  517. qp = &iwqp->sc_qp;
  518. qp->back_qp = (void *)iwqp;
  519. qp->push_idx = I40IW_INVALID_PUSH_PAGE_INDEX;
  520. iwqp->ctx_info.iwarp_info = &iwqp->iwarp_info;
  521. if (i40iw_allocate_dma_mem(dev->hw,
  522. &iwqp->q2_ctx_mem,
  523. I40IW_Q2_BUFFER_SIZE + I40IW_QP_CTX_SIZE,
  524. 256)) {
  525. i40iw_pr_err("dma_mem failed\n");
  526. err_code = -ENOMEM;
  527. goto error;
  528. }
  529. init_info.q2 = iwqp->q2_ctx_mem.va;
  530. init_info.q2_pa = iwqp->q2_ctx_mem.pa;
  531. init_info.host_ctx = (void *)init_info.q2 + I40IW_Q2_BUFFER_SIZE;
  532. init_info.host_ctx_pa = init_info.q2_pa + I40IW_Q2_BUFFER_SIZE;
  533. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_qps, iwdev->max_qp,
  534. &qp_num, &iwdev->next_qp);
  535. if (err_code) {
  536. i40iw_pr_err("qp resource\n");
  537. goto error;
  538. }
  539. iwqp->iwdev = iwdev;
  540. iwqp->iwpd = iwpd;
  541. iwqp->ibqp.qp_num = qp_num;
  542. qp = &iwqp->sc_qp;
  543. iwqp->iwscq = to_iwcq(init_attr->send_cq);
  544. iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
  545. iwqp->host_ctx.va = init_info.host_ctx;
  546. iwqp->host_ctx.pa = init_info.host_ctx_pa;
  547. iwqp->host_ctx.size = I40IW_QP_CTX_SIZE;
  548. init_info.pd = &iwpd->sc_pd;
  549. init_info.qp_uk_init_info.qp_id = iwqp->ibqp.qp_num;
  550. iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
  551. if (init_attr->qp_type != IB_QPT_RC) {
  552. err_code = -EINVAL;
  553. goto error;
  554. }
  555. if (iwdev->push_mode)
  556. i40iw_alloc_push_page(iwdev, qp);
  557. if (udata) {
  558. err_code = ib_copy_from_udata(&req, udata, sizeof(req));
  559. if (err_code) {
  560. i40iw_pr_err("ib_copy_from_data\n");
  561. goto error;
  562. }
  563. iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
  564. if (ibpd->uobject && ibpd->uobject->context) {
  565. iwqp->user_mode = 1;
  566. ucontext = to_ucontext(ibpd->uobject->context);
  567. if (req.user_wqe_buffers) {
  568. struct i40iw_pbl *iwpbl;
  569. spin_lock_irqsave(
  570. &ucontext->qp_reg_mem_list_lock, flags);
  571. iwpbl = i40iw_get_pbl(
  572. (unsigned long)req.user_wqe_buffers,
  573. &ucontext->qp_reg_mem_list);
  574. spin_unlock_irqrestore(
  575. &ucontext->qp_reg_mem_list_lock, flags);
  576. if (!iwpbl) {
  577. err_code = -ENODATA;
  578. i40iw_pr_err("no pbl info\n");
  579. goto error;
  580. }
  581. memcpy(&iwqp->iwpbl, iwpbl, sizeof(iwqp->iwpbl));
  582. }
  583. }
  584. err_code = i40iw_setup_virt_qp(iwdev, iwqp, &init_info);
  585. } else {
  586. err_code = i40iw_setup_kmode_qp(iwdev, iwqp, &init_info);
  587. }
  588. if (err_code) {
  589. i40iw_pr_err("setup qp failed\n");
  590. goto error;
  591. }
  592. init_info.type = I40IW_QP_TYPE_IWARP;
  593. ret = dev->iw_priv_qp_ops->qp_init(qp, &init_info);
  594. if (ret) {
  595. err_code = -EPROTO;
  596. i40iw_pr_err("qp_init fail\n");
  597. goto error;
  598. }
  599. ctx_info = &iwqp->ctx_info;
  600. iwarp_info = &iwqp->iwarp_info;
  601. iwarp_info->rd_enable = true;
  602. iwarp_info->wr_rdresp_en = true;
  603. if (!iwqp->user_mode) {
  604. iwarp_info->fast_reg_en = true;
  605. iwarp_info->priv_mode_en = true;
  606. }
  607. iwarp_info->ddp_ver = 1;
  608. iwarp_info->rdmap_ver = 1;
  609. ctx_info->iwarp_info_valid = true;
  610. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  611. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  612. if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) {
  613. ctx_info->push_mode_en = false;
  614. } else {
  615. ctx_info->push_mode_en = true;
  616. ctx_info->push_idx = qp->push_idx;
  617. }
  618. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  619. (u64 *)iwqp->host_ctx.va,
  620. ctx_info);
  621. ctx_info->iwarp_info_valid = false;
  622. cqp_request = i40iw_get_cqp_request(iwcqp, true);
  623. if (!cqp_request) {
  624. err_code = -ENOMEM;
  625. goto error;
  626. }
  627. cqp_info = &cqp_request->info;
  628. qp_info = &cqp_request->info.in.u.qp_create.info;
  629. memset(qp_info, 0, sizeof(*qp_info));
  630. qp_info->cq_num_valid = true;
  631. qp_info->next_iwarp_state = I40IW_QP_STATE_IDLE;
  632. cqp_info->cqp_cmd = OP_QP_CREATE;
  633. cqp_info->post_sq = 1;
  634. cqp_info->in.u.qp_create.qp = qp;
  635. cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
  636. ret = i40iw_handle_cqp_op(iwdev, cqp_request);
  637. if (ret) {
  638. i40iw_pr_err("CQP-OP QP create fail");
  639. err_code = -EACCES;
  640. goto error;
  641. }
  642. i40iw_add_ref(&iwqp->ibqp);
  643. spin_lock_init(&iwqp->lock);
  644. iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
  645. iwdev->qp_table[qp_num] = iwqp;
  646. i40iw_add_pdusecount(iwqp->iwpd);
  647. i40iw_add_devusecount(iwdev);
  648. if (ibpd->uobject && udata) {
  649. memset(&uresp, 0, sizeof(uresp));
  650. uresp.actual_sq_size = sq_size;
  651. uresp.actual_rq_size = rq_size;
  652. uresp.qp_id = qp_num;
  653. uresp.push_idx = qp->push_idx;
  654. err_code = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  655. if (err_code) {
  656. i40iw_pr_err("copy_to_udata failed\n");
  657. i40iw_destroy_qp(&iwqp->ibqp);
  658. /* let the completion of the qp destroy free the qp */
  659. return ERR_PTR(err_code);
  660. }
  661. }
  662. init_completion(&iwqp->sq_drained);
  663. init_completion(&iwqp->rq_drained);
  664. return &iwqp->ibqp;
  665. error:
  666. i40iw_free_qp_resources(iwdev, iwqp, qp_num);
  667. return ERR_PTR(err_code);
  668. }
  669. /**
  670. * i40iw_query - query qp attributes
  671. * @ibqp: qp pointer
  672. * @attr: attributes pointer
  673. * @attr_mask: Not used
  674. * @init_attr: qp attributes to return
  675. */
  676. static int i40iw_query_qp(struct ib_qp *ibqp,
  677. struct ib_qp_attr *attr,
  678. int attr_mask,
  679. struct ib_qp_init_attr *init_attr)
  680. {
  681. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  682. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  683. attr->qp_state = iwqp->ibqp_state;
  684. attr->cur_qp_state = attr->qp_state;
  685. attr->qp_access_flags = 0;
  686. attr->cap.max_send_wr = qp->qp_uk.sq_size;
  687. attr->cap.max_recv_wr = qp->qp_uk.rq_size;
  688. attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
  689. attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  690. attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
  691. attr->port_num = 1;
  692. init_attr->event_handler = iwqp->ibqp.event_handler;
  693. init_attr->qp_context = iwqp->ibqp.qp_context;
  694. init_attr->send_cq = iwqp->ibqp.send_cq;
  695. init_attr->recv_cq = iwqp->ibqp.recv_cq;
  696. init_attr->srq = iwqp->ibqp.srq;
  697. init_attr->cap = attr->cap;
  698. init_attr->port_num = 1;
  699. return 0;
  700. }
  701. /**
  702. * i40iw_hw_modify_qp - setup cqp for modify qp
  703. * @iwdev: iwarp device
  704. * @iwqp: qp ptr (user or kernel)
  705. * @info: info for modify qp
  706. * @wait: flag to wait or not for modify qp completion
  707. */
  708. void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
  709. struct i40iw_modify_qp_info *info, bool wait)
  710. {
  711. struct i40iw_cqp_request *cqp_request;
  712. struct cqp_commands_info *cqp_info;
  713. struct i40iw_modify_qp_info *m_info;
  714. struct i40iw_gen_ae_info ae_info;
  715. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
  716. if (!cqp_request)
  717. return;
  718. cqp_info = &cqp_request->info;
  719. m_info = &cqp_info->in.u.qp_modify.info;
  720. memcpy(m_info, info, sizeof(*m_info));
  721. cqp_info->cqp_cmd = OP_QP_MODIFY;
  722. cqp_info->post_sq = 1;
  723. cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
  724. cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
  725. if (!i40iw_handle_cqp_op(iwdev, cqp_request))
  726. return;
  727. switch (m_info->next_iwarp_state) {
  728. case I40IW_QP_STATE_RTS:
  729. if (iwqp->iwarp_state == I40IW_QP_STATE_IDLE)
  730. i40iw_send_reset(iwqp->cm_node);
  731. /* fall through */
  732. case I40IW_QP_STATE_IDLE:
  733. case I40IW_QP_STATE_TERMINATE:
  734. case I40IW_QP_STATE_CLOSING:
  735. ae_info.ae_code = I40IW_AE_BAD_CLOSE;
  736. ae_info.ae_source = 0;
  737. i40iw_gen_ae(iwdev, &iwqp->sc_qp, &ae_info, false);
  738. break;
  739. case I40IW_QP_STATE_ERROR:
  740. default:
  741. break;
  742. }
  743. }
  744. /**
  745. * i40iw_modify_qp - modify qp request
  746. * @ibqp: qp's pointer for modify
  747. * @attr: access attributes
  748. * @attr_mask: state mask
  749. * @udata: user data
  750. */
  751. int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  752. int attr_mask, struct ib_udata *udata)
  753. {
  754. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  755. struct i40iw_device *iwdev = iwqp->iwdev;
  756. struct i40iw_qp_host_ctx_info *ctx_info;
  757. struct i40iwarp_offload_info *iwarp_info;
  758. struct i40iw_modify_qp_info info;
  759. u8 issue_modify_qp = 0;
  760. u8 dont_wait = 0;
  761. u32 err;
  762. unsigned long flags;
  763. memset(&info, 0, sizeof(info));
  764. ctx_info = &iwqp->ctx_info;
  765. iwarp_info = &iwqp->iwarp_info;
  766. spin_lock_irqsave(&iwqp->lock, flags);
  767. if (attr_mask & IB_QP_STATE) {
  768. if (iwdev->closing && attr->qp_state != IB_QPS_ERR) {
  769. err = -EINVAL;
  770. goto exit;
  771. }
  772. switch (attr->qp_state) {
  773. case IB_QPS_INIT:
  774. case IB_QPS_RTR:
  775. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_IDLE) {
  776. err = -EINVAL;
  777. goto exit;
  778. }
  779. if (iwqp->iwarp_state == I40IW_QP_STATE_INVALID) {
  780. info.next_iwarp_state = I40IW_QP_STATE_IDLE;
  781. issue_modify_qp = 1;
  782. }
  783. break;
  784. case IB_QPS_RTS:
  785. if ((iwqp->iwarp_state > (u32)I40IW_QP_STATE_RTS) ||
  786. (!iwqp->cm_id)) {
  787. err = -EINVAL;
  788. goto exit;
  789. }
  790. issue_modify_qp = 1;
  791. iwqp->hw_tcp_state = I40IW_TCP_STATE_ESTABLISHED;
  792. iwqp->hte_added = 1;
  793. info.next_iwarp_state = I40IW_QP_STATE_RTS;
  794. info.tcp_ctx_valid = true;
  795. info.ord_valid = true;
  796. info.arp_cache_idx_valid = true;
  797. info.cq_num_valid = true;
  798. break;
  799. case IB_QPS_SQD:
  800. if (iwqp->hw_iwarp_state > (u32)I40IW_QP_STATE_RTS) {
  801. err = 0;
  802. goto exit;
  803. }
  804. if ((iwqp->iwarp_state == (u32)I40IW_QP_STATE_CLOSING) ||
  805. (iwqp->iwarp_state < (u32)I40IW_QP_STATE_RTS)) {
  806. err = 0;
  807. goto exit;
  808. }
  809. if (iwqp->iwarp_state > (u32)I40IW_QP_STATE_CLOSING) {
  810. err = -EINVAL;
  811. goto exit;
  812. }
  813. info.next_iwarp_state = I40IW_QP_STATE_CLOSING;
  814. issue_modify_qp = 1;
  815. break;
  816. case IB_QPS_SQE:
  817. if (iwqp->iwarp_state >= (u32)I40IW_QP_STATE_TERMINATE) {
  818. err = -EINVAL;
  819. goto exit;
  820. }
  821. info.next_iwarp_state = I40IW_QP_STATE_TERMINATE;
  822. issue_modify_qp = 1;
  823. break;
  824. case IB_QPS_ERR:
  825. case IB_QPS_RESET:
  826. if (iwqp->iwarp_state == (u32)I40IW_QP_STATE_ERROR) {
  827. err = -EINVAL;
  828. goto exit;
  829. }
  830. if (iwqp->sc_qp.term_flags)
  831. i40iw_terminate_del_timer(&iwqp->sc_qp);
  832. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  833. if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
  834. iwdev->iw_status &&
  835. (iwqp->hw_tcp_state != I40IW_TCP_STATE_TIME_WAIT))
  836. info.reset_tcp_conn = true;
  837. else
  838. dont_wait = 1;
  839. issue_modify_qp = 1;
  840. info.next_iwarp_state = I40IW_QP_STATE_ERROR;
  841. break;
  842. default:
  843. err = -EINVAL;
  844. goto exit;
  845. }
  846. iwqp->ibqp_state = attr->qp_state;
  847. }
  848. if (attr_mask & IB_QP_ACCESS_FLAGS) {
  849. ctx_info->iwarp_info_valid = true;
  850. if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
  851. iwarp_info->wr_rdresp_en = true;
  852. if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
  853. iwarp_info->wr_rdresp_en = true;
  854. if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
  855. iwarp_info->rd_enable = true;
  856. if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
  857. iwarp_info->bind_en = true;
  858. if (iwqp->user_mode) {
  859. iwarp_info->rd_enable = true;
  860. iwarp_info->wr_rdresp_en = true;
  861. iwarp_info->priv_mode_en = false;
  862. }
  863. }
  864. if (ctx_info->iwarp_info_valid) {
  865. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  866. int ret;
  867. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  868. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  869. ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
  870. (u64 *)iwqp->host_ctx.va,
  871. ctx_info);
  872. if (ret) {
  873. i40iw_pr_err("setting QP context\n");
  874. err = -EINVAL;
  875. goto exit;
  876. }
  877. }
  878. spin_unlock_irqrestore(&iwqp->lock, flags);
  879. if (issue_modify_qp) {
  880. i40iw_hw_modify_qp(iwdev, iwqp, &info, true);
  881. spin_lock_irqsave(&iwqp->lock, flags);
  882. iwqp->iwarp_state = info.next_iwarp_state;
  883. spin_unlock_irqrestore(&iwqp->lock, flags);
  884. }
  885. if (issue_modify_qp && (iwqp->ibqp_state > IB_QPS_RTS)) {
  886. if (dont_wait) {
  887. if (iwqp->cm_id && iwqp->hw_tcp_state) {
  888. spin_lock_irqsave(&iwqp->lock, flags);
  889. iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSED;
  890. iwqp->last_aeq = I40IW_AE_RESET_SENT;
  891. spin_unlock_irqrestore(&iwqp->lock, flags);
  892. i40iw_cm_disconn(iwqp);
  893. }
  894. } else {
  895. spin_lock_irqsave(&iwqp->lock, flags);
  896. if (iwqp->cm_id) {
  897. if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
  898. iwqp->cm_id->add_ref(iwqp->cm_id);
  899. i40iw_schedule_cm_timer(iwqp->cm_node,
  900. (struct i40iw_puda_buf *)iwqp,
  901. I40IW_TIMER_TYPE_CLOSE, 1, 0);
  902. }
  903. }
  904. spin_unlock_irqrestore(&iwqp->lock, flags);
  905. }
  906. }
  907. return 0;
  908. exit:
  909. spin_unlock_irqrestore(&iwqp->lock, flags);
  910. return err;
  911. }
  912. /**
  913. * cq_free_resources - free up recources for cq
  914. * @iwdev: iwarp device
  915. * @iwcq: cq ptr
  916. */
  917. static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
  918. {
  919. struct i40iw_sc_cq *cq = &iwcq->sc_cq;
  920. if (!iwcq->user_mode)
  921. i40iw_free_dma_mem(iwdev->sc_dev.hw, &iwcq->kmem);
  922. i40iw_free_resource(iwdev, iwdev->allocated_cqs, cq->cq_uk.cq_id);
  923. }
  924. /**
  925. * i40iw_cq_wq_destroy - send cq destroy cqp
  926. * @iwdev: iwarp device
  927. * @cq: hardware control cq
  928. */
  929. void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
  930. {
  931. enum i40iw_status_code status;
  932. struct i40iw_cqp_request *cqp_request;
  933. struct cqp_commands_info *cqp_info;
  934. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  935. if (!cqp_request)
  936. return;
  937. cqp_info = &cqp_request->info;
  938. cqp_info->cqp_cmd = OP_CQ_DESTROY;
  939. cqp_info->post_sq = 1;
  940. cqp_info->in.u.cq_destroy.cq = cq;
  941. cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
  942. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  943. if (status)
  944. i40iw_pr_err("CQP-OP Destroy QP fail");
  945. }
  946. /**
  947. * i40iw_destroy_cq - destroy cq
  948. * @ib_cq: cq pointer
  949. */
  950. static int i40iw_destroy_cq(struct ib_cq *ib_cq)
  951. {
  952. struct i40iw_cq *iwcq;
  953. struct i40iw_device *iwdev;
  954. struct i40iw_sc_cq *cq;
  955. if (!ib_cq) {
  956. i40iw_pr_err("ib_cq == NULL\n");
  957. return 0;
  958. }
  959. iwcq = to_iwcq(ib_cq);
  960. iwdev = to_iwdev(ib_cq->device);
  961. cq = &iwcq->sc_cq;
  962. i40iw_cq_wq_destroy(iwdev, cq);
  963. cq_free_resources(iwdev, iwcq);
  964. kfree(iwcq);
  965. i40iw_rem_devusecount(iwdev);
  966. return 0;
  967. }
  968. /**
  969. * i40iw_create_cq - create cq
  970. * @ibdev: device pointer from stack
  971. * @attr: attributes for cq
  972. * @context: user context created during alloc
  973. * @udata: user data
  974. */
  975. static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
  976. const struct ib_cq_init_attr *attr,
  977. struct ib_ucontext *context,
  978. struct ib_udata *udata)
  979. {
  980. struct i40iw_device *iwdev = to_iwdev(ibdev);
  981. struct i40iw_cq *iwcq;
  982. struct i40iw_pbl *iwpbl;
  983. u32 cq_num = 0;
  984. struct i40iw_sc_cq *cq;
  985. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  986. struct i40iw_cq_init_info info;
  987. enum i40iw_status_code status;
  988. struct i40iw_cqp_request *cqp_request;
  989. struct cqp_commands_info *cqp_info;
  990. struct i40iw_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
  991. unsigned long flags;
  992. int err_code;
  993. int entries = attr->cqe;
  994. if (iwdev->closing)
  995. return ERR_PTR(-ENODEV);
  996. if (entries > iwdev->max_cqe)
  997. return ERR_PTR(-EINVAL);
  998. iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL);
  999. if (!iwcq)
  1000. return ERR_PTR(-ENOMEM);
  1001. memset(&info, 0, sizeof(info));
  1002. err_code = i40iw_alloc_resource(iwdev, iwdev->allocated_cqs,
  1003. iwdev->max_cq, &cq_num,
  1004. &iwdev->next_cq);
  1005. if (err_code)
  1006. goto error;
  1007. cq = &iwcq->sc_cq;
  1008. cq->back_cq = (void *)iwcq;
  1009. spin_lock_init(&iwcq->lock);
  1010. info.dev = dev;
  1011. ukinfo->cq_size = max(entries, 4);
  1012. ukinfo->cq_id = cq_num;
  1013. iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
  1014. info.ceqe_mask = 0;
  1015. if (attr->comp_vector < iwdev->ceqs_count)
  1016. info.ceq_id = attr->comp_vector;
  1017. info.ceq_id_valid = true;
  1018. info.ceqe_mask = 1;
  1019. info.type = I40IW_CQ_TYPE_IWARP;
  1020. if (context) {
  1021. struct i40iw_ucontext *ucontext;
  1022. struct i40iw_create_cq_req req;
  1023. struct i40iw_cq_mr *cqmr;
  1024. memset(&req, 0, sizeof(req));
  1025. iwcq->user_mode = true;
  1026. ucontext = to_ucontext(context);
  1027. if (ib_copy_from_udata(&req, udata, sizeof(struct i40iw_create_cq_req))) {
  1028. err_code = -EFAULT;
  1029. goto cq_free_resources;
  1030. }
  1031. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1032. iwpbl = i40iw_get_pbl((unsigned long)req.user_cq_buffer,
  1033. &ucontext->cq_reg_mem_list);
  1034. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1035. if (!iwpbl) {
  1036. err_code = -EPROTO;
  1037. goto cq_free_resources;
  1038. }
  1039. iwcq->iwpbl = iwpbl;
  1040. iwcq->cq_mem_size = 0;
  1041. cqmr = &iwpbl->cq_mr;
  1042. info.shadow_area_pa = cpu_to_le64(cqmr->shadow);
  1043. if (iwpbl->pbl_allocated) {
  1044. info.virtual_map = true;
  1045. info.pbl_chunk_size = 1;
  1046. info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
  1047. } else {
  1048. info.cq_base_pa = cqmr->cq_pbl.addr;
  1049. }
  1050. } else {
  1051. /* Kmode allocations */
  1052. int rsize;
  1053. int shadow;
  1054. rsize = info.cq_uk_init_info.cq_size * sizeof(struct i40iw_cqe);
  1055. rsize = round_up(rsize, 256);
  1056. shadow = I40IW_SHADOW_AREA_SIZE << 3;
  1057. status = i40iw_allocate_dma_mem(dev->hw, &iwcq->kmem,
  1058. rsize + shadow, 256);
  1059. if (status) {
  1060. err_code = -ENOMEM;
  1061. goto cq_free_resources;
  1062. }
  1063. ukinfo->cq_base = iwcq->kmem.va;
  1064. info.cq_base_pa = iwcq->kmem.pa;
  1065. info.shadow_area_pa = info.cq_base_pa + rsize;
  1066. ukinfo->shadow_area = iwcq->kmem.va + rsize;
  1067. }
  1068. if (dev->iw_priv_cq_ops->cq_init(cq, &info)) {
  1069. i40iw_pr_err("init cq fail\n");
  1070. err_code = -EPROTO;
  1071. goto cq_free_resources;
  1072. }
  1073. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1074. if (!cqp_request) {
  1075. err_code = -ENOMEM;
  1076. goto cq_free_resources;
  1077. }
  1078. cqp_info = &cqp_request->info;
  1079. cqp_info->cqp_cmd = OP_CQ_CREATE;
  1080. cqp_info->post_sq = 1;
  1081. cqp_info->in.u.cq_create.cq = cq;
  1082. cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
  1083. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1084. if (status) {
  1085. i40iw_pr_err("CQP-OP Create QP fail");
  1086. err_code = -EPROTO;
  1087. goto cq_free_resources;
  1088. }
  1089. if (context) {
  1090. struct i40iw_create_cq_resp resp;
  1091. memset(&resp, 0, sizeof(resp));
  1092. resp.cq_id = info.cq_uk_init_info.cq_id;
  1093. resp.cq_size = info.cq_uk_init_info.cq_size;
  1094. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  1095. i40iw_pr_err("copy to user data\n");
  1096. err_code = -EPROTO;
  1097. goto cq_destroy;
  1098. }
  1099. }
  1100. i40iw_add_devusecount(iwdev);
  1101. return (struct ib_cq *)iwcq;
  1102. cq_destroy:
  1103. i40iw_cq_wq_destroy(iwdev, cq);
  1104. cq_free_resources:
  1105. cq_free_resources(iwdev, iwcq);
  1106. error:
  1107. kfree(iwcq);
  1108. return ERR_PTR(err_code);
  1109. }
  1110. /**
  1111. * i40iw_get_user_access - get hw access from IB access
  1112. * @acc: IB access to return hw access
  1113. */
  1114. static inline u16 i40iw_get_user_access(int acc)
  1115. {
  1116. u16 access = 0;
  1117. access |= (acc & IB_ACCESS_LOCAL_WRITE) ? I40IW_ACCESS_FLAGS_LOCALWRITE : 0;
  1118. access |= (acc & IB_ACCESS_REMOTE_WRITE) ? I40IW_ACCESS_FLAGS_REMOTEWRITE : 0;
  1119. access |= (acc & IB_ACCESS_REMOTE_READ) ? I40IW_ACCESS_FLAGS_REMOTEREAD : 0;
  1120. access |= (acc & IB_ACCESS_MW_BIND) ? I40IW_ACCESS_FLAGS_BIND_WINDOW : 0;
  1121. return access;
  1122. }
  1123. /**
  1124. * i40iw_free_stag - free stag resource
  1125. * @iwdev: iwarp device
  1126. * @stag: stag to free
  1127. */
  1128. static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
  1129. {
  1130. u32 stag_idx;
  1131. stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1132. i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
  1133. i40iw_rem_devusecount(iwdev);
  1134. }
  1135. /**
  1136. * i40iw_create_stag - create random stag
  1137. * @iwdev: iwarp device
  1138. */
  1139. static u32 i40iw_create_stag(struct i40iw_device *iwdev)
  1140. {
  1141. u32 stag = 0;
  1142. u32 stag_index = 0;
  1143. u32 next_stag_index;
  1144. u32 driver_key;
  1145. u32 random;
  1146. u8 consumer_key;
  1147. int ret;
  1148. get_random_bytes(&random, sizeof(random));
  1149. consumer_key = (u8)random;
  1150. driver_key = random & ~iwdev->mr_stagmask;
  1151. next_stag_index = (random & iwdev->mr_stagmask) >> 8;
  1152. next_stag_index %= iwdev->max_mr;
  1153. ret = i40iw_alloc_resource(iwdev,
  1154. iwdev->allocated_mrs, iwdev->max_mr,
  1155. &stag_index, &next_stag_index);
  1156. if (!ret) {
  1157. stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
  1158. stag |= driver_key;
  1159. stag += (u32)consumer_key;
  1160. i40iw_add_devusecount(iwdev);
  1161. }
  1162. return stag;
  1163. }
  1164. /**
  1165. * i40iw_next_pbl_addr - Get next pbl address
  1166. * @pbl: pointer to a pble
  1167. * @pinfo: info pointer
  1168. * @idx: index
  1169. */
  1170. static inline u64 *i40iw_next_pbl_addr(u64 *pbl,
  1171. struct i40iw_pble_info **pinfo,
  1172. u32 *idx)
  1173. {
  1174. *idx += 1;
  1175. if ((!(*pinfo)) || (*idx != (*pinfo)->cnt))
  1176. return ++pbl;
  1177. *idx = 0;
  1178. (*pinfo)++;
  1179. return (u64 *)(*pinfo)->addr;
  1180. }
  1181. /**
  1182. * i40iw_copy_user_pgaddrs - copy user page address to pble's os locally
  1183. * @iwmr: iwmr for IB's user page addresses
  1184. * @pbl: ple pointer to save 1 level or 0 level pble
  1185. * @level: indicated level 0, 1 or 2
  1186. */
  1187. static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
  1188. u64 *pbl,
  1189. enum i40iw_pble_level level)
  1190. {
  1191. struct ib_umem *region = iwmr->region;
  1192. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1193. int chunk_pages, entry, i;
  1194. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1195. struct i40iw_pble_info *pinfo;
  1196. struct scatterlist *sg;
  1197. u64 pg_addr = 0;
  1198. u32 idx = 0;
  1199. pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
  1200. for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) {
  1201. chunk_pages = sg_dma_len(sg) >> region->page_shift;
  1202. if ((iwmr->type == IW_MEMREG_TYPE_QP) &&
  1203. !iwpbl->qp_mr.sq_page)
  1204. iwpbl->qp_mr.sq_page = sg_page(sg);
  1205. for (i = 0; i < chunk_pages; i++) {
  1206. pg_addr = sg_dma_address(sg) +
  1207. (i << region->page_shift);
  1208. if ((entry + i) == 0)
  1209. *pbl = cpu_to_le64(pg_addr & iwmr->page_msk);
  1210. else if (!(pg_addr & ~iwmr->page_msk))
  1211. *pbl = cpu_to_le64(pg_addr);
  1212. else
  1213. continue;
  1214. pbl = i40iw_next_pbl_addr(pbl, &pinfo, &idx);
  1215. }
  1216. }
  1217. }
  1218. /**
  1219. * i40iw_set_hugetlb_params - set MR pg size and mask to huge pg values.
  1220. * @addr: virtual address
  1221. * @iwmr: mr pointer for this memory registration
  1222. */
  1223. static void i40iw_set_hugetlb_values(u64 addr, struct i40iw_mr *iwmr)
  1224. {
  1225. struct vm_area_struct *vma;
  1226. struct hstate *h;
  1227. down_read(&current->mm->mmap_sem);
  1228. vma = find_vma(current->mm, addr);
  1229. if (vma && is_vm_hugetlb_page(vma)) {
  1230. h = hstate_vma(vma);
  1231. if (huge_page_size(h) == 0x200000) {
  1232. iwmr->page_size = huge_page_size(h);
  1233. iwmr->page_msk = huge_page_mask(h);
  1234. }
  1235. }
  1236. up_read(&current->mm->mmap_sem);
  1237. }
  1238. /**
  1239. * i40iw_check_mem_contiguous - check if pbls stored in arr are contiguous
  1240. * @arr: lvl1 pbl array
  1241. * @npages: page count
  1242. * pg_size: page size
  1243. *
  1244. */
  1245. static bool i40iw_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
  1246. {
  1247. u32 pg_idx;
  1248. for (pg_idx = 0; pg_idx < npages; pg_idx++) {
  1249. if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
  1250. return false;
  1251. }
  1252. return true;
  1253. }
  1254. /**
  1255. * i40iw_check_mr_contiguous - check if MR is physically contiguous
  1256. * @palloc: pbl allocation struct
  1257. * pg_size: page size
  1258. */
  1259. static bool i40iw_check_mr_contiguous(struct i40iw_pble_alloc *palloc, u32 pg_size)
  1260. {
  1261. struct i40iw_pble_level2 *lvl2 = &palloc->level2;
  1262. struct i40iw_pble_info *leaf = lvl2->leaf;
  1263. u64 *arr = NULL;
  1264. u64 *start_addr = NULL;
  1265. int i;
  1266. bool ret;
  1267. if (palloc->level == I40IW_LEVEL_1) {
  1268. arr = (u64 *)palloc->level1.addr;
  1269. ret = i40iw_check_mem_contiguous(arr, palloc->total_cnt, pg_size);
  1270. return ret;
  1271. }
  1272. start_addr = (u64 *)leaf->addr;
  1273. for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
  1274. arr = (u64 *)leaf->addr;
  1275. if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
  1276. return false;
  1277. ret = i40iw_check_mem_contiguous(arr, leaf->cnt, pg_size);
  1278. if (!ret)
  1279. return false;
  1280. }
  1281. return true;
  1282. }
  1283. /**
  1284. * i40iw_setup_pbles - copy user pg address to pble's
  1285. * @iwdev: iwarp device
  1286. * @iwmr: mr pointer for this memory registration
  1287. * @use_pbles: flag if to use pble's
  1288. */
  1289. static int i40iw_setup_pbles(struct i40iw_device *iwdev,
  1290. struct i40iw_mr *iwmr,
  1291. bool use_pbles)
  1292. {
  1293. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1294. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1295. struct i40iw_pble_info *pinfo;
  1296. u64 *pbl;
  1297. enum i40iw_status_code status;
  1298. enum i40iw_pble_level level = I40IW_LEVEL_1;
  1299. if (use_pbles) {
  1300. mutex_lock(&iwdev->pbl_mutex);
  1301. status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
  1302. mutex_unlock(&iwdev->pbl_mutex);
  1303. if (status)
  1304. return -ENOMEM;
  1305. iwpbl->pbl_allocated = true;
  1306. level = palloc->level;
  1307. pinfo = (level == I40IW_LEVEL_1) ? &palloc->level1 : palloc->level2.leaf;
  1308. pbl = (u64 *)pinfo->addr;
  1309. } else {
  1310. pbl = iwmr->pgaddrmem;
  1311. }
  1312. i40iw_copy_user_pgaddrs(iwmr, pbl, level);
  1313. if (use_pbles)
  1314. iwmr->pgaddrmem[0] = *pbl;
  1315. return 0;
  1316. }
  1317. /**
  1318. * i40iw_handle_q_mem - handle memory for qp and cq
  1319. * @iwdev: iwarp device
  1320. * @req: information for q memory management
  1321. * @iwpbl: pble struct
  1322. * @use_pbles: flag to use pble
  1323. */
  1324. static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
  1325. struct i40iw_mem_reg_req *req,
  1326. struct i40iw_pbl *iwpbl,
  1327. bool use_pbles)
  1328. {
  1329. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1330. struct i40iw_mr *iwmr = iwpbl->iwmr;
  1331. struct i40iw_qp_mr *qpmr = &iwpbl->qp_mr;
  1332. struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
  1333. struct i40iw_hmc_pble *hmc_p;
  1334. u64 *arr = iwmr->pgaddrmem;
  1335. u32 pg_size;
  1336. int err;
  1337. int total;
  1338. bool ret = true;
  1339. total = req->sq_pages + req->rq_pages + req->cq_pages;
  1340. pg_size = iwmr->page_size;
  1341. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1342. if (err)
  1343. return err;
  1344. if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
  1345. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1346. iwpbl->pbl_allocated = false;
  1347. return -ENOMEM;
  1348. }
  1349. if (use_pbles)
  1350. arr = (u64 *)palloc->level1.addr;
  1351. if (iwmr->type == IW_MEMREG_TYPE_QP) {
  1352. hmc_p = &qpmr->sq_pbl;
  1353. qpmr->shadow = (dma_addr_t)arr[total];
  1354. if (use_pbles) {
  1355. ret = i40iw_check_mem_contiguous(arr, req->sq_pages, pg_size);
  1356. if (ret)
  1357. ret = i40iw_check_mem_contiguous(&arr[req->sq_pages], req->rq_pages, pg_size);
  1358. }
  1359. if (!ret) {
  1360. hmc_p->idx = palloc->level1.idx;
  1361. hmc_p = &qpmr->rq_pbl;
  1362. hmc_p->idx = palloc->level1.idx + req->sq_pages;
  1363. } else {
  1364. hmc_p->addr = arr[0];
  1365. hmc_p = &qpmr->rq_pbl;
  1366. hmc_p->addr = arr[req->sq_pages];
  1367. }
  1368. } else { /* CQ */
  1369. hmc_p = &cqmr->cq_pbl;
  1370. cqmr->shadow = (dma_addr_t)arr[total];
  1371. if (use_pbles)
  1372. ret = i40iw_check_mem_contiguous(arr, req->cq_pages, pg_size);
  1373. if (!ret)
  1374. hmc_p->idx = palloc->level1.idx;
  1375. else
  1376. hmc_p->addr = arr[0];
  1377. }
  1378. if (use_pbles && ret) {
  1379. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1380. iwpbl->pbl_allocated = false;
  1381. }
  1382. return err;
  1383. }
  1384. /**
  1385. * i40iw_hw_alloc_stag - cqp command to allocate stag
  1386. * @iwdev: iwarp device
  1387. * @iwmr: iwarp mr pointer
  1388. */
  1389. static int i40iw_hw_alloc_stag(struct i40iw_device *iwdev, struct i40iw_mr *iwmr)
  1390. {
  1391. struct i40iw_allocate_stag_info *info;
  1392. struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  1393. enum i40iw_status_code status;
  1394. int err = 0;
  1395. struct i40iw_cqp_request *cqp_request;
  1396. struct cqp_commands_info *cqp_info;
  1397. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1398. if (!cqp_request)
  1399. return -ENOMEM;
  1400. cqp_info = &cqp_request->info;
  1401. info = &cqp_info->in.u.alloc_stag.info;
  1402. memset(info, 0, sizeof(*info));
  1403. info->page_size = PAGE_SIZE;
  1404. info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1405. info->pd_id = iwpd->sc_pd.pd_id;
  1406. info->total_len = iwmr->length;
  1407. info->remote_access = true;
  1408. cqp_info->cqp_cmd = OP_ALLOC_STAG;
  1409. cqp_info->post_sq = 1;
  1410. cqp_info->in.u.alloc_stag.dev = &iwdev->sc_dev;
  1411. cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
  1412. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1413. if (status) {
  1414. err = -ENOMEM;
  1415. i40iw_pr_err("CQP-OP MR Reg fail");
  1416. }
  1417. return err;
  1418. }
  1419. /**
  1420. * i40iw_alloc_mr - register stag for fast memory registration
  1421. * @pd: ibpd pointer
  1422. * @mr_type: memory for stag registrion
  1423. * @max_num_sg: man number of pages
  1424. */
  1425. static struct ib_mr *i40iw_alloc_mr(struct ib_pd *pd,
  1426. enum ib_mr_type mr_type,
  1427. u32 max_num_sg)
  1428. {
  1429. struct i40iw_pd *iwpd = to_iwpd(pd);
  1430. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1431. struct i40iw_pble_alloc *palloc;
  1432. struct i40iw_pbl *iwpbl;
  1433. struct i40iw_mr *iwmr;
  1434. enum i40iw_status_code status;
  1435. u32 stag;
  1436. int err_code = -ENOMEM;
  1437. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1438. if (!iwmr)
  1439. return ERR_PTR(-ENOMEM);
  1440. stag = i40iw_create_stag(iwdev);
  1441. if (!stag) {
  1442. err_code = -EOVERFLOW;
  1443. goto err;
  1444. }
  1445. stag &= ~I40IW_CQPSQ_STAG_KEY_MASK;
  1446. iwmr->stag = stag;
  1447. iwmr->ibmr.rkey = stag;
  1448. iwmr->ibmr.lkey = stag;
  1449. iwmr->ibmr.pd = pd;
  1450. iwmr->ibmr.device = pd->device;
  1451. iwpbl = &iwmr->iwpbl;
  1452. iwpbl->iwmr = iwmr;
  1453. iwmr->type = IW_MEMREG_TYPE_MEM;
  1454. palloc = &iwpbl->pble_alloc;
  1455. iwmr->page_cnt = max_num_sg;
  1456. mutex_lock(&iwdev->pbl_mutex);
  1457. status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
  1458. mutex_unlock(&iwdev->pbl_mutex);
  1459. if (status)
  1460. goto err1;
  1461. if (palloc->level != I40IW_LEVEL_1)
  1462. goto err2;
  1463. err_code = i40iw_hw_alloc_stag(iwdev, iwmr);
  1464. if (err_code)
  1465. goto err2;
  1466. iwpbl->pbl_allocated = true;
  1467. i40iw_add_pdusecount(iwpd);
  1468. return &iwmr->ibmr;
  1469. err2:
  1470. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1471. err1:
  1472. i40iw_free_stag(iwdev, stag);
  1473. err:
  1474. kfree(iwmr);
  1475. return ERR_PTR(err_code);
  1476. }
  1477. /**
  1478. * i40iw_set_page - populate pbl list for fmr
  1479. * @ibmr: ib mem to access iwarp mr pointer
  1480. * @addr: page dma address fro pbl list
  1481. */
  1482. static int i40iw_set_page(struct ib_mr *ibmr, u64 addr)
  1483. {
  1484. struct i40iw_mr *iwmr = to_iwmr(ibmr);
  1485. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1486. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1487. u64 *pbl;
  1488. if (unlikely(iwmr->npages == iwmr->page_cnt))
  1489. return -ENOMEM;
  1490. pbl = (u64 *)palloc->level1.addr;
  1491. pbl[iwmr->npages++] = cpu_to_le64(addr);
  1492. return 0;
  1493. }
  1494. /**
  1495. * i40iw_map_mr_sg - map of sg list for fmr
  1496. * @ibmr: ib mem to access iwarp mr pointer
  1497. * @sg: scatter gather list for fmr
  1498. * @sg_nents: number of sg pages
  1499. */
  1500. static int i40iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
  1501. int sg_nents, unsigned int *sg_offset)
  1502. {
  1503. struct i40iw_mr *iwmr = to_iwmr(ibmr);
  1504. iwmr->npages = 0;
  1505. return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, i40iw_set_page);
  1506. }
  1507. /**
  1508. * i40iw_drain_sq - drain the send queue
  1509. * @ibqp: ib qp pointer
  1510. */
  1511. static void i40iw_drain_sq(struct ib_qp *ibqp)
  1512. {
  1513. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  1514. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  1515. if (I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
  1516. wait_for_completion(&iwqp->sq_drained);
  1517. }
  1518. /**
  1519. * i40iw_drain_rq - drain the receive queue
  1520. * @ibqp: ib qp pointer
  1521. */
  1522. static void i40iw_drain_rq(struct ib_qp *ibqp)
  1523. {
  1524. struct i40iw_qp *iwqp = to_iwqp(ibqp);
  1525. struct i40iw_sc_qp *qp = &iwqp->sc_qp;
  1526. if (I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
  1527. wait_for_completion(&iwqp->rq_drained);
  1528. }
  1529. /**
  1530. * i40iw_hwreg_mr - send cqp command for memory registration
  1531. * @iwdev: iwarp device
  1532. * @iwmr: iwarp mr pointer
  1533. * @access: access for MR
  1534. */
  1535. static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
  1536. struct i40iw_mr *iwmr,
  1537. u16 access)
  1538. {
  1539. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1540. struct i40iw_reg_ns_stag_info *stag_info;
  1541. struct i40iw_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  1542. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1543. enum i40iw_status_code status;
  1544. int err = 0;
  1545. struct i40iw_cqp_request *cqp_request;
  1546. struct cqp_commands_info *cqp_info;
  1547. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1548. if (!cqp_request)
  1549. return -ENOMEM;
  1550. cqp_info = &cqp_request->info;
  1551. stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
  1552. memset(stag_info, 0, sizeof(*stag_info));
  1553. stag_info->va = (void *)(unsigned long)iwpbl->user_base;
  1554. stag_info->stag_idx = iwmr->stag >> I40IW_CQPSQ_STAG_IDX_SHIFT;
  1555. stag_info->stag_key = (u8)iwmr->stag;
  1556. stag_info->total_len = iwmr->length;
  1557. stag_info->access_rights = access;
  1558. stag_info->pd_id = iwpd->sc_pd.pd_id;
  1559. stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
  1560. stag_info->page_size = iwmr->page_size;
  1561. if (iwpbl->pbl_allocated) {
  1562. if (palloc->level == I40IW_LEVEL_1) {
  1563. stag_info->first_pm_pbl_index = palloc->level1.idx;
  1564. stag_info->chunk_size = 1;
  1565. } else {
  1566. stag_info->first_pm_pbl_index = palloc->level2.root.idx;
  1567. stag_info->chunk_size = 3;
  1568. }
  1569. } else {
  1570. stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
  1571. }
  1572. cqp_info->cqp_cmd = OP_MR_REG_NON_SHARED;
  1573. cqp_info->post_sq = 1;
  1574. cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->sc_dev;
  1575. cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
  1576. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1577. if (status) {
  1578. err = -ENOMEM;
  1579. i40iw_pr_err("CQP-OP MR Reg fail");
  1580. }
  1581. return err;
  1582. }
  1583. /**
  1584. * i40iw_reg_user_mr - Register a user memory region
  1585. * @pd: ptr of pd
  1586. * @start: virtual start address
  1587. * @length: length of mr
  1588. * @virt: virtual address
  1589. * @acc: access of mr
  1590. * @udata: user data
  1591. */
  1592. static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
  1593. u64 start,
  1594. u64 length,
  1595. u64 virt,
  1596. int acc,
  1597. struct ib_udata *udata)
  1598. {
  1599. struct i40iw_pd *iwpd = to_iwpd(pd);
  1600. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1601. struct i40iw_ucontext *ucontext;
  1602. struct i40iw_pble_alloc *palloc;
  1603. struct i40iw_pbl *iwpbl;
  1604. struct i40iw_mr *iwmr;
  1605. struct ib_umem *region;
  1606. struct i40iw_mem_reg_req req;
  1607. u64 pbl_depth = 0;
  1608. u32 stag = 0;
  1609. u16 access;
  1610. u64 region_length;
  1611. bool use_pbles = false;
  1612. unsigned long flags;
  1613. int err = -ENOSYS;
  1614. int ret;
  1615. int pg_shift;
  1616. if (iwdev->closing)
  1617. return ERR_PTR(-ENODEV);
  1618. if (length > I40IW_MAX_MR_SIZE)
  1619. return ERR_PTR(-EINVAL);
  1620. region = ib_umem_get(pd->uobject->context, start, length, acc, 0);
  1621. if (IS_ERR(region))
  1622. return (struct ib_mr *)region;
  1623. if (ib_copy_from_udata(&req, udata, sizeof(req))) {
  1624. ib_umem_release(region);
  1625. return ERR_PTR(-EFAULT);
  1626. }
  1627. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1628. if (!iwmr) {
  1629. ib_umem_release(region);
  1630. return ERR_PTR(-ENOMEM);
  1631. }
  1632. iwpbl = &iwmr->iwpbl;
  1633. iwpbl->iwmr = iwmr;
  1634. iwmr->region = region;
  1635. iwmr->ibmr.pd = pd;
  1636. iwmr->ibmr.device = pd->device;
  1637. ucontext = to_ucontext(pd->uobject->context);
  1638. iwmr->page_size = PAGE_SIZE;
  1639. iwmr->page_msk = PAGE_MASK;
  1640. if (region->hugetlb && (req.reg_type == IW_MEMREG_TYPE_MEM))
  1641. i40iw_set_hugetlb_values(start, iwmr);
  1642. region_length = region->length + (start & (iwmr->page_size - 1));
  1643. pg_shift = ffs(iwmr->page_size) - 1;
  1644. pbl_depth = region_length >> pg_shift;
  1645. pbl_depth += (region_length & (iwmr->page_size - 1)) ? 1 : 0;
  1646. iwmr->length = region->length;
  1647. iwpbl->user_base = virt;
  1648. palloc = &iwpbl->pble_alloc;
  1649. iwmr->type = req.reg_type;
  1650. iwmr->page_cnt = (u32)pbl_depth;
  1651. switch (req.reg_type) {
  1652. case IW_MEMREG_TYPE_QP:
  1653. use_pbles = ((req.sq_pages + req.rq_pages) > 2);
  1654. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1655. if (err)
  1656. goto error;
  1657. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1658. list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
  1659. iwpbl->on_list = true;
  1660. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1661. break;
  1662. case IW_MEMREG_TYPE_CQ:
  1663. use_pbles = (req.cq_pages > 1);
  1664. err = i40iw_handle_q_mem(iwdev, &req, iwpbl, use_pbles);
  1665. if (err)
  1666. goto error;
  1667. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1668. list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
  1669. iwpbl->on_list = true;
  1670. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1671. break;
  1672. case IW_MEMREG_TYPE_MEM:
  1673. use_pbles = (iwmr->page_cnt != 1);
  1674. access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1675. err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
  1676. if (err)
  1677. goto error;
  1678. if (use_pbles) {
  1679. ret = i40iw_check_mr_contiguous(palloc, iwmr->page_size);
  1680. if (ret) {
  1681. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1682. iwpbl->pbl_allocated = false;
  1683. }
  1684. }
  1685. access |= i40iw_get_user_access(acc);
  1686. stag = i40iw_create_stag(iwdev);
  1687. if (!stag) {
  1688. err = -ENOMEM;
  1689. goto error;
  1690. }
  1691. iwmr->stag = stag;
  1692. iwmr->ibmr.rkey = stag;
  1693. iwmr->ibmr.lkey = stag;
  1694. err = i40iw_hwreg_mr(iwdev, iwmr, access);
  1695. if (err) {
  1696. i40iw_free_stag(iwdev, stag);
  1697. goto error;
  1698. }
  1699. break;
  1700. default:
  1701. goto error;
  1702. }
  1703. iwmr->type = req.reg_type;
  1704. if (req.reg_type == IW_MEMREG_TYPE_MEM)
  1705. i40iw_add_pdusecount(iwpd);
  1706. return &iwmr->ibmr;
  1707. error:
  1708. if (palloc->level != I40IW_LEVEL_0 && iwpbl->pbl_allocated)
  1709. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1710. ib_umem_release(region);
  1711. kfree(iwmr);
  1712. return ERR_PTR(err);
  1713. }
  1714. /**
  1715. * i40iw_reg_phys_mr - register kernel physical memory
  1716. * @pd: ibpd pointer
  1717. * @addr: physical address of memory to register
  1718. * @size: size of memory to register
  1719. * @acc: Access rights
  1720. * @iova_start: start of virtual address for physical buffers
  1721. */
  1722. struct ib_mr *i40iw_reg_phys_mr(struct ib_pd *pd,
  1723. u64 addr,
  1724. u64 size,
  1725. int acc,
  1726. u64 *iova_start)
  1727. {
  1728. struct i40iw_pd *iwpd = to_iwpd(pd);
  1729. struct i40iw_device *iwdev = to_iwdev(pd->device);
  1730. struct i40iw_pbl *iwpbl;
  1731. struct i40iw_mr *iwmr;
  1732. enum i40iw_status_code status;
  1733. u32 stag;
  1734. u16 access = I40IW_ACCESS_FLAGS_LOCALREAD;
  1735. int ret;
  1736. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  1737. if (!iwmr)
  1738. return ERR_PTR(-ENOMEM);
  1739. iwmr->ibmr.pd = pd;
  1740. iwmr->ibmr.device = pd->device;
  1741. iwpbl = &iwmr->iwpbl;
  1742. iwpbl->iwmr = iwmr;
  1743. iwmr->type = IW_MEMREG_TYPE_MEM;
  1744. iwpbl->user_base = *iova_start;
  1745. stag = i40iw_create_stag(iwdev);
  1746. if (!stag) {
  1747. ret = -EOVERFLOW;
  1748. goto err;
  1749. }
  1750. access |= i40iw_get_user_access(acc);
  1751. iwmr->stag = stag;
  1752. iwmr->ibmr.rkey = stag;
  1753. iwmr->ibmr.lkey = stag;
  1754. iwmr->page_cnt = 1;
  1755. iwmr->pgaddrmem[0] = addr;
  1756. iwmr->length = size;
  1757. status = i40iw_hwreg_mr(iwdev, iwmr, access);
  1758. if (status) {
  1759. i40iw_free_stag(iwdev, stag);
  1760. ret = -ENOMEM;
  1761. goto err;
  1762. }
  1763. i40iw_add_pdusecount(iwpd);
  1764. return &iwmr->ibmr;
  1765. err:
  1766. kfree(iwmr);
  1767. return ERR_PTR(ret);
  1768. }
  1769. /**
  1770. * i40iw_get_dma_mr - register physical mem
  1771. * @pd: ptr of pd
  1772. * @acc: access for memory
  1773. */
  1774. static struct ib_mr *i40iw_get_dma_mr(struct ib_pd *pd, int acc)
  1775. {
  1776. u64 kva = 0;
  1777. return i40iw_reg_phys_mr(pd, 0, 0, acc, &kva);
  1778. }
  1779. /**
  1780. * i40iw_del_mem_list - Deleting pbl list entries for CQ/QP
  1781. * @iwmr: iwmr for IB's user page addresses
  1782. * @ucontext: ptr to user context
  1783. */
  1784. static void i40iw_del_memlist(struct i40iw_mr *iwmr,
  1785. struct i40iw_ucontext *ucontext)
  1786. {
  1787. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1788. unsigned long flags;
  1789. switch (iwmr->type) {
  1790. case IW_MEMREG_TYPE_CQ:
  1791. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1792. if (iwpbl->on_list) {
  1793. iwpbl->on_list = false;
  1794. list_del(&iwpbl->list);
  1795. }
  1796. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1797. break;
  1798. case IW_MEMREG_TYPE_QP:
  1799. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  1800. if (iwpbl->on_list) {
  1801. iwpbl->on_list = false;
  1802. list_del(&iwpbl->list);
  1803. }
  1804. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  1805. break;
  1806. default:
  1807. break;
  1808. }
  1809. }
  1810. /**
  1811. * i40iw_dereg_mr - deregister mr
  1812. * @ib_mr: mr ptr for dereg
  1813. */
  1814. static int i40iw_dereg_mr(struct ib_mr *ib_mr)
  1815. {
  1816. struct ib_pd *ibpd = ib_mr->pd;
  1817. struct i40iw_pd *iwpd = to_iwpd(ibpd);
  1818. struct i40iw_mr *iwmr = to_iwmr(ib_mr);
  1819. struct i40iw_device *iwdev = to_iwdev(ib_mr->device);
  1820. enum i40iw_status_code status;
  1821. struct i40iw_dealloc_stag_info *info;
  1822. struct i40iw_pbl *iwpbl = &iwmr->iwpbl;
  1823. struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
  1824. struct i40iw_cqp_request *cqp_request;
  1825. struct cqp_commands_info *cqp_info;
  1826. u32 stag_idx;
  1827. if (iwmr->region)
  1828. ib_umem_release(iwmr->region);
  1829. if (iwmr->type != IW_MEMREG_TYPE_MEM) {
  1830. if (ibpd->uobject) {
  1831. struct i40iw_ucontext *ucontext;
  1832. ucontext = to_ucontext(ibpd->uobject->context);
  1833. i40iw_del_memlist(iwmr, ucontext);
  1834. }
  1835. if (iwpbl->pbl_allocated && iwmr->type != IW_MEMREG_TYPE_QP)
  1836. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1837. kfree(iwmr);
  1838. return 0;
  1839. }
  1840. cqp_request = i40iw_get_cqp_request(&iwdev->cqp, true);
  1841. if (!cqp_request)
  1842. return -ENOMEM;
  1843. cqp_info = &cqp_request->info;
  1844. info = &cqp_info->in.u.dealloc_stag.info;
  1845. memset(info, 0, sizeof(*info));
  1846. info->pd_id = cpu_to_le32(iwpd->sc_pd.pd_id & 0x00007fff);
  1847. info->stag_idx = RS_64_1(ib_mr->rkey, I40IW_CQPSQ_STAG_IDX_SHIFT);
  1848. stag_idx = info->stag_idx;
  1849. info->mr = true;
  1850. if (iwpbl->pbl_allocated)
  1851. info->dealloc_pbl = true;
  1852. cqp_info->cqp_cmd = OP_DEALLOC_STAG;
  1853. cqp_info->post_sq = 1;
  1854. cqp_info->in.u.dealloc_stag.dev = &iwdev->sc_dev;
  1855. cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
  1856. status = i40iw_handle_cqp_op(iwdev, cqp_request);
  1857. if (status)
  1858. i40iw_pr_err("CQP-OP dealloc failed for stag_idx = 0x%x\n", stag_idx);
  1859. i40iw_rem_pdusecount(iwpd, iwdev);
  1860. i40iw_free_stag(iwdev, iwmr->stag);
  1861. if (iwpbl->pbl_allocated)
  1862. i40iw_free_pble(iwdev->pble_rsrc, palloc);
  1863. kfree(iwmr);
  1864. return 0;
  1865. }
  1866. /**
  1867. * i40iw_show_rev
  1868. */
  1869. static ssize_t i40iw_show_rev(struct device *dev,
  1870. struct device_attribute *attr, char *buf)
  1871. {
  1872. struct i40iw_ib_device *iwibdev = container_of(dev,
  1873. struct i40iw_ib_device,
  1874. ibdev.dev);
  1875. u32 hw_rev = iwibdev->iwdev->sc_dev.hw_rev;
  1876. return sprintf(buf, "%x\n", hw_rev);
  1877. }
  1878. /**
  1879. * i40iw_show_hca
  1880. */
  1881. static ssize_t i40iw_show_hca(struct device *dev,
  1882. struct device_attribute *attr, char *buf)
  1883. {
  1884. return sprintf(buf, "I40IW\n");
  1885. }
  1886. /**
  1887. * i40iw_show_board
  1888. */
  1889. static ssize_t i40iw_show_board(struct device *dev,
  1890. struct device_attribute *attr,
  1891. char *buf)
  1892. {
  1893. return sprintf(buf, "%.*s\n", 32, "I40IW Board ID");
  1894. }
  1895. static DEVICE_ATTR(hw_rev, S_IRUGO, i40iw_show_rev, NULL);
  1896. static DEVICE_ATTR(hca_type, S_IRUGO, i40iw_show_hca, NULL);
  1897. static DEVICE_ATTR(board_id, S_IRUGO, i40iw_show_board, NULL);
  1898. static struct device_attribute *i40iw_dev_attributes[] = {
  1899. &dev_attr_hw_rev,
  1900. &dev_attr_hca_type,
  1901. &dev_attr_board_id
  1902. };
  1903. /**
  1904. * i40iw_copy_sg_list - copy sg list for qp
  1905. * @sg_list: copied into sg_list
  1906. * @sgl: copy from sgl
  1907. * @num_sges: count of sg entries
  1908. */
  1909. static void i40iw_copy_sg_list(struct i40iw_sge *sg_list, struct ib_sge *sgl, int num_sges)
  1910. {
  1911. unsigned int i;
  1912. for (i = 0; (i < num_sges) && (i < I40IW_MAX_WQ_FRAGMENT_COUNT); i++) {
  1913. sg_list[i].tag_off = sgl[i].addr;
  1914. sg_list[i].len = sgl[i].length;
  1915. sg_list[i].stag = sgl[i].lkey;
  1916. }
  1917. }
  1918. /**
  1919. * i40iw_post_send - kernel application wr
  1920. * @ibqp: qp ptr for wr
  1921. * @ib_wr: work request ptr
  1922. * @bad_wr: return of bad wr if err
  1923. */
  1924. static int i40iw_post_send(struct ib_qp *ibqp,
  1925. const struct ib_send_wr *ib_wr,
  1926. const struct ib_send_wr **bad_wr)
  1927. {
  1928. struct i40iw_qp *iwqp;
  1929. struct i40iw_qp_uk *ukqp;
  1930. struct i40iw_post_sq_info info;
  1931. enum i40iw_status_code ret;
  1932. int err = 0;
  1933. unsigned long flags;
  1934. bool inv_stag;
  1935. iwqp = (struct i40iw_qp *)ibqp;
  1936. ukqp = &iwqp->sc_qp.qp_uk;
  1937. spin_lock_irqsave(&iwqp->lock, flags);
  1938. if (iwqp->flush_issued) {
  1939. err = -EINVAL;
  1940. goto out;
  1941. }
  1942. while (ib_wr) {
  1943. inv_stag = false;
  1944. memset(&info, 0, sizeof(info));
  1945. info.wr_id = (u64)(ib_wr->wr_id);
  1946. if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
  1947. info.signaled = true;
  1948. if (ib_wr->send_flags & IB_SEND_FENCE)
  1949. info.read_fence = true;
  1950. switch (ib_wr->opcode) {
  1951. case IB_WR_SEND:
  1952. /* fall-through */
  1953. case IB_WR_SEND_WITH_INV:
  1954. if (ib_wr->opcode == IB_WR_SEND) {
  1955. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  1956. info.op_type = I40IW_OP_TYPE_SEND_SOL;
  1957. else
  1958. info.op_type = I40IW_OP_TYPE_SEND;
  1959. } else {
  1960. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  1961. info.op_type = I40IW_OP_TYPE_SEND_SOL_INV;
  1962. else
  1963. info.op_type = I40IW_OP_TYPE_SEND_INV;
  1964. }
  1965. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1966. info.op.inline_send.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1967. info.op.inline_send.len = ib_wr->sg_list[0].length;
  1968. ret = ukqp->ops.iw_inline_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
  1969. } else {
  1970. info.op.send.num_sges = ib_wr->num_sge;
  1971. info.op.send.sg_list = (struct i40iw_sge *)ib_wr->sg_list;
  1972. ret = ukqp->ops.iw_send(ukqp, &info, ib_wr->ex.invalidate_rkey, false);
  1973. }
  1974. if (ret) {
  1975. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1976. err = -ENOMEM;
  1977. else
  1978. err = -EINVAL;
  1979. }
  1980. break;
  1981. case IB_WR_RDMA_WRITE:
  1982. info.op_type = I40IW_OP_TYPE_RDMA_WRITE;
  1983. if (ib_wr->send_flags & IB_SEND_INLINE) {
  1984. info.op.inline_rdma_write.data = (void *)(unsigned long)ib_wr->sg_list[0].addr;
  1985. info.op.inline_rdma_write.len = ib_wr->sg_list[0].length;
  1986. info.op.inline_rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1987. info.op.inline_rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1988. ret = ukqp->ops.iw_inline_rdma_write(ukqp, &info, false);
  1989. } else {
  1990. info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list;
  1991. info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
  1992. info.op.rdma_write.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  1993. info.op.rdma_write.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  1994. ret = ukqp->ops.iw_rdma_write(ukqp, &info, false);
  1995. }
  1996. if (ret) {
  1997. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  1998. err = -ENOMEM;
  1999. else
  2000. err = -EINVAL;
  2001. }
  2002. break;
  2003. case IB_WR_RDMA_READ_WITH_INV:
  2004. inv_stag = true;
  2005. /* fall-through*/
  2006. case IB_WR_RDMA_READ:
  2007. if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {
  2008. err = -EINVAL;
  2009. break;
  2010. }
  2011. info.op_type = I40IW_OP_TYPE_RDMA_READ;
  2012. info.op.rdma_read.rem_addr.tag_off = rdma_wr(ib_wr)->remote_addr;
  2013. info.op.rdma_read.rem_addr.stag = rdma_wr(ib_wr)->rkey;
  2014. info.op.rdma_read.lo_addr.tag_off = ib_wr->sg_list->addr;
  2015. info.op.rdma_read.lo_addr.stag = ib_wr->sg_list->lkey;
  2016. info.op.rdma_read.lo_addr.len = ib_wr->sg_list->length;
  2017. ret = ukqp->ops.iw_rdma_read(ukqp, &info, inv_stag, false);
  2018. if (ret) {
  2019. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  2020. err = -ENOMEM;
  2021. else
  2022. err = -EINVAL;
  2023. }
  2024. break;
  2025. case IB_WR_LOCAL_INV:
  2026. info.op_type = I40IW_OP_TYPE_INV_STAG;
  2027. info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
  2028. ret = ukqp->ops.iw_stag_local_invalidate(ukqp, &info, true);
  2029. if (ret)
  2030. err = -ENOMEM;
  2031. break;
  2032. case IB_WR_REG_MR:
  2033. {
  2034. struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
  2035. int flags = reg_wr(ib_wr)->access;
  2036. struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
  2037. struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev;
  2038. struct i40iw_fast_reg_stag_info info;
  2039. memset(&info, 0, sizeof(info));
  2040. info.access_rights = I40IW_ACCESS_FLAGS_LOCALREAD;
  2041. info.access_rights |= i40iw_get_user_access(flags);
  2042. info.stag_key = reg_wr(ib_wr)->key & 0xff;
  2043. info.stag_idx = reg_wr(ib_wr)->key >> 8;
  2044. info.page_size = reg_wr(ib_wr)->mr->page_size;
  2045. info.wr_id = ib_wr->wr_id;
  2046. info.addr_type = I40IW_ADDR_TYPE_VA_BASED;
  2047. info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
  2048. info.total_len = iwmr->ibmr.length;
  2049. info.reg_addr_pa = *(u64 *)palloc->level1.addr;
  2050. info.first_pm_pbl_index = palloc->level1.idx;
  2051. info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
  2052. info.signaled = ib_wr->send_flags & IB_SEND_SIGNALED;
  2053. if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR)
  2054. info.chunk_size = 1;
  2055. ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true);
  2056. if (ret)
  2057. err = -ENOMEM;
  2058. break;
  2059. }
  2060. default:
  2061. err = -EINVAL;
  2062. i40iw_pr_err(" upost_send bad opcode = 0x%x\n",
  2063. ib_wr->opcode);
  2064. break;
  2065. }
  2066. if (err)
  2067. break;
  2068. ib_wr = ib_wr->next;
  2069. }
  2070. out:
  2071. if (err)
  2072. *bad_wr = ib_wr;
  2073. else
  2074. ukqp->ops.iw_qp_post_wr(ukqp);
  2075. spin_unlock_irqrestore(&iwqp->lock, flags);
  2076. return err;
  2077. }
  2078. /**
  2079. * i40iw_post_recv - post receive wr for kernel application
  2080. * @ibqp: ib qp pointer
  2081. * @ib_wr: work request for receive
  2082. * @bad_wr: bad wr caused an error
  2083. */
  2084. static int i40iw_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *ib_wr,
  2085. const struct ib_recv_wr **bad_wr)
  2086. {
  2087. struct i40iw_qp *iwqp;
  2088. struct i40iw_qp_uk *ukqp;
  2089. struct i40iw_post_rq_info post_recv;
  2090. struct i40iw_sge sg_list[I40IW_MAX_WQ_FRAGMENT_COUNT];
  2091. enum i40iw_status_code ret = 0;
  2092. unsigned long flags;
  2093. int err = 0;
  2094. iwqp = (struct i40iw_qp *)ibqp;
  2095. ukqp = &iwqp->sc_qp.qp_uk;
  2096. memset(&post_recv, 0, sizeof(post_recv));
  2097. spin_lock_irqsave(&iwqp->lock, flags);
  2098. if (iwqp->flush_issued) {
  2099. err = -EINVAL;
  2100. goto out;
  2101. }
  2102. while (ib_wr) {
  2103. post_recv.num_sges = ib_wr->num_sge;
  2104. post_recv.wr_id = ib_wr->wr_id;
  2105. i40iw_copy_sg_list(sg_list, ib_wr->sg_list, ib_wr->num_sge);
  2106. post_recv.sg_list = sg_list;
  2107. ret = ukqp->ops.iw_post_receive(ukqp, &post_recv);
  2108. if (ret) {
  2109. i40iw_pr_err(" post_recv err %d\n", ret);
  2110. if (ret == I40IW_ERR_QP_TOOMANY_WRS_POSTED)
  2111. err = -ENOMEM;
  2112. else
  2113. err = -EINVAL;
  2114. *bad_wr = ib_wr;
  2115. goto out;
  2116. }
  2117. ib_wr = ib_wr->next;
  2118. }
  2119. out:
  2120. spin_unlock_irqrestore(&iwqp->lock, flags);
  2121. return err;
  2122. }
  2123. /**
  2124. * i40iw_poll_cq - poll cq for completion (kernel apps)
  2125. * @ibcq: cq to poll
  2126. * @num_entries: number of entries to poll
  2127. * @entry: wr of entry completed
  2128. */
  2129. static int i40iw_poll_cq(struct ib_cq *ibcq,
  2130. int num_entries,
  2131. struct ib_wc *entry)
  2132. {
  2133. struct i40iw_cq *iwcq;
  2134. int cqe_count = 0;
  2135. struct i40iw_cq_poll_info cq_poll_info;
  2136. enum i40iw_status_code ret;
  2137. struct i40iw_cq_uk *ukcq;
  2138. struct i40iw_sc_qp *qp;
  2139. struct i40iw_qp *iwqp;
  2140. unsigned long flags;
  2141. iwcq = (struct i40iw_cq *)ibcq;
  2142. ukcq = &iwcq->sc_cq.cq_uk;
  2143. spin_lock_irqsave(&iwcq->lock, flags);
  2144. while (cqe_count < num_entries) {
  2145. ret = ukcq->ops.iw_cq_poll_completion(ukcq, &cq_poll_info);
  2146. if (ret == I40IW_ERR_QUEUE_EMPTY) {
  2147. break;
  2148. } else if (ret == I40IW_ERR_QUEUE_DESTROYED) {
  2149. continue;
  2150. } else if (ret) {
  2151. if (!cqe_count)
  2152. cqe_count = -1;
  2153. break;
  2154. }
  2155. entry->wc_flags = 0;
  2156. entry->wr_id = cq_poll_info.wr_id;
  2157. if (cq_poll_info.error) {
  2158. entry->status = IB_WC_WR_FLUSH_ERR;
  2159. entry->vendor_err = cq_poll_info.major_err << 16 | cq_poll_info.minor_err;
  2160. } else {
  2161. entry->status = IB_WC_SUCCESS;
  2162. }
  2163. switch (cq_poll_info.op_type) {
  2164. case I40IW_OP_TYPE_RDMA_WRITE:
  2165. entry->opcode = IB_WC_RDMA_WRITE;
  2166. break;
  2167. case I40IW_OP_TYPE_RDMA_READ_INV_STAG:
  2168. case I40IW_OP_TYPE_RDMA_READ:
  2169. entry->opcode = IB_WC_RDMA_READ;
  2170. break;
  2171. case I40IW_OP_TYPE_SEND_SOL:
  2172. case I40IW_OP_TYPE_SEND_SOL_INV:
  2173. case I40IW_OP_TYPE_SEND_INV:
  2174. case I40IW_OP_TYPE_SEND:
  2175. entry->opcode = IB_WC_SEND;
  2176. break;
  2177. case I40IW_OP_TYPE_REC:
  2178. entry->opcode = IB_WC_RECV;
  2179. break;
  2180. default:
  2181. entry->opcode = IB_WC_RECV;
  2182. break;
  2183. }
  2184. entry->ex.imm_data = 0;
  2185. qp = (struct i40iw_sc_qp *)cq_poll_info.qp_handle;
  2186. entry->qp = (struct ib_qp *)qp->back_qp;
  2187. entry->src_qp = cq_poll_info.qp_id;
  2188. iwqp = (struct i40iw_qp *)qp->back_qp;
  2189. if (iwqp->iwarp_state > I40IW_QP_STATE_RTS) {
  2190. if (!I40IW_RING_MORE_WORK(qp->qp_uk.sq_ring))
  2191. complete(&iwqp->sq_drained);
  2192. if (!I40IW_RING_MORE_WORK(qp->qp_uk.rq_ring))
  2193. complete(&iwqp->rq_drained);
  2194. }
  2195. entry->byte_len = cq_poll_info.bytes_xfered;
  2196. entry++;
  2197. cqe_count++;
  2198. }
  2199. spin_unlock_irqrestore(&iwcq->lock, flags);
  2200. return cqe_count;
  2201. }
  2202. /**
  2203. * i40iw_req_notify_cq - arm cq kernel application
  2204. * @ibcq: cq to arm
  2205. * @notify_flags: notofication flags
  2206. */
  2207. static int i40iw_req_notify_cq(struct ib_cq *ibcq,
  2208. enum ib_cq_notify_flags notify_flags)
  2209. {
  2210. struct i40iw_cq *iwcq;
  2211. struct i40iw_cq_uk *ukcq;
  2212. unsigned long flags;
  2213. enum i40iw_completion_notify cq_notify = IW_CQ_COMPL_EVENT;
  2214. iwcq = (struct i40iw_cq *)ibcq;
  2215. ukcq = &iwcq->sc_cq.cq_uk;
  2216. if (notify_flags == IB_CQ_SOLICITED)
  2217. cq_notify = IW_CQ_COMPL_SOLICITED;
  2218. spin_lock_irqsave(&iwcq->lock, flags);
  2219. ukcq->ops.iw_cq_request_notification(ukcq, cq_notify);
  2220. spin_unlock_irqrestore(&iwcq->lock, flags);
  2221. return 0;
  2222. }
  2223. /**
  2224. * i40iw_port_immutable - return port's immutable data
  2225. * @ibdev: ib dev struct
  2226. * @port_num: port number
  2227. * @immutable: immutable data for the port return
  2228. */
  2229. static int i40iw_port_immutable(struct ib_device *ibdev, u8 port_num,
  2230. struct ib_port_immutable *immutable)
  2231. {
  2232. struct ib_port_attr attr;
  2233. int err;
  2234. immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
  2235. err = ib_query_port(ibdev, port_num, &attr);
  2236. if (err)
  2237. return err;
  2238. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  2239. immutable->gid_tbl_len = attr.gid_tbl_len;
  2240. return 0;
  2241. }
  2242. static const char * const i40iw_hw_stat_names[] = {
  2243. // 32bit names
  2244. [I40IW_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards",
  2245. [I40IW_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts",
  2246. [I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes",
  2247. [I40IW_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards",
  2248. [I40IW_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts",
  2249. [I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes",
  2250. [I40IW_HW_STAT_INDEX_TCPRTXSEG] = "tcpRetransSegs",
  2251. [I40IW_HW_STAT_INDEX_TCPRXOPTERR] = "tcpInOptErrors",
  2252. [I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = "tcpInProtoErrors",
  2253. // 64bit names
  2254. [I40IW_HW_STAT_INDEX_IP4RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2255. "ip4InOctets",
  2256. [I40IW_HW_STAT_INDEX_IP4RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2257. "ip4InPkts",
  2258. [I40IW_HW_STAT_INDEX_IP4RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2259. "ip4InReasmRqd",
  2260. [I40IW_HW_STAT_INDEX_IP4RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2261. "ip4InMcastPkts",
  2262. [I40IW_HW_STAT_INDEX_IP4TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2263. "ip4OutOctets",
  2264. [I40IW_HW_STAT_INDEX_IP4TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2265. "ip4OutPkts",
  2266. [I40IW_HW_STAT_INDEX_IP4TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2267. "ip4OutSegRqd",
  2268. [I40IW_HW_STAT_INDEX_IP4TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2269. "ip4OutMcastPkts",
  2270. [I40IW_HW_STAT_INDEX_IP6RXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2271. "ip6InOctets",
  2272. [I40IW_HW_STAT_INDEX_IP6RXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2273. "ip6InPkts",
  2274. [I40IW_HW_STAT_INDEX_IP6RXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2275. "ip6InReasmRqd",
  2276. [I40IW_HW_STAT_INDEX_IP6RXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2277. "ip6InMcastPkts",
  2278. [I40IW_HW_STAT_INDEX_IP6TXOCTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2279. "ip6OutOctets",
  2280. [I40IW_HW_STAT_INDEX_IP6TXPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2281. "ip6OutPkts",
  2282. [I40IW_HW_STAT_INDEX_IP6TXFRAGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2283. "ip6OutSegRqd",
  2284. [I40IW_HW_STAT_INDEX_IP6TXMCPKTS + I40IW_HW_STAT_INDEX_MAX_32] =
  2285. "ip6OutMcastPkts",
  2286. [I40IW_HW_STAT_INDEX_TCPRXSEGS + I40IW_HW_STAT_INDEX_MAX_32] =
  2287. "tcpInSegs",
  2288. [I40IW_HW_STAT_INDEX_TCPTXSEG + I40IW_HW_STAT_INDEX_MAX_32] =
  2289. "tcpOutSegs",
  2290. [I40IW_HW_STAT_INDEX_RDMARXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2291. "iwInRdmaReads",
  2292. [I40IW_HW_STAT_INDEX_RDMARXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2293. "iwInRdmaSends",
  2294. [I40IW_HW_STAT_INDEX_RDMARXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
  2295. "iwInRdmaWrites",
  2296. [I40IW_HW_STAT_INDEX_RDMATXRDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2297. "iwOutRdmaReads",
  2298. [I40IW_HW_STAT_INDEX_RDMATXSNDS + I40IW_HW_STAT_INDEX_MAX_32] =
  2299. "iwOutRdmaSends",
  2300. [I40IW_HW_STAT_INDEX_RDMATXWRS + I40IW_HW_STAT_INDEX_MAX_32] =
  2301. "iwOutRdmaWrites",
  2302. [I40IW_HW_STAT_INDEX_RDMAVBND + I40IW_HW_STAT_INDEX_MAX_32] =
  2303. "iwRdmaBnd",
  2304. [I40IW_HW_STAT_INDEX_RDMAVINV + I40IW_HW_STAT_INDEX_MAX_32] =
  2305. "iwRdmaInv"
  2306. };
  2307. static void i40iw_get_dev_fw_str(struct ib_device *dev, char *str)
  2308. {
  2309. u32 firmware_version = I40IW_FW_VERSION;
  2310. snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u", firmware_version,
  2311. (firmware_version & 0x000000ff));
  2312. }
  2313. /**
  2314. * i40iw_alloc_hw_stats - Allocate a hw stats structure
  2315. * @ibdev: device pointer from stack
  2316. * @port_num: port number
  2317. */
  2318. static struct rdma_hw_stats *i40iw_alloc_hw_stats(struct ib_device *ibdev,
  2319. u8 port_num)
  2320. {
  2321. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2322. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  2323. int num_counters = I40IW_HW_STAT_INDEX_MAX_32 +
  2324. I40IW_HW_STAT_INDEX_MAX_64;
  2325. unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
  2326. BUILD_BUG_ON(ARRAY_SIZE(i40iw_hw_stat_names) !=
  2327. (I40IW_HW_STAT_INDEX_MAX_32 +
  2328. I40IW_HW_STAT_INDEX_MAX_64));
  2329. /*
  2330. * PFs get the default update lifespan, but VFs only update once
  2331. * per second
  2332. */
  2333. if (!dev->is_pf)
  2334. lifespan = 1000;
  2335. return rdma_alloc_hw_stats_struct(i40iw_hw_stat_names, num_counters,
  2336. lifespan);
  2337. }
  2338. /**
  2339. * i40iw_get_hw_stats - Populates the rdma_hw_stats structure
  2340. * @ibdev: device pointer from stack
  2341. * @stats: stats pointer from stack
  2342. * @port_num: port number
  2343. * @index: which hw counter the stack is requesting we update
  2344. */
  2345. static int i40iw_get_hw_stats(struct ib_device *ibdev,
  2346. struct rdma_hw_stats *stats,
  2347. u8 port_num, int index)
  2348. {
  2349. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2350. struct i40iw_sc_dev *dev = &iwdev->sc_dev;
  2351. struct i40iw_vsi_pestat *devstat = iwdev->vsi.pestat;
  2352. struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
  2353. if (dev->is_pf) {
  2354. i40iw_hw_stats_read_all(devstat, &devstat->hw_stats);
  2355. } else {
  2356. if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats))
  2357. return -ENOSYS;
  2358. }
  2359. memcpy(&stats->value[0], hw_stats, sizeof(*hw_stats));
  2360. return stats->num_counters;
  2361. }
  2362. /**
  2363. * i40iw_query_gid - Query port GID
  2364. * @ibdev: device pointer from stack
  2365. * @port: port number
  2366. * @index: Entry index
  2367. * @gid: Global ID
  2368. */
  2369. static int i40iw_query_gid(struct ib_device *ibdev,
  2370. u8 port,
  2371. int index,
  2372. union ib_gid *gid)
  2373. {
  2374. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2375. memset(gid->raw, 0, sizeof(gid->raw));
  2376. ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
  2377. return 0;
  2378. }
  2379. /**
  2380. * i40iw_query_pkey - Query partition key
  2381. * @ibdev: device pointer from stack
  2382. * @port: port number
  2383. * @index: index of pkey
  2384. * @pkey: pointer to store the pkey
  2385. */
  2386. static int i40iw_query_pkey(struct ib_device *ibdev,
  2387. u8 port,
  2388. u16 index,
  2389. u16 *pkey)
  2390. {
  2391. *pkey = 0;
  2392. return 0;
  2393. }
  2394. /**
  2395. * i40iw_get_vector_affinity - report IRQ affinity mask
  2396. * @ibdev: IB device
  2397. * @comp_vector: completion vector index
  2398. */
  2399. static const struct cpumask *i40iw_get_vector_affinity(struct ib_device *ibdev,
  2400. int comp_vector)
  2401. {
  2402. struct i40iw_device *iwdev = to_iwdev(ibdev);
  2403. struct i40iw_msix_vector *msix_vec;
  2404. if (iwdev->msix_shared)
  2405. msix_vec = &iwdev->iw_msixtbl[comp_vector];
  2406. else
  2407. msix_vec = &iwdev->iw_msixtbl[comp_vector + 1];
  2408. return irq_get_affinity_mask(msix_vec->irq);
  2409. }
  2410. /**
  2411. * i40iw_init_rdma_device - initialization of iwarp device
  2412. * @iwdev: iwarp device
  2413. */
  2414. static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev)
  2415. {
  2416. struct i40iw_ib_device *iwibdev;
  2417. struct net_device *netdev = iwdev->netdev;
  2418. struct pci_dev *pcidev = (struct pci_dev *)iwdev->hw.dev_context;
  2419. iwibdev = (struct i40iw_ib_device *)ib_alloc_device(sizeof(*iwibdev));
  2420. if (!iwibdev) {
  2421. i40iw_pr_err("iwdev == NULL\n");
  2422. return NULL;
  2423. }
  2424. strlcpy(iwibdev->ibdev.name, "i40iw%d", IB_DEVICE_NAME_MAX);
  2425. iwibdev->ibdev.owner = THIS_MODULE;
  2426. iwdev->iwibdev = iwibdev;
  2427. iwibdev->iwdev = iwdev;
  2428. iwibdev->ibdev.node_type = RDMA_NODE_RNIC;
  2429. ether_addr_copy((u8 *)&iwibdev->ibdev.node_guid, netdev->dev_addr);
  2430. iwibdev->ibdev.uverbs_cmd_mask =
  2431. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  2432. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  2433. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  2434. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  2435. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  2436. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  2437. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  2438. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  2439. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  2440. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  2441. (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
  2442. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  2443. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  2444. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  2445. (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
  2446. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  2447. (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
  2448. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  2449. (1ull << IB_USER_VERBS_CMD_POST_RECV) |
  2450. (1ull << IB_USER_VERBS_CMD_POST_SEND);
  2451. iwibdev->ibdev.phys_port_cnt = 1;
  2452. iwibdev->ibdev.num_comp_vectors = iwdev->ceqs_count;
  2453. iwibdev->ibdev.dev.parent = &pcidev->dev;
  2454. iwibdev->ibdev.query_port = i40iw_query_port;
  2455. iwibdev->ibdev.query_pkey = i40iw_query_pkey;
  2456. iwibdev->ibdev.query_gid = i40iw_query_gid;
  2457. iwibdev->ibdev.alloc_ucontext = i40iw_alloc_ucontext;
  2458. iwibdev->ibdev.dealloc_ucontext = i40iw_dealloc_ucontext;
  2459. iwibdev->ibdev.mmap = i40iw_mmap;
  2460. iwibdev->ibdev.alloc_pd = i40iw_alloc_pd;
  2461. iwibdev->ibdev.dealloc_pd = i40iw_dealloc_pd;
  2462. iwibdev->ibdev.create_qp = i40iw_create_qp;
  2463. iwibdev->ibdev.modify_qp = i40iw_modify_qp;
  2464. iwibdev->ibdev.query_qp = i40iw_query_qp;
  2465. iwibdev->ibdev.destroy_qp = i40iw_destroy_qp;
  2466. iwibdev->ibdev.create_cq = i40iw_create_cq;
  2467. iwibdev->ibdev.destroy_cq = i40iw_destroy_cq;
  2468. iwibdev->ibdev.get_dma_mr = i40iw_get_dma_mr;
  2469. iwibdev->ibdev.reg_user_mr = i40iw_reg_user_mr;
  2470. iwibdev->ibdev.dereg_mr = i40iw_dereg_mr;
  2471. iwibdev->ibdev.alloc_hw_stats = i40iw_alloc_hw_stats;
  2472. iwibdev->ibdev.get_hw_stats = i40iw_get_hw_stats;
  2473. iwibdev->ibdev.query_device = i40iw_query_device;
  2474. iwibdev->ibdev.drain_sq = i40iw_drain_sq;
  2475. iwibdev->ibdev.drain_rq = i40iw_drain_rq;
  2476. iwibdev->ibdev.alloc_mr = i40iw_alloc_mr;
  2477. iwibdev->ibdev.map_mr_sg = i40iw_map_mr_sg;
  2478. iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL);
  2479. if (!iwibdev->ibdev.iwcm) {
  2480. ib_dealloc_device(&iwibdev->ibdev);
  2481. return NULL;
  2482. }
  2483. iwibdev->ibdev.iwcm->add_ref = i40iw_add_ref;
  2484. iwibdev->ibdev.iwcm->rem_ref = i40iw_rem_ref;
  2485. iwibdev->ibdev.iwcm->get_qp = i40iw_get_qp;
  2486. iwibdev->ibdev.iwcm->connect = i40iw_connect;
  2487. iwibdev->ibdev.iwcm->accept = i40iw_accept;
  2488. iwibdev->ibdev.iwcm->reject = i40iw_reject;
  2489. iwibdev->ibdev.iwcm->create_listen = i40iw_create_listen;
  2490. iwibdev->ibdev.iwcm->destroy_listen = i40iw_destroy_listen;
  2491. memcpy(iwibdev->ibdev.iwcm->ifname, netdev->name,
  2492. sizeof(iwibdev->ibdev.iwcm->ifname));
  2493. iwibdev->ibdev.get_port_immutable = i40iw_port_immutable;
  2494. iwibdev->ibdev.get_dev_fw_str = i40iw_get_dev_fw_str;
  2495. iwibdev->ibdev.poll_cq = i40iw_poll_cq;
  2496. iwibdev->ibdev.req_notify_cq = i40iw_req_notify_cq;
  2497. iwibdev->ibdev.post_send = i40iw_post_send;
  2498. iwibdev->ibdev.post_recv = i40iw_post_recv;
  2499. iwibdev->ibdev.get_vector_affinity = i40iw_get_vector_affinity;
  2500. return iwibdev;
  2501. }
  2502. /**
  2503. * i40iw_port_ibevent - indicate port event
  2504. * @iwdev: iwarp device
  2505. */
  2506. void i40iw_port_ibevent(struct i40iw_device *iwdev)
  2507. {
  2508. struct i40iw_ib_device *iwibdev = iwdev->iwibdev;
  2509. struct ib_event event;
  2510. event.device = &iwibdev->ibdev;
  2511. event.element.port_num = 1;
  2512. event.event = iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2513. ib_dispatch_event(&event);
  2514. }
  2515. /**
  2516. * i40iw_unregister_rdma_device - unregister of iwarp from IB
  2517. * @iwibdev: rdma device ptr
  2518. */
  2519. static void i40iw_unregister_rdma_device(struct i40iw_ib_device *iwibdev)
  2520. {
  2521. int i;
  2522. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i)
  2523. device_remove_file(&iwibdev->ibdev.dev,
  2524. i40iw_dev_attributes[i]);
  2525. ib_unregister_device(&iwibdev->ibdev);
  2526. }
  2527. /**
  2528. * i40iw_destroy_rdma_device - destroy rdma device and free resources
  2529. * @iwibdev: IB device ptr
  2530. */
  2531. void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
  2532. {
  2533. if (!iwibdev)
  2534. return;
  2535. i40iw_unregister_rdma_device(iwibdev);
  2536. kfree(iwibdev->ibdev.iwcm);
  2537. iwibdev->ibdev.iwcm = NULL;
  2538. wait_event_timeout(iwibdev->iwdev->close_wq,
  2539. !atomic64_read(&iwibdev->iwdev->use_count),
  2540. I40IW_EVENT_TIMEOUT);
  2541. ib_dealloc_device(&iwibdev->ibdev);
  2542. }
  2543. /**
  2544. * i40iw_register_rdma_device - register iwarp device to IB
  2545. * @iwdev: iwarp device
  2546. */
  2547. int i40iw_register_rdma_device(struct i40iw_device *iwdev)
  2548. {
  2549. int i, ret;
  2550. struct i40iw_ib_device *iwibdev;
  2551. iwdev->iwibdev = i40iw_init_rdma_device(iwdev);
  2552. if (!iwdev->iwibdev)
  2553. return -ENOMEM;
  2554. iwibdev = iwdev->iwibdev;
  2555. iwibdev->ibdev.driver_id = RDMA_DRIVER_I40IW;
  2556. ret = ib_register_device(&iwibdev->ibdev, NULL);
  2557. if (ret)
  2558. goto error;
  2559. for (i = 0; i < ARRAY_SIZE(i40iw_dev_attributes); ++i) {
  2560. ret =
  2561. device_create_file(&iwibdev->ibdev.dev,
  2562. i40iw_dev_attributes[i]);
  2563. if (ret) {
  2564. while (i > 0) {
  2565. i--;
  2566. device_remove_file(&iwibdev->ibdev.dev, i40iw_dev_attributes[i]);
  2567. }
  2568. ib_unregister_device(&iwibdev->ibdev);
  2569. goto error;
  2570. }
  2571. }
  2572. return 0;
  2573. error:
  2574. kfree(iwdev->iwibdev->ibdev.iwcm);
  2575. iwdev->iwibdev->ibdev.iwcm = NULL;
  2576. ib_dealloc_device(&iwdev->iwibdev->ibdev);
  2577. return ret;
  2578. }