pvrdma_main.c 32 KB

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  1. /*
  2. * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of EITHER the GNU General Public License
  6. * version 2 as published by the Free Software Foundation or the BSD
  7. * 2-Clause License. This program is distributed in the hope that it
  8. * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
  9. * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
  10. * See the GNU General Public License version 2 for more details at
  11. * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program available in the file COPYING in the main
  15. * directory of this source tree.
  16. *
  17. * The BSD 2-Clause License
  18. *
  19. * Redistribution and use in source and binary forms, with or
  20. * without modification, are permitted provided that the following
  21. * conditions are met:
  22. *
  23. * - Redistributions of source code must retain the above
  24. * copyright notice, this list of conditions and the following
  25. * disclaimer.
  26. *
  27. * - Redistributions in binary form must reproduce the above
  28. * copyright notice, this list of conditions and the following
  29. * disclaimer in the documentation and/or other materials
  30. * provided with the distribution.
  31. *
  32. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  33. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  34. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  35. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  36. * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  37. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  38. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  39. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  40. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  41. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  42. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  43. * OF THE POSSIBILITY OF SUCH DAMAGE.
  44. */
  45. #include <linux/errno.h>
  46. #include <linux/inetdevice.h>
  47. #include <linux/init.h>
  48. #include <linux/module.h>
  49. #include <linux/slab.h>
  50. #include <rdma/ib_addr.h>
  51. #include <rdma/ib_smi.h>
  52. #include <rdma/ib_user_verbs.h>
  53. #include <net/addrconf.h>
  54. #include "pvrdma.h"
  55. #define DRV_NAME "vmw_pvrdma"
  56. #define DRV_VERSION "1.0.1.0-k"
  57. static DEFINE_MUTEX(pvrdma_device_list_lock);
  58. static LIST_HEAD(pvrdma_device_list);
  59. static struct workqueue_struct *event_wq;
  60. static int pvrdma_add_gid(const struct ib_gid_attr *attr, void **context);
  61. static int pvrdma_del_gid(const struct ib_gid_attr *attr, void **context);
  62. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  63. char *buf)
  64. {
  65. return sprintf(buf, "VMW_PVRDMA-%s\n", DRV_VERSION);
  66. }
  67. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  68. char *buf)
  69. {
  70. return sprintf(buf, "%d\n", PVRDMA_REV_ID);
  71. }
  72. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  73. char *buf)
  74. {
  75. return sprintf(buf, "%d\n", PVRDMA_BOARD_ID);
  76. }
  77. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  78. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  79. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  80. static struct device_attribute *pvrdma_class_attributes[] = {
  81. &dev_attr_hw_rev,
  82. &dev_attr_hca_type,
  83. &dev_attr_board_id
  84. };
  85. static void pvrdma_get_fw_ver_str(struct ib_device *device, char *str)
  86. {
  87. struct pvrdma_dev *dev =
  88. container_of(device, struct pvrdma_dev, ib_dev);
  89. snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d\n",
  90. (int) (dev->dsr->caps.fw_ver >> 32),
  91. (int) (dev->dsr->caps.fw_ver >> 16) & 0xffff,
  92. (int) dev->dsr->caps.fw_ver & 0xffff);
  93. }
  94. static int pvrdma_init_device(struct pvrdma_dev *dev)
  95. {
  96. /* Initialize some device related stuff */
  97. spin_lock_init(&dev->cmd_lock);
  98. sema_init(&dev->cmd_sema, 1);
  99. atomic_set(&dev->num_qps, 0);
  100. atomic_set(&dev->num_srqs, 0);
  101. atomic_set(&dev->num_cqs, 0);
  102. atomic_set(&dev->num_pds, 0);
  103. atomic_set(&dev->num_ahs, 0);
  104. return 0;
  105. }
  106. static int pvrdma_port_immutable(struct ib_device *ibdev, u8 port_num,
  107. struct ib_port_immutable *immutable)
  108. {
  109. struct pvrdma_dev *dev = to_vdev(ibdev);
  110. struct ib_port_attr attr;
  111. int err;
  112. if (dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1)
  113. immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE;
  114. else if (dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V2)
  115. immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  116. err = ib_query_port(ibdev, port_num, &attr);
  117. if (err)
  118. return err;
  119. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  120. immutable->gid_tbl_len = attr.gid_tbl_len;
  121. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  122. return 0;
  123. }
  124. static struct net_device *pvrdma_get_netdev(struct ib_device *ibdev,
  125. u8 port_num)
  126. {
  127. struct net_device *netdev;
  128. struct pvrdma_dev *dev = to_vdev(ibdev);
  129. if (port_num != 1)
  130. return NULL;
  131. rcu_read_lock();
  132. netdev = dev->netdev;
  133. if (netdev)
  134. dev_hold(netdev);
  135. rcu_read_unlock();
  136. return netdev;
  137. }
  138. static int pvrdma_register_device(struct pvrdma_dev *dev)
  139. {
  140. int ret = -1;
  141. int i = 0;
  142. strlcpy(dev->ib_dev.name, "vmw_pvrdma%d", IB_DEVICE_NAME_MAX);
  143. dev->ib_dev.node_guid = dev->dsr->caps.node_guid;
  144. dev->sys_image_guid = dev->dsr->caps.sys_image_guid;
  145. dev->flags = 0;
  146. dev->ib_dev.owner = THIS_MODULE;
  147. dev->ib_dev.num_comp_vectors = 1;
  148. dev->ib_dev.dev.parent = &dev->pdev->dev;
  149. dev->ib_dev.uverbs_abi_ver = PVRDMA_UVERBS_ABI_VERSION;
  150. dev->ib_dev.uverbs_cmd_mask =
  151. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  152. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  153. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  154. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  155. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  156. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  157. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  158. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  159. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  160. (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
  161. (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
  162. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  163. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  164. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  165. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  166. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  167. (1ull << IB_USER_VERBS_CMD_POST_SEND) |
  168. (1ull << IB_USER_VERBS_CMD_POST_RECV) |
  169. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  170. (1ull << IB_USER_VERBS_CMD_DESTROY_AH);
  171. dev->ib_dev.node_type = RDMA_NODE_IB_CA;
  172. dev->ib_dev.phys_port_cnt = dev->dsr->caps.phys_port_cnt;
  173. dev->ib_dev.query_device = pvrdma_query_device;
  174. dev->ib_dev.query_port = pvrdma_query_port;
  175. dev->ib_dev.query_gid = pvrdma_query_gid;
  176. dev->ib_dev.query_pkey = pvrdma_query_pkey;
  177. dev->ib_dev.modify_port = pvrdma_modify_port;
  178. dev->ib_dev.alloc_ucontext = pvrdma_alloc_ucontext;
  179. dev->ib_dev.dealloc_ucontext = pvrdma_dealloc_ucontext;
  180. dev->ib_dev.mmap = pvrdma_mmap;
  181. dev->ib_dev.alloc_pd = pvrdma_alloc_pd;
  182. dev->ib_dev.dealloc_pd = pvrdma_dealloc_pd;
  183. dev->ib_dev.create_ah = pvrdma_create_ah;
  184. dev->ib_dev.destroy_ah = pvrdma_destroy_ah;
  185. dev->ib_dev.create_qp = pvrdma_create_qp;
  186. dev->ib_dev.modify_qp = pvrdma_modify_qp;
  187. dev->ib_dev.query_qp = pvrdma_query_qp;
  188. dev->ib_dev.destroy_qp = pvrdma_destroy_qp;
  189. dev->ib_dev.post_send = pvrdma_post_send;
  190. dev->ib_dev.post_recv = pvrdma_post_recv;
  191. dev->ib_dev.create_cq = pvrdma_create_cq;
  192. dev->ib_dev.destroy_cq = pvrdma_destroy_cq;
  193. dev->ib_dev.poll_cq = pvrdma_poll_cq;
  194. dev->ib_dev.req_notify_cq = pvrdma_req_notify_cq;
  195. dev->ib_dev.get_dma_mr = pvrdma_get_dma_mr;
  196. dev->ib_dev.reg_user_mr = pvrdma_reg_user_mr;
  197. dev->ib_dev.dereg_mr = pvrdma_dereg_mr;
  198. dev->ib_dev.alloc_mr = pvrdma_alloc_mr;
  199. dev->ib_dev.map_mr_sg = pvrdma_map_mr_sg;
  200. dev->ib_dev.add_gid = pvrdma_add_gid;
  201. dev->ib_dev.del_gid = pvrdma_del_gid;
  202. dev->ib_dev.get_netdev = pvrdma_get_netdev;
  203. dev->ib_dev.get_port_immutable = pvrdma_port_immutable;
  204. dev->ib_dev.get_link_layer = pvrdma_port_link_layer;
  205. dev->ib_dev.get_dev_fw_str = pvrdma_get_fw_ver_str;
  206. mutex_init(&dev->port_mutex);
  207. spin_lock_init(&dev->desc_lock);
  208. dev->cq_tbl = kcalloc(dev->dsr->caps.max_cq, sizeof(struct pvrdma_cq *),
  209. GFP_KERNEL);
  210. if (!dev->cq_tbl)
  211. return ret;
  212. spin_lock_init(&dev->cq_tbl_lock);
  213. dev->qp_tbl = kcalloc(dev->dsr->caps.max_qp, sizeof(struct pvrdma_qp *),
  214. GFP_KERNEL);
  215. if (!dev->qp_tbl)
  216. goto err_cq_free;
  217. spin_lock_init(&dev->qp_tbl_lock);
  218. /* Check if SRQ is supported by backend */
  219. if (dev->dsr->caps.max_srq) {
  220. dev->ib_dev.uverbs_cmd_mask |=
  221. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  222. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  223. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  224. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  225. (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
  226. dev->ib_dev.create_srq = pvrdma_create_srq;
  227. dev->ib_dev.modify_srq = pvrdma_modify_srq;
  228. dev->ib_dev.query_srq = pvrdma_query_srq;
  229. dev->ib_dev.destroy_srq = pvrdma_destroy_srq;
  230. dev->srq_tbl = kcalloc(dev->dsr->caps.max_srq,
  231. sizeof(struct pvrdma_srq *),
  232. GFP_KERNEL);
  233. if (!dev->srq_tbl)
  234. goto err_qp_free;
  235. }
  236. dev->ib_dev.driver_id = RDMA_DRIVER_VMW_PVRDMA;
  237. spin_lock_init(&dev->srq_tbl_lock);
  238. ret = ib_register_device(&dev->ib_dev, NULL);
  239. if (ret)
  240. goto err_srq_free;
  241. for (i = 0; i < ARRAY_SIZE(pvrdma_class_attributes); ++i) {
  242. ret = device_create_file(&dev->ib_dev.dev,
  243. pvrdma_class_attributes[i]);
  244. if (ret)
  245. goto err_class;
  246. }
  247. dev->ib_active = true;
  248. return 0;
  249. err_class:
  250. ib_unregister_device(&dev->ib_dev);
  251. err_srq_free:
  252. kfree(dev->srq_tbl);
  253. err_qp_free:
  254. kfree(dev->qp_tbl);
  255. err_cq_free:
  256. kfree(dev->cq_tbl);
  257. return ret;
  258. }
  259. static irqreturn_t pvrdma_intr0_handler(int irq, void *dev_id)
  260. {
  261. u32 icr = PVRDMA_INTR_CAUSE_RESPONSE;
  262. struct pvrdma_dev *dev = dev_id;
  263. dev_dbg(&dev->pdev->dev, "interrupt 0 (response) handler\n");
  264. if (!dev->pdev->msix_enabled) {
  265. /* Legacy intr */
  266. icr = pvrdma_read_reg(dev, PVRDMA_REG_ICR);
  267. if (icr == 0)
  268. return IRQ_NONE;
  269. }
  270. if (icr == PVRDMA_INTR_CAUSE_RESPONSE)
  271. complete(&dev->cmd_done);
  272. return IRQ_HANDLED;
  273. }
  274. static void pvrdma_qp_event(struct pvrdma_dev *dev, u32 qpn, int type)
  275. {
  276. struct pvrdma_qp *qp;
  277. unsigned long flags;
  278. spin_lock_irqsave(&dev->qp_tbl_lock, flags);
  279. qp = dev->qp_tbl[qpn % dev->dsr->caps.max_qp];
  280. if (qp)
  281. refcount_inc(&qp->refcnt);
  282. spin_unlock_irqrestore(&dev->qp_tbl_lock, flags);
  283. if (qp && qp->ibqp.event_handler) {
  284. struct ib_qp *ibqp = &qp->ibqp;
  285. struct ib_event e;
  286. e.device = ibqp->device;
  287. e.element.qp = ibqp;
  288. e.event = type; /* 1:1 mapping for now. */
  289. ibqp->event_handler(&e, ibqp->qp_context);
  290. }
  291. if (qp) {
  292. if (refcount_dec_and_test(&qp->refcnt))
  293. complete(&qp->free);
  294. }
  295. }
  296. static void pvrdma_cq_event(struct pvrdma_dev *dev, u32 cqn, int type)
  297. {
  298. struct pvrdma_cq *cq;
  299. unsigned long flags;
  300. spin_lock_irqsave(&dev->cq_tbl_lock, flags);
  301. cq = dev->cq_tbl[cqn % dev->dsr->caps.max_cq];
  302. if (cq)
  303. refcount_inc(&cq->refcnt);
  304. spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
  305. if (cq && cq->ibcq.event_handler) {
  306. struct ib_cq *ibcq = &cq->ibcq;
  307. struct ib_event e;
  308. e.device = ibcq->device;
  309. e.element.cq = ibcq;
  310. e.event = type; /* 1:1 mapping for now. */
  311. ibcq->event_handler(&e, ibcq->cq_context);
  312. }
  313. if (cq) {
  314. if (refcount_dec_and_test(&cq->refcnt))
  315. complete(&cq->free);
  316. }
  317. }
  318. static void pvrdma_srq_event(struct pvrdma_dev *dev, u32 srqn, int type)
  319. {
  320. struct pvrdma_srq *srq;
  321. unsigned long flags;
  322. spin_lock_irqsave(&dev->srq_tbl_lock, flags);
  323. if (dev->srq_tbl)
  324. srq = dev->srq_tbl[srqn % dev->dsr->caps.max_srq];
  325. else
  326. srq = NULL;
  327. if (srq)
  328. refcount_inc(&srq->refcnt);
  329. spin_unlock_irqrestore(&dev->srq_tbl_lock, flags);
  330. if (srq && srq->ibsrq.event_handler) {
  331. struct ib_srq *ibsrq = &srq->ibsrq;
  332. struct ib_event e;
  333. e.device = ibsrq->device;
  334. e.element.srq = ibsrq;
  335. e.event = type; /* 1:1 mapping for now. */
  336. ibsrq->event_handler(&e, ibsrq->srq_context);
  337. }
  338. if (srq) {
  339. if (refcount_dec_and_test(&srq->refcnt))
  340. complete(&srq->free);
  341. }
  342. }
  343. static void pvrdma_dispatch_event(struct pvrdma_dev *dev, int port,
  344. enum ib_event_type event)
  345. {
  346. struct ib_event ib_event;
  347. memset(&ib_event, 0, sizeof(ib_event));
  348. ib_event.device = &dev->ib_dev;
  349. ib_event.element.port_num = port;
  350. ib_event.event = event;
  351. ib_dispatch_event(&ib_event);
  352. }
  353. static void pvrdma_dev_event(struct pvrdma_dev *dev, u8 port, int type)
  354. {
  355. if (port < 1 || port > dev->dsr->caps.phys_port_cnt) {
  356. dev_warn(&dev->pdev->dev, "event on port %d\n", port);
  357. return;
  358. }
  359. pvrdma_dispatch_event(dev, port, type);
  360. }
  361. static inline struct pvrdma_eqe *get_eqe(struct pvrdma_dev *dev, unsigned int i)
  362. {
  363. return (struct pvrdma_eqe *)pvrdma_page_dir_get_ptr(
  364. &dev->async_pdir,
  365. PAGE_SIZE +
  366. sizeof(struct pvrdma_eqe) * i);
  367. }
  368. static irqreturn_t pvrdma_intr1_handler(int irq, void *dev_id)
  369. {
  370. struct pvrdma_dev *dev = dev_id;
  371. struct pvrdma_ring *ring = &dev->async_ring_state->rx;
  372. int ring_slots = (dev->dsr->async_ring_pages.num_pages - 1) *
  373. PAGE_SIZE / sizeof(struct pvrdma_eqe);
  374. unsigned int head;
  375. dev_dbg(&dev->pdev->dev, "interrupt 1 (async event) handler\n");
  376. /*
  377. * Don't process events until the IB device is registered. Otherwise
  378. * we'll try to ib_dispatch_event() on an invalid device.
  379. */
  380. if (!dev->ib_active)
  381. return IRQ_HANDLED;
  382. while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
  383. struct pvrdma_eqe *eqe;
  384. eqe = get_eqe(dev, head);
  385. switch (eqe->type) {
  386. case PVRDMA_EVENT_QP_FATAL:
  387. case PVRDMA_EVENT_QP_REQ_ERR:
  388. case PVRDMA_EVENT_QP_ACCESS_ERR:
  389. case PVRDMA_EVENT_COMM_EST:
  390. case PVRDMA_EVENT_SQ_DRAINED:
  391. case PVRDMA_EVENT_PATH_MIG:
  392. case PVRDMA_EVENT_PATH_MIG_ERR:
  393. case PVRDMA_EVENT_QP_LAST_WQE_REACHED:
  394. pvrdma_qp_event(dev, eqe->info, eqe->type);
  395. break;
  396. case PVRDMA_EVENT_CQ_ERR:
  397. pvrdma_cq_event(dev, eqe->info, eqe->type);
  398. break;
  399. case PVRDMA_EVENT_SRQ_ERR:
  400. case PVRDMA_EVENT_SRQ_LIMIT_REACHED:
  401. pvrdma_srq_event(dev, eqe->info, eqe->type);
  402. break;
  403. case PVRDMA_EVENT_PORT_ACTIVE:
  404. case PVRDMA_EVENT_PORT_ERR:
  405. case PVRDMA_EVENT_LID_CHANGE:
  406. case PVRDMA_EVENT_PKEY_CHANGE:
  407. case PVRDMA_EVENT_SM_CHANGE:
  408. case PVRDMA_EVENT_CLIENT_REREGISTER:
  409. case PVRDMA_EVENT_GID_CHANGE:
  410. pvrdma_dev_event(dev, eqe->info, eqe->type);
  411. break;
  412. case PVRDMA_EVENT_DEVICE_FATAL:
  413. pvrdma_dev_event(dev, 1, eqe->type);
  414. break;
  415. default:
  416. break;
  417. }
  418. pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
  419. }
  420. return IRQ_HANDLED;
  421. }
  422. static inline struct pvrdma_cqne *get_cqne(struct pvrdma_dev *dev,
  423. unsigned int i)
  424. {
  425. return (struct pvrdma_cqne *)pvrdma_page_dir_get_ptr(
  426. &dev->cq_pdir,
  427. PAGE_SIZE +
  428. sizeof(struct pvrdma_cqne) * i);
  429. }
  430. static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id)
  431. {
  432. struct pvrdma_dev *dev = dev_id;
  433. struct pvrdma_ring *ring = &dev->cq_ring_state->rx;
  434. int ring_slots = (dev->dsr->cq_ring_pages.num_pages - 1) * PAGE_SIZE /
  435. sizeof(struct pvrdma_cqne);
  436. unsigned int head;
  437. unsigned long flags;
  438. dev_dbg(&dev->pdev->dev, "interrupt x (completion) handler\n");
  439. while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
  440. struct pvrdma_cqne *cqne;
  441. struct pvrdma_cq *cq;
  442. cqne = get_cqne(dev, head);
  443. spin_lock_irqsave(&dev->cq_tbl_lock, flags);
  444. cq = dev->cq_tbl[cqne->info % dev->dsr->caps.max_cq];
  445. if (cq)
  446. refcount_inc(&cq->refcnt);
  447. spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
  448. if (cq && cq->ibcq.comp_handler)
  449. cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
  450. if (cq) {
  451. if (refcount_dec_and_test(&cq->refcnt))
  452. complete(&cq->free);
  453. }
  454. pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
  455. }
  456. return IRQ_HANDLED;
  457. }
  458. static void pvrdma_free_irq(struct pvrdma_dev *dev)
  459. {
  460. int i;
  461. dev_dbg(&dev->pdev->dev, "freeing interrupts\n");
  462. for (i = 0; i < dev->nr_vectors; i++)
  463. free_irq(pci_irq_vector(dev->pdev, i), dev);
  464. }
  465. static void pvrdma_enable_intrs(struct pvrdma_dev *dev)
  466. {
  467. dev_dbg(&dev->pdev->dev, "enable interrupts\n");
  468. pvrdma_write_reg(dev, PVRDMA_REG_IMR, 0);
  469. }
  470. static void pvrdma_disable_intrs(struct pvrdma_dev *dev)
  471. {
  472. dev_dbg(&dev->pdev->dev, "disable interrupts\n");
  473. pvrdma_write_reg(dev, PVRDMA_REG_IMR, ~0);
  474. }
  475. static int pvrdma_alloc_intrs(struct pvrdma_dev *dev)
  476. {
  477. struct pci_dev *pdev = dev->pdev;
  478. int ret = 0, i;
  479. ret = pci_alloc_irq_vectors(pdev, 1, PVRDMA_MAX_INTERRUPTS,
  480. PCI_IRQ_MSIX);
  481. if (ret < 0) {
  482. ret = pci_alloc_irq_vectors(pdev, 1, 1,
  483. PCI_IRQ_MSI | PCI_IRQ_LEGACY);
  484. if (ret < 0)
  485. return ret;
  486. }
  487. dev->nr_vectors = ret;
  488. ret = request_irq(pci_irq_vector(dev->pdev, 0), pvrdma_intr0_handler,
  489. pdev->msix_enabled ? 0 : IRQF_SHARED, DRV_NAME, dev);
  490. if (ret) {
  491. dev_err(&dev->pdev->dev,
  492. "failed to request interrupt 0\n");
  493. goto out_free_vectors;
  494. }
  495. for (i = 1; i < dev->nr_vectors; i++) {
  496. ret = request_irq(pci_irq_vector(dev->pdev, i),
  497. i == 1 ? pvrdma_intr1_handler :
  498. pvrdma_intrx_handler,
  499. 0, DRV_NAME, dev);
  500. if (ret) {
  501. dev_err(&dev->pdev->dev,
  502. "failed to request interrupt %d\n", i);
  503. goto free_irqs;
  504. }
  505. }
  506. return 0;
  507. free_irqs:
  508. while (--i >= 0)
  509. free_irq(pci_irq_vector(dev->pdev, i), dev);
  510. out_free_vectors:
  511. pci_free_irq_vectors(pdev);
  512. return ret;
  513. }
  514. static void pvrdma_free_slots(struct pvrdma_dev *dev)
  515. {
  516. struct pci_dev *pdev = dev->pdev;
  517. if (dev->resp_slot)
  518. dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->resp_slot,
  519. dev->dsr->resp_slot_dma);
  520. if (dev->cmd_slot)
  521. dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->cmd_slot,
  522. dev->dsr->cmd_slot_dma);
  523. }
  524. static int pvrdma_add_gid_at_index(struct pvrdma_dev *dev,
  525. const union ib_gid *gid,
  526. u8 gid_type,
  527. int index)
  528. {
  529. int ret;
  530. union pvrdma_cmd_req req;
  531. struct pvrdma_cmd_create_bind *cmd_bind = &req.create_bind;
  532. if (!dev->sgid_tbl) {
  533. dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
  534. return -EINVAL;
  535. }
  536. memset(cmd_bind, 0, sizeof(*cmd_bind));
  537. cmd_bind->hdr.cmd = PVRDMA_CMD_CREATE_BIND;
  538. memcpy(cmd_bind->new_gid, gid->raw, 16);
  539. cmd_bind->mtu = ib_mtu_enum_to_int(IB_MTU_1024);
  540. cmd_bind->vlan = 0xfff;
  541. cmd_bind->index = index;
  542. cmd_bind->gid_type = gid_type;
  543. ret = pvrdma_cmd_post(dev, &req, NULL, 0);
  544. if (ret < 0) {
  545. dev_warn(&dev->pdev->dev,
  546. "could not create binding, error: %d\n", ret);
  547. return -EFAULT;
  548. }
  549. memcpy(&dev->sgid_tbl[index], gid, sizeof(*gid));
  550. return 0;
  551. }
  552. static int pvrdma_add_gid(const struct ib_gid_attr *attr, void **context)
  553. {
  554. struct pvrdma_dev *dev = to_vdev(attr->device);
  555. return pvrdma_add_gid_at_index(dev, &attr->gid,
  556. ib_gid_type_to_pvrdma(attr->gid_type),
  557. attr->index);
  558. }
  559. static int pvrdma_del_gid_at_index(struct pvrdma_dev *dev, int index)
  560. {
  561. int ret;
  562. union pvrdma_cmd_req req;
  563. struct pvrdma_cmd_destroy_bind *cmd_dest = &req.destroy_bind;
  564. /* Update sgid table. */
  565. if (!dev->sgid_tbl) {
  566. dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
  567. return -EINVAL;
  568. }
  569. memset(cmd_dest, 0, sizeof(*cmd_dest));
  570. cmd_dest->hdr.cmd = PVRDMA_CMD_DESTROY_BIND;
  571. memcpy(cmd_dest->dest_gid, &dev->sgid_tbl[index], 16);
  572. cmd_dest->index = index;
  573. ret = pvrdma_cmd_post(dev, &req, NULL, 0);
  574. if (ret < 0) {
  575. dev_warn(&dev->pdev->dev,
  576. "could not destroy binding, error: %d\n", ret);
  577. return ret;
  578. }
  579. memset(&dev->sgid_tbl[index], 0, 16);
  580. return 0;
  581. }
  582. static int pvrdma_del_gid(const struct ib_gid_attr *attr, void **context)
  583. {
  584. struct pvrdma_dev *dev = to_vdev(attr->device);
  585. dev_dbg(&dev->pdev->dev, "removing gid at index %u from %s",
  586. attr->index, dev->netdev->name);
  587. return pvrdma_del_gid_at_index(dev, attr->index);
  588. }
  589. static void pvrdma_netdevice_event_handle(struct pvrdma_dev *dev,
  590. struct net_device *ndev,
  591. unsigned long event)
  592. {
  593. struct pci_dev *pdev_net;
  594. unsigned int slot;
  595. switch (event) {
  596. case NETDEV_REBOOT:
  597. case NETDEV_DOWN:
  598. pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
  599. break;
  600. case NETDEV_UP:
  601. pvrdma_write_reg(dev, PVRDMA_REG_CTL,
  602. PVRDMA_DEVICE_CTL_UNQUIESCE);
  603. mb();
  604. if (pvrdma_read_reg(dev, PVRDMA_REG_ERR))
  605. dev_err(&dev->pdev->dev,
  606. "failed to activate device during link up\n");
  607. else
  608. pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
  609. break;
  610. case NETDEV_UNREGISTER:
  611. dev_put(dev->netdev);
  612. dev->netdev = NULL;
  613. break;
  614. case NETDEV_REGISTER:
  615. /* vmxnet3 will have same bus, slot. But func will be 0 */
  616. slot = PCI_SLOT(dev->pdev->devfn);
  617. pdev_net = pci_get_slot(dev->pdev->bus,
  618. PCI_DEVFN(slot, 0));
  619. if ((dev->netdev == NULL) &&
  620. (pci_get_drvdata(pdev_net) == ndev)) {
  621. /* this is our netdev */
  622. dev->netdev = ndev;
  623. dev_hold(ndev);
  624. }
  625. pci_dev_put(pdev_net);
  626. break;
  627. default:
  628. dev_dbg(&dev->pdev->dev, "ignore netdevice event %ld on %s\n",
  629. event, dev->ib_dev.name);
  630. break;
  631. }
  632. }
  633. static void pvrdma_netdevice_event_work(struct work_struct *work)
  634. {
  635. struct pvrdma_netdevice_work *netdev_work;
  636. struct pvrdma_dev *dev;
  637. netdev_work = container_of(work, struct pvrdma_netdevice_work, work);
  638. mutex_lock(&pvrdma_device_list_lock);
  639. list_for_each_entry(dev, &pvrdma_device_list, device_link) {
  640. if ((netdev_work->event == NETDEV_REGISTER) ||
  641. (dev->netdev == netdev_work->event_netdev)) {
  642. pvrdma_netdevice_event_handle(dev,
  643. netdev_work->event_netdev,
  644. netdev_work->event);
  645. break;
  646. }
  647. }
  648. mutex_unlock(&pvrdma_device_list_lock);
  649. kfree(netdev_work);
  650. }
  651. static int pvrdma_netdevice_event(struct notifier_block *this,
  652. unsigned long event, void *ptr)
  653. {
  654. struct net_device *event_netdev = netdev_notifier_info_to_dev(ptr);
  655. struct pvrdma_netdevice_work *netdev_work;
  656. netdev_work = kmalloc(sizeof(*netdev_work), GFP_ATOMIC);
  657. if (!netdev_work)
  658. return NOTIFY_BAD;
  659. INIT_WORK(&netdev_work->work, pvrdma_netdevice_event_work);
  660. netdev_work->event_netdev = event_netdev;
  661. netdev_work->event = event;
  662. queue_work(event_wq, &netdev_work->work);
  663. return NOTIFY_DONE;
  664. }
  665. static int pvrdma_pci_probe(struct pci_dev *pdev,
  666. const struct pci_device_id *id)
  667. {
  668. struct pci_dev *pdev_net;
  669. struct pvrdma_dev *dev;
  670. int ret;
  671. unsigned long start;
  672. unsigned long len;
  673. dma_addr_t slot_dma = 0;
  674. dev_dbg(&pdev->dev, "initializing driver %s\n", pci_name(pdev));
  675. /* Allocate zero-out device */
  676. dev = (struct pvrdma_dev *)ib_alloc_device(sizeof(*dev));
  677. if (!dev) {
  678. dev_err(&pdev->dev, "failed to allocate IB device\n");
  679. return -ENOMEM;
  680. }
  681. mutex_lock(&pvrdma_device_list_lock);
  682. list_add(&dev->device_link, &pvrdma_device_list);
  683. mutex_unlock(&pvrdma_device_list_lock);
  684. ret = pvrdma_init_device(dev);
  685. if (ret)
  686. goto err_free_device;
  687. dev->pdev = pdev;
  688. pci_set_drvdata(pdev, dev);
  689. ret = pci_enable_device(pdev);
  690. if (ret) {
  691. dev_err(&pdev->dev, "cannot enable PCI device\n");
  692. goto err_free_device;
  693. }
  694. dev_dbg(&pdev->dev, "PCI resource flags BAR0 %#lx\n",
  695. pci_resource_flags(pdev, 0));
  696. dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
  697. (unsigned long long)pci_resource_len(pdev, 0));
  698. dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
  699. (unsigned long long)pci_resource_start(pdev, 0));
  700. dev_dbg(&pdev->dev, "PCI resource flags BAR1 %#lx\n",
  701. pci_resource_flags(pdev, 1));
  702. dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
  703. (unsigned long long)pci_resource_len(pdev, 1));
  704. dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
  705. (unsigned long long)pci_resource_start(pdev, 1));
  706. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  707. !(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
  708. dev_err(&pdev->dev, "PCI BAR region not MMIO\n");
  709. ret = -ENOMEM;
  710. goto err_disable_pdev;
  711. }
  712. ret = pci_request_regions(pdev, DRV_NAME);
  713. if (ret) {
  714. dev_err(&pdev->dev, "cannot request PCI resources\n");
  715. goto err_disable_pdev;
  716. }
  717. /* Enable 64-Bit DMA */
  718. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
  719. ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  720. if (ret != 0) {
  721. dev_err(&pdev->dev,
  722. "pci_set_consistent_dma_mask failed\n");
  723. goto err_free_resource;
  724. }
  725. } else {
  726. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  727. if (ret != 0) {
  728. dev_err(&pdev->dev,
  729. "pci_set_dma_mask failed\n");
  730. goto err_free_resource;
  731. }
  732. }
  733. pci_set_master(pdev);
  734. /* Map register space */
  735. start = pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
  736. len = pci_resource_len(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
  737. dev->regs = ioremap(start, len);
  738. if (!dev->regs) {
  739. dev_err(&pdev->dev, "register mapping failed\n");
  740. ret = -ENOMEM;
  741. goto err_free_resource;
  742. }
  743. /* Setup per-device UAR. */
  744. dev->driver_uar.index = 0;
  745. dev->driver_uar.pfn =
  746. pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_UAR) >>
  747. PAGE_SHIFT;
  748. dev->driver_uar.map =
  749. ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  750. if (!dev->driver_uar.map) {
  751. dev_err(&pdev->dev, "failed to remap UAR pages\n");
  752. ret = -ENOMEM;
  753. goto err_unmap_regs;
  754. }
  755. dev->dsr_version = pvrdma_read_reg(dev, PVRDMA_REG_VERSION);
  756. dev_info(&pdev->dev, "device version %d, driver version %d\n",
  757. dev->dsr_version, PVRDMA_VERSION);
  758. dev->dsr = dma_zalloc_coherent(&pdev->dev, sizeof(*dev->dsr),
  759. &dev->dsrbase, GFP_KERNEL);
  760. if (!dev->dsr) {
  761. dev_err(&pdev->dev, "failed to allocate shared region\n");
  762. ret = -ENOMEM;
  763. goto err_uar_unmap;
  764. }
  765. /* Setup the shared region */
  766. dev->dsr->driver_version = PVRDMA_VERSION;
  767. dev->dsr->gos_info.gos_bits = sizeof(void *) == 4 ?
  768. PVRDMA_GOS_BITS_32 :
  769. PVRDMA_GOS_BITS_64;
  770. dev->dsr->gos_info.gos_type = PVRDMA_GOS_TYPE_LINUX;
  771. dev->dsr->gos_info.gos_ver = 1;
  772. dev->dsr->uar_pfn = dev->driver_uar.pfn;
  773. /* Command slot. */
  774. dev->cmd_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
  775. &slot_dma, GFP_KERNEL);
  776. if (!dev->cmd_slot) {
  777. ret = -ENOMEM;
  778. goto err_free_dsr;
  779. }
  780. dev->dsr->cmd_slot_dma = (u64)slot_dma;
  781. /* Response slot. */
  782. dev->resp_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
  783. &slot_dma, GFP_KERNEL);
  784. if (!dev->resp_slot) {
  785. ret = -ENOMEM;
  786. goto err_free_slots;
  787. }
  788. dev->dsr->resp_slot_dma = (u64)slot_dma;
  789. /* Async event ring */
  790. dev->dsr->async_ring_pages.num_pages = PVRDMA_NUM_RING_PAGES;
  791. ret = pvrdma_page_dir_init(dev, &dev->async_pdir,
  792. dev->dsr->async_ring_pages.num_pages, true);
  793. if (ret)
  794. goto err_free_slots;
  795. dev->async_ring_state = dev->async_pdir.pages[0];
  796. dev->dsr->async_ring_pages.pdir_dma = dev->async_pdir.dir_dma;
  797. /* CQ notification ring */
  798. dev->dsr->cq_ring_pages.num_pages = PVRDMA_NUM_RING_PAGES;
  799. ret = pvrdma_page_dir_init(dev, &dev->cq_pdir,
  800. dev->dsr->cq_ring_pages.num_pages, true);
  801. if (ret)
  802. goto err_free_async_ring;
  803. dev->cq_ring_state = dev->cq_pdir.pages[0];
  804. dev->dsr->cq_ring_pages.pdir_dma = dev->cq_pdir.dir_dma;
  805. /*
  806. * Write the PA of the shared region to the device. The writes must be
  807. * ordered such that the high bits are written last. When the writes
  808. * complete, the device will have filled out the capabilities.
  809. */
  810. pvrdma_write_reg(dev, PVRDMA_REG_DSRLOW, (u32)dev->dsrbase);
  811. pvrdma_write_reg(dev, PVRDMA_REG_DSRHIGH,
  812. (u32)((u64)(dev->dsrbase) >> 32));
  813. /* Make sure the write is complete before reading status. */
  814. mb();
  815. /* The driver supports RoCE V1 and V2. */
  816. if (!PVRDMA_SUPPORTED(dev)) {
  817. dev_err(&pdev->dev, "driver needs RoCE v1 or v2 support\n");
  818. ret = -EFAULT;
  819. goto err_free_cq_ring;
  820. }
  821. /* Paired vmxnet3 will have same bus, slot. But func will be 0 */
  822. pdev_net = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
  823. if (!pdev_net) {
  824. dev_err(&pdev->dev, "failed to find paired net device\n");
  825. ret = -ENODEV;
  826. goto err_free_cq_ring;
  827. }
  828. if (pdev_net->vendor != PCI_VENDOR_ID_VMWARE ||
  829. pdev_net->device != PCI_DEVICE_ID_VMWARE_VMXNET3) {
  830. dev_err(&pdev->dev, "failed to find paired vmxnet3 device\n");
  831. pci_dev_put(pdev_net);
  832. ret = -ENODEV;
  833. goto err_free_cq_ring;
  834. }
  835. dev->netdev = pci_get_drvdata(pdev_net);
  836. pci_dev_put(pdev_net);
  837. if (!dev->netdev) {
  838. dev_err(&pdev->dev, "failed to get vmxnet3 device\n");
  839. ret = -ENODEV;
  840. goto err_free_cq_ring;
  841. }
  842. dev_hold(dev->netdev);
  843. dev_info(&pdev->dev, "paired device to %s\n", dev->netdev->name);
  844. /* Interrupt setup */
  845. ret = pvrdma_alloc_intrs(dev);
  846. if (ret) {
  847. dev_err(&pdev->dev, "failed to allocate interrupts\n");
  848. ret = -ENOMEM;
  849. goto err_free_cq_ring;
  850. }
  851. /* Allocate UAR table. */
  852. ret = pvrdma_uar_table_init(dev);
  853. if (ret) {
  854. dev_err(&pdev->dev, "failed to allocate UAR table\n");
  855. ret = -ENOMEM;
  856. goto err_free_intrs;
  857. }
  858. /* Allocate GID table */
  859. dev->sgid_tbl = kcalloc(dev->dsr->caps.gid_tbl_len,
  860. sizeof(union ib_gid), GFP_KERNEL);
  861. if (!dev->sgid_tbl) {
  862. ret = -ENOMEM;
  863. goto err_free_uar_table;
  864. }
  865. dev_dbg(&pdev->dev, "gid table len %d\n", dev->dsr->caps.gid_tbl_len);
  866. pvrdma_enable_intrs(dev);
  867. /* Activate pvrdma device */
  868. pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_ACTIVATE);
  869. /* Make sure the write is complete before reading status. */
  870. mb();
  871. /* Check if device was successfully activated */
  872. ret = pvrdma_read_reg(dev, PVRDMA_REG_ERR);
  873. if (ret != 0) {
  874. dev_err(&pdev->dev, "failed to activate device\n");
  875. ret = -EFAULT;
  876. goto err_disable_intr;
  877. }
  878. /* Register IB device */
  879. ret = pvrdma_register_device(dev);
  880. if (ret) {
  881. dev_err(&pdev->dev, "failed to register IB device\n");
  882. goto err_disable_intr;
  883. }
  884. dev->nb_netdev.notifier_call = pvrdma_netdevice_event;
  885. ret = register_netdevice_notifier(&dev->nb_netdev);
  886. if (ret) {
  887. dev_err(&pdev->dev, "failed to register netdevice events\n");
  888. goto err_unreg_ibdev;
  889. }
  890. dev_info(&pdev->dev, "attached to device\n");
  891. return 0;
  892. err_unreg_ibdev:
  893. ib_unregister_device(&dev->ib_dev);
  894. err_disable_intr:
  895. pvrdma_disable_intrs(dev);
  896. kfree(dev->sgid_tbl);
  897. err_free_uar_table:
  898. pvrdma_uar_table_cleanup(dev);
  899. err_free_intrs:
  900. pvrdma_free_irq(dev);
  901. pci_free_irq_vectors(pdev);
  902. err_free_cq_ring:
  903. if (dev->netdev) {
  904. dev_put(dev->netdev);
  905. dev->netdev = NULL;
  906. }
  907. pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
  908. err_free_async_ring:
  909. pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
  910. err_free_slots:
  911. pvrdma_free_slots(dev);
  912. err_free_dsr:
  913. dma_free_coherent(&pdev->dev, sizeof(*dev->dsr), dev->dsr,
  914. dev->dsrbase);
  915. err_uar_unmap:
  916. iounmap(dev->driver_uar.map);
  917. err_unmap_regs:
  918. iounmap(dev->regs);
  919. err_free_resource:
  920. pci_release_regions(pdev);
  921. err_disable_pdev:
  922. pci_disable_device(pdev);
  923. pci_set_drvdata(pdev, NULL);
  924. err_free_device:
  925. mutex_lock(&pvrdma_device_list_lock);
  926. list_del(&dev->device_link);
  927. mutex_unlock(&pvrdma_device_list_lock);
  928. ib_dealloc_device(&dev->ib_dev);
  929. return ret;
  930. }
  931. static void pvrdma_pci_remove(struct pci_dev *pdev)
  932. {
  933. struct pvrdma_dev *dev = pci_get_drvdata(pdev);
  934. if (!dev)
  935. return;
  936. dev_info(&pdev->dev, "detaching from device\n");
  937. unregister_netdevice_notifier(&dev->nb_netdev);
  938. dev->nb_netdev.notifier_call = NULL;
  939. flush_workqueue(event_wq);
  940. if (dev->netdev) {
  941. dev_put(dev->netdev);
  942. dev->netdev = NULL;
  943. }
  944. /* Unregister ib device */
  945. ib_unregister_device(&dev->ib_dev);
  946. mutex_lock(&pvrdma_device_list_lock);
  947. list_del(&dev->device_link);
  948. mutex_unlock(&pvrdma_device_list_lock);
  949. pvrdma_disable_intrs(dev);
  950. pvrdma_free_irq(dev);
  951. pci_free_irq_vectors(pdev);
  952. /* Deactivate pvrdma device */
  953. pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_RESET);
  954. pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
  955. pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
  956. pvrdma_free_slots(dev);
  957. dma_free_coherent(&pdev->dev, sizeof(*dev->dsr), dev->dsr,
  958. dev->dsrbase);
  959. iounmap(dev->regs);
  960. kfree(dev->sgid_tbl);
  961. kfree(dev->cq_tbl);
  962. kfree(dev->srq_tbl);
  963. kfree(dev->qp_tbl);
  964. pvrdma_uar_table_cleanup(dev);
  965. iounmap(dev->driver_uar.map);
  966. ib_dealloc_device(&dev->ib_dev);
  967. /* Free pci resources */
  968. pci_release_regions(pdev);
  969. pci_disable_device(pdev);
  970. pci_set_drvdata(pdev, NULL);
  971. }
  972. static const struct pci_device_id pvrdma_pci_table[] = {
  973. { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, PCI_DEVICE_ID_VMWARE_PVRDMA), },
  974. { 0 },
  975. };
  976. MODULE_DEVICE_TABLE(pci, pvrdma_pci_table);
  977. static struct pci_driver pvrdma_driver = {
  978. .name = DRV_NAME,
  979. .id_table = pvrdma_pci_table,
  980. .probe = pvrdma_pci_probe,
  981. .remove = pvrdma_pci_remove,
  982. };
  983. static int __init pvrdma_init(void)
  984. {
  985. int err;
  986. event_wq = alloc_ordered_workqueue("pvrdma_event_wq", WQ_MEM_RECLAIM);
  987. if (!event_wq)
  988. return -ENOMEM;
  989. err = pci_register_driver(&pvrdma_driver);
  990. if (err)
  991. destroy_workqueue(event_wq);
  992. return err;
  993. }
  994. static void __exit pvrdma_cleanup(void)
  995. {
  996. pci_unregister_driver(&pvrdma_driver);
  997. destroy_workqueue(event_wq);
  998. }
  999. module_init(pvrdma_init);
  1000. module_exit(pvrdma_cleanup);
  1001. MODULE_AUTHOR("VMware, Inc");
  1002. MODULE_DESCRIPTION("VMware Paravirtual RDMA driver");
  1003. MODULE_LICENSE("Dual BSD/GPL");