Kconfig 7.2 KB

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  1. menu "IRQ chip support"
  2. config IRQCHIP
  3. def_bool y
  4. depends on OF_IRQ
  5. config ARM_GIC
  6. bool
  7. select IRQ_DOMAIN
  8. select IRQ_DOMAIN_HIERARCHY
  9. select GENERIC_IRQ_MULTI_HANDLER
  10. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  11. config ARM_GIC_PM
  12. bool
  13. depends on PM
  14. select ARM_GIC
  15. select PM_CLK
  16. config ARM_GIC_MAX_NR
  17. int
  18. default 2 if ARCH_REALVIEW
  19. default 1
  20. config ARM_GIC_V2M
  21. bool
  22. depends on PCI
  23. select ARM_GIC
  24. select PCI_MSI
  25. config GIC_NON_BANKED
  26. bool
  27. config ARM_GIC_V3
  28. bool
  29. select IRQ_DOMAIN
  30. select GENERIC_IRQ_MULTI_HANDLER
  31. select IRQ_DOMAIN_HIERARCHY
  32. select PARTITION_PERCPU
  33. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  34. config ARM_GIC_V3_ITS
  35. bool
  36. select GENERIC_MSI_IRQ_DOMAIN
  37. default ARM_GIC_V3
  38. config ARM_GIC_V3_ITS_PCI
  39. bool
  40. depends on ARM_GIC_V3_ITS
  41. depends on PCI
  42. depends on PCI_MSI
  43. default ARM_GIC_V3_ITS
  44. config ARM_GIC_V3_ITS_FSL_MC
  45. bool
  46. depends on ARM_GIC_V3_ITS
  47. depends on FSL_MC_BUS
  48. default ARM_GIC_V3_ITS
  49. config ARM_NVIC
  50. bool
  51. select IRQ_DOMAIN
  52. select IRQ_DOMAIN_HIERARCHY
  53. select GENERIC_IRQ_CHIP
  54. config ARM_VIC
  55. bool
  56. select IRQ_DOMAIN
  57. select GENERIC_IRQ_MULTI_HANDLER
  58. config ARM_VIC_NR
  59. int
  60. default 4 if ARCH_S5PV210
  61. default 2
  62. depends on ARM_VIC
  63. help
  64. The maximum number of VICs available in the system, for
  65. power management.
  66. config ARMADA_370_XP_IRQ
  67. bool
  68. select GENERIC_IRQ_CHIP
  69. select PCI_MSI if PCI
  70. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  71. config ALPINE_MSI
  72. bool
  73. depends on PCI
  74. select PCI_MSI
  75. select GENERIC_IRQ_CHIP
  76. config ATMEL_AIC_IRQ
  77. bool
  78. select GENERIC_IRQ_CHIP
  79. select IRQ_DOMAIN
  80. select GENERIC_IRQ_MULTI_HANDLER
  81. select SPARSE_IRQ
  82. config ATMEL_AIC5_IRQ
  83. bool
  84. select GENERIC_IRQ_CHIP
  85. select IRQ_DOMAIN
  86. select GENERIC_IRQ_MULTI_HANDLER
  87. select SPARSE_IRQ
  88. config I8259
  89. bool
  90. select IRQ_DOMAIN
  91. config BCM6345_L1_IRQ
  92. bool
  93. select GENERIC_IRQ_CHIP
  94. select IRQ_DOMAIN
  95. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  96. config BCM7038_L1_IRQ
  97. bool
  98. select GENERIC_IRQ_CHIP
  99. select IRQ_DOMAIN
  100. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  101. config BCM7120_L2_IRQ
  102. bool
  103. select GENERIC_IRQ_CHIP
  104. select IRQ_DOMAIN
  105. config BRCMSTB_L2_IRQ
  106. bool
  107. select GENERIC_IRQ_CHIP
  108. select IRQ_DOMAIN
  109. config DW_APB_ICTL
  110. bool
  111. select GENERIC_IRQ_CHIP
  112. select IRQ_DOMAIN
  113. config FARADAY_FTINTC010
  114. bool
  115. select IRQ_DOMAIN
  116. select GENERIC_IRQ_MULTI_HANDLER
  117. select SPARSE_IRQ
  118. config HISILICON_IRQ_MBIGEN
  119. bool
  120. select ARM_GIC_V3
  121. select ARM_GIC_V3_ITS
  122. config IMGPDC_IRQ
  123. bool
  124. select GENERIC_IRQ_CHIP
  125. select IRQ_DOMAIN
  126. config IRQ_MIPS_CPU
  127. bool
  128. select GENERIC_IRQ_CHIP
  129. select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
  130. select IRQ_DOMAIN
  131. select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
  132. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  133. config CLPS711X_IRQCHIP
  134. bool
  135. depends on ARCH_CLPS711X
  136. select IRQ_DOMAIN
  137. select GENERIC_IRQ_MULTI_HANDLER
  138. select SPARSE_IRQ
  139. default y
  140. config OMPIC
  141. bool
  142. config OR1K_PIC
  143. bool
  144. select IRQ_DOMAIN
  145. config OMAP_IRQCHIP
  146. bool
  147. select GENERIC_IRQ_CHIP
  148. select IRQ_DOMAIN
  149. config ORION_IRQCHIP
  150. bool
  151. select IRQ_DOMAIN
  152. select GENERIC_IRQ_MULTI_HANDLER
  153. config PIC32_EVIC
  154. bool
  155. select GENERIC_IRQ_CHIP
  156. select IRQ_DOMAIN
  157. config JCORE_AIC
  158. bool "J-Core integrated AIC" if COMPILE_TEST
  159. depends on OF
  160. select IRQ_DOMAIN
  161. help
  162. Support for the J-Core integrated AIC.
  163. config RENESAS_INTC_IRQPIN
  164. bool
  165. select IRQ_DOMAIN
  166. config RENESAS_IRQC
  167. bool
  168. select GENERIC_IRQ_CHIP
  169. select IRQ_DOMAIN
  170. config ST_IRQCHIP
  171. bool
  172. select REGMAP
  173. select MFD_SYSCON
  174. help
  175. Enables SysCfg Controlled IRQs on STi based platforms.
  176. config TANGO_IRQ
  177. bool
  178. select IRQ_DOMAIN
  179. select GENERIC_IRQ_CHIP
  180. config TB10X_IRQC
  181. bool
  182. select IRQ_DOMAIN
  183. select GENERIC_IRQ_CHIP
  184. config TS4800_IRQ
  185. tristate "TS-4800 IRQ controller"
  186. select IRQ_DOMAIN
  187. depends on HAS_IOMEM
  188. depends on SOC_IMX51 || COMPILE_TEST
  189. help
  190. Support for the TS-4800 FPGA IRQ controller
  191. config VERSATILE_FPGA_IRQ
  192. bool
  193. select IRQ_DOMAIN
  194. config VERSATILE_FPGA_IRQ_NR
  195. int
  196. default 4
  197. depends on VERSATILE_FPGA_IRQ
  198. config XTENSA_MX
  199. bool
  200. select IRQ_DOMAIN
  201. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  202. config XILINX_INTC
  203. bool
  204. select IRQ_DOMAIN
  205. config IRQ_CROSSBAR
  206. bool
  207. help
  208. Support for a CROSSBAR ip that precedes the main interrupt controller.
  209. The primary irqchip invokes the crossbar's callback which inturn allocates
  210. a free irq and configures the IP. Thus the peripheral interrupts are
  211. routed to one of the free irqchip interrupt lines.
  212. config KEYSTONE_IRQ
  213. tristate "Keystone 2 IRQ controller IP"
  214. depends on ARCH_KEYSTONE
  215. help
  216. Support for Texas Instruments Keystone 2 IRQ controller IP which
  217. is part of the Keystone 2 IPC mechanism
  218. config MIPS_GIC
  219. bool
  220. select GENERIC_IRQ_IPI
  221. select IRQ_DOMAIN_HIERARCHY
  222. select MIPS_CM
  223. config INGENIC_IRQ
  224. bool
  225. depends on MACH_INGENIC
  226. default y
  227. config RENESAS_H8300H_INTC
  228. bool
  229. select IRQ_DOMAIN
  230. config RENESAS_H8S_INTC
  231. bool
  232. select IRQ_DOMAIN
  233. config IMX_GPCV2
  234. bool
  235. select IRQ_DOMAIN
  236. help
  237. Enables the wakeup IRQs for IMX platforms with GPCv2 block
  238. config IRQ_MXS
  239. def_bool y if MACH_ASM9260 || ARCH_MXS
  240. select IRQ_DOMAIN
  241. select STMP_DEVICE
  242. config MSCC_OCELOT_IRQ
  243. bool
  244. select IRQ_DOMAIN
  245. select GENERIC_IRQ_CHIP
  246. config MVEBU_GICP
  247. bool
  248. config MVEBU_ICU
  249. bool
  250. config MVEBU_ODMI
  251. bool
  252. select GENERIC_MSI_IRQ_DOMAIN
  253. config MVEBU_PIC
  254. bool
  255. config LS_SCFG_MSI
  256. def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
  257. depends on PCI && PCI_MSI
  258. config PARTITION_PERCPU
  259. bool
  260. config EZNPS_GIC
  261. bool "NPS400 Global Interrupt Manager (GIM)"
  262. depends on ARC || (COMPILE_TEST && !64BIT)
  263. select IRQ_DOMAIN
  264. help
  265. Support the EZchip NPS400 global interrupt controller
  266. config STM32_EXTI
  267. bool
  268. select IRQ_DOMAIN
  269. select GENERIC_IRQ_CHIP
  270. config QCOM_IRQ_COMBINER
  271. bool "QCOM IRQ combiner support"
  272. depends on ARCH_QCOM && ACPI
  273. select IRQ_DOMAIN
  274. select IRQ_DOMAIN_HIERARCHY
  275. help
  276. Say yes here to add support for the IRQ combiner devices embedded
  277. in Qualcomm Technologies chips.
  278. config IRQ_UNIPHIER_AIDET
  279. bool "UniPhier AIDET support" if COMPILE_TEST
  280. depends on ARCH_UNIPHIER || COMPILE_TEST
  281. default ARCH_UNIPHIER
  282. select IRQ_DOMAIN_HIERARCHY
  283. help
  284. Support for the UniPhier AIDET (ARM Interrupt Detector).
  285. config MESON_IRQ_GPIO
  286. bool "Meson GPIO Interrupt Multiplexer"
  287. depends on ARCH_MESON
  288. select IRQ_DOMAIN
  289. select IRQ_DOMAIN_HIERARCHY
  290. help
  291. Support Meson SoC Family GPIO Interrupt Multiplexer
  292. config GOLDFISH_PIC
  293. bool "Goldfish programmable interrupt controller"
  294. depends on MIPS && (GOLDFISH || COMPILE_TEST)
  295. select IRQ_DOMAIN
  296. help
  297. Say yes here to enable Goldfish interrupt controller driver used
  298. for Goldfish based virtual platforms.
  299. config QCOM_PDC
  300. bool "QCOM PDC"
  301. depends on ARCH_QCOM
  302. select IRQ_DOMAIN
  303. select IRQ_DOMAIN_HIERARCHY
  304. help
  305. Power Domain Controller driver to manage and configure wakeup
  306. IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
  307. config SIFIVE_PLIC
  308. bool "SiFive Platform-Level Interrupt Controller"
  309. depends on RISCV
  310. help
  311. This enables support for the PLIC chip found in SiFive (and
  312. potentially other) RISC-V systems. The PLIC controls devices
  313. interrupts and connects them to each core's local interrupt
  314. controller. Aside from timer and software interrupts, all other
  315. interrupt sources are subordinate to the PLIC.
  316. If you don't know what to do here, say Y.
  317. endmenu