irq-bcm6345-l1.c 9.4 KB

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  1. /*
  2. * Broadcom BCM6345 style Level 1 interrupt controller driver
  3. *
  4. * Copyright (C) 2014 Broadcom Corporation
  5. * Copyright 2015 Simon Arlott
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This is based on the BCM7038 (which supports SMP) but with a single
  12. * enable register instead of separate mask/set/clear registers.
  13. *
  14. * The BCM3380 has a similar mask/status register layout, but each pair
  15. * of words is at separate locations (and SMP is not supported).
  16. *
  17. * ENABLE/STATUS words are packed next to each other for each CPU:
  18. *
  19. * BCM6368:
  20. * 0x1000_0020: CPU0_W0_ENABLE
  21. * 0x1000_0024: CPU0_W1_ENABLE
  22. * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
  23. * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
  24. * 0x1000_0030: CPU1_W0_ENABLE
  25. * 0x1000_0034: CPU1_W1_ENABLE
  26. * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
  27. * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
  28. *
  29. * BCM63168:
  30. * 0x1000_0020: CPU0_W0_ENABLE
  31. * 0x1000_0024: CPU0_W1_ENABLE
  32. * 0x1000_0028: CPU0_W2_ENABLE
  33. * 0x1000_002c: CPU0_W3_ENABLE
  34. * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
  35. * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
  36. * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
  37. * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
  38. * 0x1000_0040: CPU1_W0_ENABLE
  39. * 0x1000_0044: CPU1_W1_ENABLE
  40. * 0x1000_0048: CPU1_W2_ENABLE
  41. * 0x1000_004c: CPU1_W3_ENABLE
  42. * 0x1000_0050: CPU1_W0_STATUS IRQs 96-127
  43. * 0x1000_0054: CPU1_W1_STATUS IRQs 64-95
  44. * 0x1000_0058: CPU1_W2_STATUS IRQs 32-63
  45. * 0x1000_005c: CPU1_W3_STATUS IRQs 0-31
  46. *
  47. * IRQs are numbered in CPU native endian order
  48. * (which is big-endian in these examples)
  49. */
  50. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  51. #include <linux/bitops.h>
  52. #include <linux/cpumask.h>
  53. #include <linux/kernel.h>
  54. #include <linux/init.h>
  55. #include <linux/interrupt.h>
  56. #include <linux/io.h>
  57. #include <linux/ioport.h>
  58. #include <linux/irq.h>
  59. #include <linux/irqdomain.h>
  60. #include <linux/module.h>
  61. #include <linux/of.h>
  62. #include <linux/of_irq.h>
  63. #include <linux/of_address.h>
  64. #include <linux/of_platform.h>
  65. #include <linux/platform_device.h>
  66. #include <linux/slab.h>
  67. #include <linux/smp.h>
  68. #include <linux/types.h>
  69. #include <linux/irqchip.h>
  70. #include <linux/irqchip/chained_irq.h>
  71. #define IRQS_PER_WORD 32
  72. #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 2)
  73. struct bcm6345_l1_cpu;
  74. struct bcm6345_l1_chip {
  75. raw_spinlock_t lock;
  76. unsigned int n_words;
  77. struct irq_domain *domain;
  78. struct cpumask cpumask;
  79. struct bcm6345_l1_cpu *cpus[NR_CPUS];
  80. };
  81. struct bcm6345_l1_cpu {
  82. void __iomem *map_base;
  83. unsigned int parent_irq;
  84. u32 enable_cache[];
  85. };
  86. static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc,
  87. unsigned int word)
  88. {
  89. #ifdef __BIG_ENDIAN
  90. return (1 * intc->n_words - word - 1) * sizeof(u32);
  91. #else
  92. return (0 * intc->n_words + word) * sizeof(u32);
  93. #endif
  94. }
  95. static inline unsigned int reg_status(struct bcm6345_l1_chip *intc,
  96. unsigned int word)
  97. {
  98. #ifdef __BIG_ENDIAN
  99. return (2 * intc->n_words - word - 1) * sizeof(u32);
  100. #else
  101. return (1 * intc->n_words + word) * sizeof(u32);
  102. #endif
  103. }
  104. static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
  105. struct irq_data *d)
  106. {
  107. return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
  108. }
  109. static void bcm6345_l1_irq_handle(struct irq_desc *desc)
  110. {
  111. struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);
  112. struct bcm6345_l1_cpu *cpu;
  113. struct irq_chip *chip = irq_desc_get_chip(desc);
  114. unsigned int idx;
  115. #ifdef CONFIG_SMP
  116. cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
  117. #else
  118. cpu = intc->cpus[0];
  119. #endif
  120. chained_irq_enter(chip, desc);
  121. for (idx = 0; idx < intc->n_words; idx++) {
  122. int base = idx * IRQS_PER_WORD;
  123. unsigned long pending;
  124. irq_hw_number_t hwirq;
  125. unsigned int irq;
  126. pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
  127. pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
  128. for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
  129. irq = irq_linear_revmap(intc->domain, base + hwirq);
  130. if (irq)
  131. do_IRQ(irq);
  132. else
  133. spurious_interrupt();
  134. }
  135. }
  136. chained_irq_exit(chip, desc);
  137. }
  138. static inline void __bcm6345_l1_unmask(struct irq_data *d)
  139. {
  140. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  141. u32 word = d->hwirq / IRQS_PER_WORD;
  142. u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
  143. unsigned int cpu_idx = cpu_for_irq(intc, d);
  144. intc->cpus[cpu_idx]->enable_cache[word] |= mask;
  145. __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
  146. intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
  147. }
  148. static inline void __bcm6345_l1_mask(struct irq_data *d)
  149. {
  150. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  151. u32 word = d->hwirq / IRQS_PER_WORD;
  152. u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
  153. unsigned int cpu_idx = cpu_for_irq(intc, d);
  154. intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;
  155. __raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
  156. intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
  157. }
  158. static void bcm6345_l1_unmask(struct irq_data *d)
  159. {
  160. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  161. unsigned long flags;
  162. raw_spin_lock_irqsave(&intc->lock, flags);
  163. __bcm6345_l1_unmask(d);
  164. raw_spin_unlock_irqrestore(&intc->lock, flags);
  165. }
  166. static void bcm6345_l1_mask(struct irq_data *d)
  167. {
  168. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  169. unsigned long flags;
  170. raw_spin_lock_irqsave(&intc->lock, flags);
  171. __bcm6345_l1_mask(d);
  172. raw_spin_unlock_irqrestore(&intc->lock, flags);
  173. }
  174. static int bcm6345_l1_set_affinity(struct irq_data *d,
  175. const struct cpumask *dest,
  176. bool force)
  177. {
  178. struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
  179. u32 word = d->hwirq / IRQS_PER_WORD;
  180. u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
  181. unsigned int old_cpu = cpu_for_irq(intc, d);
  182. unsigned int new_cpu;
  183. struct cpumask valid;
  184. unsigned long flags;
  185. bool enabled;
  186. if (!cpumask_and(&valid, &intc->cpumask, dest))
  187. return -EINVAL;
  188. new_cpu = cpumask_any_and(&valid, cpu_online_mask);
  189. if (new_cpu >= nr_cpu_ids)
  190. return -EINVAL;
  191. dest = cpumask_of(new_cpu);
  192. raw_spin_lock_irqsave(&intc->lock, flags);
  193. if (old_cpu != new_cpu) {
  194. enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;
  195. if (enabled)
  196. __bcm6345_l1_mask(d);
  197. cpumask_copy(irq_data_get_affinity_mask(d), dest);
  198. if (enabled)
  199. __bcm6345_l1_unmask(d);
  200. } else {
  201. cpumask_copy(irq_data_get_affinity_mask(d), dest);
  202. }
  203. raw_spin_unlock_irqrestore(&intc->lock, flags);
  204. irq_data_update_effective_affinity(d, cpumask_of(new_cpu));
  205. return IRQ_SET_MASK_OK_NOCOPY;
  206. }
  207. static int __init bcm6345_l1_init_one(struct device_node *dn,
  208. unsigned int idx,
  209. struct bcm6345_l1_chip *intc)
  210. {
  211. struct resource res;
  212. resource_size_t sz;
  213. struct bcm6345_l1_cpu *cpu;
  214. unsigned int i, n_words;
  215. if (of_address_to_resource(dn, idx, &res))
  216. return -EINVAL;
  217. sz = resource_size(&res);
  218. n_words = sz / REG_BYTES_PER_IRQ_WORD;
  219. if (!intc->n_words)
  220. intc->n_words = n_words;
  221. else if (intc->n_words != n_words)
  222. return -EINVAL;
  223. cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
  224. GFP_KERNEL);
  225. if (!cpu)
  226. return -ENOMEM;
  227. cpu->map_base = ioremap(res.start, sz);
  228. if (!cpu->map_base)
  229. return -ENOMEM;
  230. for (i = 0; i < n_words; i++) {
  231. cpu->enable_cache[i] = 0;
  232. __raw_writel(0, cpu->map_base + reg_enable(intc, i));
  233. }
  234. cpu->parent_irq = irq_of_parse_and_map(dn, idx);
  235. if (!cpu->parent_irq) {
  236. pr_err("failed to map parent interrupt %d\n", cpu->parent_irq);
  237. return -EINVAL;
  238. }
  239. irq_set_chained_handler_and_data(cpu->parent_irq,
  240. bcm6345_l1_irq_handle, intc);
  241. return 0;
  242. }
  243. static struct irq_chip bcm6345_l1_irq_chip = {
  244. .name = "bcm6345-l1",
  245. .irq_mask = bcm6345_l1_mask,
  246. .irq_unmask = bcm6345_l1_unmask,
  247. .irq_set_affinity = bcm6345_l1_set_affinity,
  248. };
  249. static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq,
  250. irq_hw_number_t hw_irq)
  251. {
  252. irq_set_chip_and_handler(virq,
  253. &bcm6345_l1_irq_chip, handle_percpu_irq);
  254. irq_set_chip_data(virq, d->host_data);
  255. irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
  256. return 0;
  257. }
  258. static const struct irq_domain_ops bcm6345_l1_domain_ops = {
  259. .xlate = irq_domain_xlate_onecell,
  260. .map = bcm6345_l1_map,
  261. };
  262. static int __init bcm6345_l1_of_init(struct device_node *dn,
  263. struct device_node *parent)
  264. {
  265. struct bcm6345_l1_chip *intc;
  266. unsigned int idx;
  267. int ret;
  268. intc = kzalloc(sizeof(*intc), GFP_KERNEL);
  269. if (!intc)
  270. return -ENOMEM;
  271. for_each_possible_cpu(idx) {
  272. ret = bcm6345_l1_init_one(dn, idx, intc);
  273. if (ret)
  274. pr_err("failed to init intc L1 for cpu %d: %d\n",
  275. idx, ret);
  276. else
  277. cpumask_set_cpu(idx, &intc->cpumask);
  278. }
  279. if (!cpumask_weight(&intc->cpumask)) {
  280. ret = -ENODEV;
  281. goto out_free;
  282. }
  283. raw_spin_lock_init(&intc->lock);
  284. intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
  285. &bcm6345_l1_domain_ops,
  286. intc);
  287. if (!intc->domain) {
  288. ret = -ENOMEM;
  289. goto out_unmap;
  290. }
  291. pr_info("registered BCM6345 L1 intc (IRQs: %d)\n",
  292. IRQS_PER_WORD * intc->n_words);
  293. for_each_cpu(idx, &intc->cpumask) {
  294. struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
  295. pr_info(" CPU%u at MMIO 0x%p (irq = %d)\n", idx,
  296. cpu->map_base, cpu->parent_irq);
  297. }
  298. return 0;
  299. out_unmap:
  300. for_each_possible_cpu(idx) {
  301. struct bcm6345_l1_cpu *cpu = intc->cpus[idx];
  302. if (cpu) {
  303. if (cpu->map_base)
  304. iounmap(cpu->map_base);
  305. kfree(cpu);
  306. }
  307. }
  308. out_free:
  309. kfree(intc);
  310. return ret;
  311. }
  312. IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);