irq-brcmstb-l2.c 8.0 KB

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  1. /*
  2. * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
  3. *
  4. * Copyright (C) 2014-2017 Broadcom
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  16. #include <linux/init.h>
  17. #include <linux/slab.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/of.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/irq.h>
  27. #include <linux/io.h>
  28. #include <linux/irqdomain.h>
  29. #include <linux/irqchip.h>
  30. #include <linux/irqchip/chained_irq.h>
  31. struct brcmstb_intc_init_params {
  32. irq_flow_handler_t handler;
  33. int cpu_status;
  34. int cpu_clear;
  35. int cpu_mask_status;
  36. int cpu_mask_set;
  37. int cpu_mask_clear;
  38. };
  39. /* Register offsets in the L2 latched interrupt controller */
  40. static const struct brcmstb_intc_init_params l2_edge_intc_init = {
  41. .handler = handle_edge_irq,
  42. .cpu_status = 0x00,
  43. .cpu_clear = 0x08,
  44. .cpu_mask_status = 0x0c,
  45. .cpu_mask_set = 0x10,
  46. .cpu_mask_clear = 0x14
  47. };
  48. /* Register offsets in the L2 level interrupt controller */
  49. static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
  50. .handler = handle_level_irq,
  51. .cpu_status = 0x00,
  52. .cpu_clear = -1, /* Register not present */
  53. .cpu_mask_status = 0x04,
  54. .cpu_mask_set = 0x08,
  55. .cpu_mask_clear = 0x0C
  56. };
  57. /* L2 intc private data structure */
  58. struct brcmstb_l2_intc_data {
  59. struct irq_domain *domain;
  60. struct irq_chip_generic *gc;
  61. int status_offset;
  62. int mask_offset;
  63. bool can_wake;
  64. u32 saved_mask; /* for suspend/resume */
  65. };
  66. /**
  67. * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
  68. * @d: irq_data
  69. *
  70. * Chip has separate enable/disable registers instead of a single mask
  71. * register and pending interrupt is acknowledged by setting a bit.
  72. *
  73. * Note: This function is generic and could easily be added to the
  74. * generic irqchip implementation if there ever becomes a will to do so.
  75. * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
  76. *
  77. * e.g.: https://patchwork.kernel.org/patch/9831047/
  78. */
  79. static void brcmstb_l2_mask_and_ack(struct irq_data *d)
  80. {
  81. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  82. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  83. u32 mask = d->mask;
  84. irq_gc_lock(gc);
  85. irq_reg_writel(gc, mask, ct->regs.disable);
  86. *ct->mask_cache &= ~mask;
  87. irq_reg_writel(gc, mask, ct->regs.ack);
  88. irq_gc_unlock(gc);
  89. }
  90. static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
  91. {
  92. struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
  93. struct irq_chip *chip = irq_desc_get_chip(desc);
  94. unsigned int irq;
  95. u32 status;
  96. chained_irq_enter(chip, desc);
  97. status = irq_reg_readl(b->gc, b->status_offset) &
  98. ~(irq_reg_readl(b->gc, b->mask_offset));
  99. if (status == 0) {
  100. raw_spin_lock(&desc->lock);
  101. handle_bad_irq(desc);
  102. raw_spin_unlock(&desc->lock);
  103. goto out;
  104. }
  105. do {
  106. irq = ffs(status) - 1;
  107. status &= ~(1 << irq);
  108. generic_handle_irq(irq_linear_revmap(b->domain, irq));
  109. } while (status);
  110. out:
  111. chained_irq_exit(chip, desc);
  112. }
  113. static void brcmstb_l2_intc_suspend(struct irq_data *d)
  114. {
  115. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  116. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  117. struct brcmstb_l2_intc_data *b = gc->private;
  118. unsigned long flags;
  119. irq_gc_lock_irqsave(gc, flags);
  120. /* Save the current mask */
  121. b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
  122. if (b->can_wake) {
  123. /* Program the wakeup mask */
  124. irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
  125. irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
  126. }
  127. irq_gc_unlock_irqrestore(gc, flags);
  128. }
  129. static void brcmstb_l2_intc_resume(struct irq_data *d)
  130. {
  131. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  132. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  133. struct brcmstb_l2_intc_data *b = gc->private;
  134. unsigned long flags;
  135. irq_gc_lock_irqsave(gc, flags);
  136. if (ct->chip.irq_ack) {
  137. /* Clear unmasked non-wakeup interrupts */
  138. irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
  139. ct->regs.ack);
  140. }
  141. /* Restore the saved mask */
  142. irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
  143. irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
  144. irq_gc_unlock_irqrestore(gc, flags);
  145. }
  146. static int __init brcmstb_l2_intc_of_init(struct device_node *np,
  147. struct device_node *parent,
  148. const struct brcmstb_intc_init_params
  149. *init_params)
  150. {
  151. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  152. struct brcmstb_l2_intc_data *data;
  153. struct irq_chip_type *ct;
  154. int ret;
  155. unsigned int flags;
  156. int parent_irq;
  157. void __iomem *base;
  158. data = kzalloc(sizeof(*data), GFP_KERNEL);
  159. if (!data)
  160. return -ENOMEM;
  161. base = of_iomap(np, 0);
  162. if (!base) {
  163. pr_err("failed to remap intc L2 registers\n");
  164. ret = -ENOMEM;
  165. goto out_free;
  166. }
  167. /* Disable all interrupts by default */
  168. writel(0xffffffff, base + init_params->cpu_mask_set);
  169. /* Wakeup interrupts may be retained from S5 (cold boot) */
  170. data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
  171. if (!data->can_wake && (init_params->cpu_clear >= 0))
  172. writel(0xffffffff, base + init_params->cpu_clear);
  173. parent_irq = irq_of_parse_and_map(np, 0);
  174. if (!parent_irq) {
  175. pr_err("failed to find parent interrupt\n");
  176. ret = -EINVAL;
  177. goto out_unmap;
  178. }
  179. data->domain = irq_domain_add_linear(np, 32,
  180. &irq_generic_chip_ops, NULL);
  181. if (!data->domain) {
  182. ret = -ENOMEM;
  183. goto out_unmap;
  184. }
  185. /* MIPS chips strapped for BE will automagically configure the
  186. * peripheral registers for CPU-native byte order.
  187. */
  188. flags = 0;
  189. if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  190. flags |= IRQ_GC_BE_IO;
  191. /* Allocate a single Generic IRQ chip for this node */
  192. ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
  193. np->full_name, init_params->handler, clr, 0, flags);
  194. if (ret) {
  195. pr_err("failed to allocate generic irq chip\n");
  196. goto out_free_domain;
  197. }
  198. /* Set the IRQ chaining logic */
  199. irq_set_chained_handler_and_data(parent_irq,
  200. brcmstb_l2_intc_irq_handle, data);
  201. data->gc = irq_get_domain_generic_chip(data->domain, 0);
  202. data->gc->reg_base = base;
  203. data->gc->private = data;
  204. data->status_offset = init_params->cpu_status;
  205. data->mask_offset = init_params->cpu_mask_status;
  206. ct = data->gc->chip_types;
  207. if (init_params->cpu_clear >= 0) {
  208. ct->regs.ack = init_params->cpu_clear;
  209. ct->chip.irq_ack = irq_gc_ack_set_bit;
  210. ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
  211. } else {
  212. /* No Ack - but still slightly more efficient to define this */
  213. ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
  214. }
  215. ct->chip.irq_mask = irq_gc_mask_disable_reg;
  216. ct->regs.disable = init_params->cpu_mask_set;
  217. ct->regs.mask = init_params->cpu_mask_status;
  218. ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
  219. ct->regs.enable = init_params->cpu_mask_clear;
  220. ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
  221. ct->chip.irq_resume = brcmstb_l2_intc_resume;
  222. ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
  223. if (data->can_wake) {
  224. /* This IRQ chip can wake the system, set all child interrupts
  225. * in wake_enabled mask
  226. */
  227. data->gc->wake_enabled = 0xffffffff;
  228. ct->chip.irq_set_wake = irq_gc_set_wake;
  229. }
  230. return 0;
  231. out_free_domain:
  232. irq_domain_remove(data->domain);
  233. out_unmap:
  234. iounmap(base);
  235. out_free:
  236. kfree(data);
  237. return ret;
  238. }
  239. int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
  240. struct device_node *parent)
  241. {
  242. return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
  243. }
  244. IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
  245. int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
  246. struct device_node *parent)
  247. {
  248. return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
  249. }
  250. IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
  251. brcmstb_l2_lvl_intc_of_init);