irq-imx-gpcv2.c 6.2 KB

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  1. /*
  2. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/of_address.h>
  9. #include <linux/of_irq.h>
  10. #include <linux/slab.h>
  11. #include <linux/irqchip.h>
  12. #include <linux/syscore_ops.h>
  13. #define IMR_NUM 4
  14. #define GPC_MAX_IRQS (IMR_NUM * 32)
  15. #define GPC_IMR1_CORE0 0x30
  16. #define GPC_IMR1_CORE1 0x40
  17. struct gpcv2_irqchip_data {
  18. struct raw_spinlock rlock;
  19. void __iomem *gpc_base;
  20. u32 wakeup_sources[IMR_NUM];
  21. u32 saved_irq_mask[IMR_NUM];
  22. u32 cpu2wakeup;
  23. };
  24. static struct gpcv2_irqchip_data *imx_gpcv2_instance;
  25. static int gpcv2_wakeup_source_save(void)
  26. {
  27. struct gpcv2_irqchip_data *cd;
  28. void __iomem *reg;
  29. int i;
  30. cd = imx_gpcv2_instance;
  31. if (!cd)
  32. return 0;
  33. for (i = 0; i < IMR_NUM; i++) {
  34. reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
  35. cd->saved_irq_mask[i] = readl_relaxed(reg);
  36. writel_relaxed(cd->wakeup_sources[i], reg);
  37. }
  38. return 0;
  39. }
  40. static void gpcv2_wakeup_source_restore(void)
  41. {
  42. struct gpcv2_irqchip_data *cd;
  43. void __iomem *reg;
  44. int i;
  45. cd = imx_gpcv2_instance;
  46. if (!cd)
  47. return;
  48. for (i = 0; i < IMR_NUM; i++) {
  49. reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
  50. writel_relaxed(cd->saved_irq_mask[i], reg);
  51. }
  52. }
  53. static struct syscore_ops imx_gpcv2_syscore_ops = {
  54. .suspend = gpcv2_wakeup_source_save,
  55. .resume = gpcv2_wakeup_source_restore,
  56. };
  57. static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
  58. {
  59. struct gpcv2_irqchip_data *cd = d->chip_data;
  60. unsigned int idx = d->hwirq / 32;
  61. unsigned long flags;
  62. void __iomem *reg;
  63. u32 mask, val;
  64. raw_spin_lock_irqsave(&cd->rlock, flags);
  65. reg = cd->gpc_base + cd->cpu2wakeup + idx * 4;
  66. mask = 1 << d->hwirq % 32;
  67. val = cd->wakeup_sources[idx];
  68. cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
  69. raw_spin_unlock_irqrestore(&cd->rlock, flags);
  70. /*
  71. * Do *not* call into the parent, as the GIC doesn't have any
  72. * wake-up facility...
  73. */
  74. return 0;
  75. }
  76. static void imx_gpcv2_irq_unmask(struct irq_data *d)
  77. {
  78. struct gpcv2_irqchip_data *cd = d->chip_data;
  79. void __iomem *reg;
  80. u32 val;
  81. raw_spin_lock(&cd->rlock);
  82. reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
  83. val = readl_relaxed(reg);
  84. val &= ~(1 << d->hwirq % 32);
  85. writel_relaxed(val, reg);
  86. raw_spin_unlock(&cd->rlock);
  87. irq_chip_unmask_parent(d);
  88. }
  89. static void imx_gpcv2_irq_mask(struct irq_data *d)
  90. {
  91. struct gpcv2_irqchip_data *cd = d->chip_data;
  92. void __iomem *reg;
  93. u32 val;
  94. raw_spin_lock(&cd->rlock);
  95. reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
  96. val = readl_relaxed(reg);
  97. val |= 1 << (d->hwirq % 32);
  98. writel_relaxed(val, reg);
  99. raw_spin_unlock(&cd->rlock);
  100. irq_chip_mask_parent(d);
  101. }
  102. static struct irq_chip gpcv2_irqchip_data_chip = {
  103. .name = "GPCv2",
  104. .irq_eoi = irq_chip_eoi_parent,
  105. .irq_mask = imx_gpcv2_irq_mask,
  106. .irq_unmask = imx_gpcv2_irq_unmask,
  107. .irq_set_wake = imx_gpcv2_irq_set_wake,
  108. .irq_retrigger = irq_chip_retrigger_hierarchy,
  109. .irq_set_type = irq_chip_set_type_parent,
  110. #ifdef CONFIG_SMP
  111. .irq_set_affinity = irq_chip_set_affinity_parent,
  112. #endif
  113. };
  114. static int imx_gpcv2_domain_translate(struct irq_domain *d,
  115. struct irq_fwspec *fwspec,
  116. unsigned long *hwirq,
  117. unsigned int *type)
  118. {
  119. if (is_of_node(fwspec->fwnode)) {
  120. if (fwspec->param_count != 3)
  121. return -EINVAL;
  122. /* No PPI should point to this domain */
  123. if (fwspec->param[0] != 0)
  124. return -EINVAL;
  125. *hwirq = fwspec->param[1];
  126. *type = fwspec->param[2];
  127. return 0;
  128. }
  129. return -EINVAL;
  130. }
  131. static int imx_gpcv2_domain_alloc(struct irq_domain *domain,
  132. unsigned int irq, unsigned int nr_irqs,
  133. void *data)
  134. {
  135. struct irq_fwspec *fwspec = data;
  136. struct irq_fwspec parent_fwspec;
  137. irq_hw_number_t hwirq;
  138. unsigned int type;
  139. int err;
  140. int i;
  141. err = imx_gpcv2_domain_translate(domain, fwspec, &hwirq, &type);
  142. if (err)
  143. return err;
  144. if (hwirq >= GPC_MAX_IRQS)
  145. return -EINVAL;
  146. for (i = 0; i < nr_irqs; i++) {
  147. irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
  148. &gpcv2_irqchip_data_chip, domain->host_data);
  149. }
  150. parent_fwspec = *fwspec;
  151. parent_fwspec.fwnode = domain->parent->fwnode;
  152. return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs,
  153. &parent_fwspec);
  154. }
  155. static const struct irq_domain_ops gpcv2_irqchip_data_domain_ops = {
  156. .translate = imx_gpcv2_domain_translate,
  157. .alloc = imx_gpcv2_domain_alloc,
  158. .free = irq_domain_free_irqs_common,
  159. };
  160. static int __init imx_gpcv2_irqchip_init(struct device_node *node,
  161. struct device_node *parent)
  162. {
  163. struct irq_domain *parent_domain, *domain;
  164. struct gpcv2_irqchip_data *cd;
  165. int i;
  166. if (!parent) {
  167. pr_err("%pOF: no parent, giving up\n", node);
  168. return -ENODEV;
  169. }
  170. parent_domain = irq_find_host(parent);
  171. if (!parent_domain) {
  172. pr_err("%pOF: unable to get parent domain\n", node);
  173. return -ENXIO;
  174. }
  175. cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL);
  176. if (!cd) {
  177. pr_err("kzalloc failed!\n");
  178. return -ENOMEM;
  179. }
  180. raw_spin_lock_init(&cd->rlock);
  181. cd->gpc_base = of_iomap(node, 0);
  182. if (!cd->gpc_base) {
  183. pr_err("fsl-gpcv2: unable to map gpc registers\n");
  184. kfree(cd);
  185. return -ENOMEM;
  186. }
  187. domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
  188. node, &gpcv2_irqchip_data_domain_ops, cd);
  189. if (!domain) {
  190. iounmap(cd->gpc_base);
  191. kfree(cd);
  192. return -ENOMEM;
  193. }
  194. irq_set_default_host(domain);
  195. /* Initially mask all interrupts */
  196. for (i = 0; i < IMR_NUM; i++) {
  197. writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4);
  198. writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4);
  199. cd->wakeup_sources[i] = ~0;
  200. }
  201. /* Let CORE0 as the default CPU to wake up by GPC */
  202. cd->cpu2wakeup = GPC_IMR1_CORE0;
  203. /*
  204. * Due to hardware design failure, need to make sure GPR
  205. * interrupt(#32) is unmasked during RUN mode to avoid entering
  206. * DSM by mistake.
  207. */
  208. writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
  209. imx_gpcv2_instance = cd;
  210. register_syscore_ops(&imx_gpcv2_syscore_ops);
  211. /*
  212. * Clear the OF_POPULATED flag set in of_irq_init so that
  213. * later the GPC power domain driver will not be skipped.
  214. */
  215. of_node_clear_flag(node, OF_POPULATED);
  216. return 0;
  217. }
  218. IRQCHIP_DECLARE(imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init);