irq-sifive-plic.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017 SiFive
  4. * Copyright (C) 2018 Christoph Hellwig
  5. */
  6. #define pr_fmt(fmt) "plic: " fmt
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/irq.h>
  10. #include <linux/irqchip.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/spinlock.h>
  18. /*
  19. * This driver implements a version of the RISC-V PLIC with the actual layout
  20. * specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
  21. *
  22. * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
  23. *
  24. * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
  25. * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
  26. * Spec.
  27. */
  28. #define MAX_DEVICES 1024
  29. #define MAX_CONTEXTS 15872
  30. /*
  31. * Each interrupt source has a priority register associated with it.
  32. * We always hardwire it to one in Linux.
  33. */
  34. #define PRIORITY_BASE 0
  35. #define PRIORITY_PER_ID 4
  36. /*
  37. * Each hart context has a vector of interrupt enable bits associated with it.
  38. * There's one bit for each interrupt source.
  39. */
  40. #define ENABLE_BASE 0x2000
  41. #define ENABLE_PER_HART 0x80
  42. /*
  43. * Each hart context has a set of control registers associated with it. Right
  44. * now there's only two: a source priority threshold over which the hart will
  45. * take an interrupt, and a register to claim interrupts.
  46. */
  47. #define CONTEXT_BASE 0x200000
  48. #define CONTEXT_PER_HART 0x1000
  49. #define CONTEXT_THRESHOLD 0x00
  50. #define CONTEXT_CLAIM 0x04
  51. static void __iomem *plic_regs;
  52. struct plic_handler {
  53. bool present;
  54. int ctxid;
  55. };
  56. static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
  57. static inline void __iomem *plic_hart_offset(int ctxid)
  58. {
  59. return plic_regs + CONTEXT_BASE + ctxid * CONTEXT_PER_HART;
  60. }
  61. static inline u32 __iomem *plic_enable_base(int ctxid)
  62. {
  63. return plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART;
  64. }
  65. /*
  66. * Protect mask operations on the registers given that we can't assume that
  67. * atomic memory operations work on them.
  68. */
  69. static DEFINE_RAW_SPINLOCK(plic_toggle_lock);
  70. static inline void plic_toggle(int ctxid, int hwirq, int enable)
  71. {
  72. u32 __iomem *reg = plic_enable_base(ctxid) + (hwirq / 32);
  73. u32 hwirq_mask = 1 << (hwirq % 32);
  74. raw_spin_lock(&plic_toggle_lock);
  75. if (enable)
  76. writel(readl(reg) | hwirq_mask, reg);
  77. else
  78. writel(readl(reg) & ~hwirq_mask, reg);
  79. raw_spin_unlock(&plic_toggle_lock);
  80. }
  81. static inline void plic_irq_toggle(struct irq_data *d, int enable)
  82. {
  83. int cpu;
  84. writel(enable, plic_regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
  85. for_each_cpu(cpu, irq_data_get_affinity_mask(d)) {
  86. struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
  87. if (handler->present)
  88. plic_toggle(handler->ctxid, d->hwirq, enable);
  89. }
  90. }
  91. static void plic_irq_enable(struct irq_data *d)
  92. {
  93. plic_irq_toggle(d, 1);
  94. }
  95. static void plic_irq_disable(struct irq_data *d)
  96. {
  97. plic_irq_toggle(d, 0);
  98. }
  99. static struct irq_chip plic_chip = {
  100. .name = "SiFive PLIC",
  101. /*
  102. * There is no need to mask/unmask PLIC interrupts. They are "masked"
  103. * by reading claim and "unmasked" when writing it back.
  104. */
  105. .irq_enable = plic_irq_enable,
  106. .irq_disable = plic_irq_disable,
  107. };
  108. static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
  109. irq_hw_number_t hwirq)
  110. {
  111. irq_set_chip_and_handler(irq, &plic_chip, handle_simple_irq);
  112. irq_set_chip_data(irq, NULL);
  113. irq_set_noprobe(irq);
  114. return 0;
  115. }
  116. static const struct irq_domain_ops plic_irqdomain_ops = {
  117. .map = plic_irqdomain_map,
  118. .xlate = irq_domain_xlate_onecell,
  119. };
  120. static struct irq_domain *plic_irqdomain;
  121. /*
  122. * Handling an interrupt is a two-step process: first you claim the interrupt
  123. * by reading the claim register, then you complete the interrupt by writing
  124. * that source ID back to the same claim register. This automatically enables
  125. * and disables the interrupt, so there's nothing else to do.
  126. */
  127. static void plic_handle_irq(struct pt_regs *regs)
  128. {
  129. struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
  130. void __iomem *claim = plic_hart_offset(handler->ctxid) + CONTEXT_CLAIM;
  131. irq_hw_number_t hwirq;
  132. WARN_ON_ONCE(!handler->present);
  133. csr_clear(sie, SIE_SEIE);
  134. while ((hwirq = readl(claim))) {
  135. int irq = irq_find_mapping(plic_irqdomain, hwirq);
  136. if (unlikely(irq <= 0))
  137. pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
  138. hwirq);
  139. else
  140. generic_handle_irq(irq);
  141. writel(hwirq, claim);
  142. }
  143. csr_set(sie, SIE_SEIE);
  144. }
  145. /*
  146. * Walk up the DT tree until we find an active RISC-V core (HART) node and
  147. * extract the cpuid from it.
  148. */
  149. static int plic_find_hart_id(struct device_node *node)
  150. {
  151. for (; node; node = node->parent) {
  152. if (of_device_is_compatible(node, "riscv"))
  153. return riscv_of_processor_hart(node);
  154. }
  155. return -1;
  156. }
  157. static int __init plic_init(struct device_node *node,
  158. struct device_node *parent)
  159. {
  160. int error = 0, nr_handlers, nr_mapped = 0, i;
  161. u32 nr_irqs;
  162. if (plic_regs) {
  163. pr_warn("PLIC already present.\n");
  164. return -ENXIO;
  165. }
  166. plic_regs = of_iomap(node, 0);
  167. if (WARN_ON(!plic_regs))
  168. return -EIO;
  169. error = -EINVAL;
  170. of_property_read_u32(node, "riscv,ndev", &nr_irqs);
  171. if (WARN_ON(!nr_irqs))
  172. goto out_iounmap;
  173. nr_handlers = of_irq_count(node);
  174. if (WARN_ON(!nr_handlers))
  175. goto out_iounmap;
  176. if (WARN_ON(nr_handlers < num_possible_cpus()))
  177. goto out_iounmap;
  178. error = -ENOMEM;
  179. plic_irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
  180. &plic_irqdomain_ops, NULL);
  181. if (WARN_ON(!plic_irqdomain))
  182. goto out_iounmap;
  183. for (i = 0; i < nr_handlers; i++) {
  184. struct of_phandle_args parent;
  185. struct plic_handler *handler;
  186. irq_hw_number_t hwirq;
  187. int cpu;
  188. if (of_irq_parse_one(node, i, &parent)) {
  189. pr_err("failed to parse parent for context %d.\n", i);
  190. continue;
  191. }
  192. /* skip context holes */
  193. if (parent.args[0] == -1)
  194. continue;
  195. cpu = plic_find_hart_id(parent.np);
  196. if (cpu < 0) {
  197. pr_warn("failed to parse hart ID for context %d.\n", i);
  198. continue;
  199. }
  200. handler = per_cpu_ptr(&plic_handlers, cpu);
  201. handler->present = true;
  202. handler->ctxid = i;
  203. /* priority must be > threshold to trigger an interrupt */
  204. writel(0, plic_hart_offset(i) + CONTEXT_THRESHOLD);
  205. for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
  206. plic_toggle(i, hwirq, 0);
  207. nr_mapped++;
  208. }
  209. pr_info("mapped %d interrupts to %d (out of %d) handlers.\n",
  210. nr_irqs, nr_mapped, nr_handlers);
  211. set_handle_irq(plic_handle_irq);
  212. return 0;
  213. out_iounmap:
  214. iounmap(plic_regs);
  215. return error;
  216. }
  217. IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
  218. IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */