irq-stm32-exti.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Maxime Coquelin 2015
  4. * Copyright (C) STMicroelectronics 2017
  5. * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/irq.h>
  11. #include <linux/irqchip.h>
  12. #include <linux/irqchip/chained_irq.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/syscore_ops.h>
  17. #include <dt-bindings/interrupt-controller/arm-gic.h>
  18. #define IRQS_PER_BANK 32
  19. struct stm32_exti_bank {
  20. u32 imr_ofst;
  21. u32 emr_ofst;
  22. u32 rtsr_ofst;
  23. u32 ftsr_ofst;
  24. u32 swier_ofst;
  25. u32 rpr_ofst;
  26. u32 fpr_ofst;
  27. };
  28. #define UNDEF_REG ~0
  29. struct stm32_desc_irq {
  30. u32 exti;
  31. u32 irq_parent;
  32. };
  33. struct stm32_exti_drv_data {
  34. const struct stm32_exti_bank **exti_banks;
  35. const struct stm32_desc_irq *desc_irqs;
  36. u32 bank_nr;
  37. u32 irq_nr;
  38. };
  39. struct stm32_exti_chip_data {
  40. struct stm32_exti_host_data *host_data;
  41. const struct stm32_exti_bank *reg_bank;
  42. struct raw_spinlock rlock;
  43. u32 wake_active;
  44. u32 mask_cache;
  45. u32 rtsr_cache;
  46. u32 ftsr_cache;
  47. };
  48. struct stm32_exti_host_data {
  49. void __iomem *base;
  50. struct stm32_exti_chip_data *chips_data;
  51. const struct stm32_exti_drv_data *drv_data;
  52. };
  53. static struct stm32_exti_host_data *stm32_host_data;
  54. static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
  55. .imr_ofst = 0x00,
  56. .emr_ofst = 0x04,
  57. .rtsr_ofst = 0x08,
  58. .ftsr_ofst = 0x0C,
  59. .swier_ofst = 0x10,
  60. .rpr_ofst = 0x14,
  61. .fpr_ofst = UNDEF_REG,
  62. };
  63. static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
  64. &stm32f4xx_exti_b1,
  65. };
  66. static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
  67. .exti_banks = stm32f4xx_exti_banks,
  68. .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
  69. };
  70. static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
  71. .imr_ofst = 0x80,
  72. .emr_ofst = 0x84,
  73. .rtsr_ofst = 0x00,
  74. .ftsr_ofst = 0x04,
  75. .swier_ofst = 0x08,
  76. .rpr_ofst = 0x88,
  77. .fpr_ofst = UNDEF_REG,
  78. };
  79. static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
  80. .imr_ofst = 0x90,
  81. .emr_ofst = 0x94,
  82. .rtsr_ofst = 0x20,
  83. .ftsr_ofst = 0x24,
  84. .swier_ofst = 0x28,
  85. .rpr_ofst = 0x98,
  86. .fpr_ofst = UNDEF_REG,
  87. };
  88. static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
  89. .imr_ofst = 0xA0,
  90. .emr_ofst = 0xA4,
  91. .rtsr_ofst = 0x40,
  92. .ftsr_ofst = 0x44,
  93. .swier_ofst = 0x48,
  94. .rpr_ofst = 0xA8,
  95. .fpr_ofst = UNDEF_REG,
  96. };
  97. static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
  98. &stm32h7xx_exti_b1,
  99. &stm32h7xx_exti_b2,
  100. &stm32h7xx_exti_b3,
  101. };
  102. static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
  103. .exti_banks = stm32h7xx_exti_banks,
  104. .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
  105. };
  106. static const struct stm32_exti_bank stm32mp1_exti_b1 = {
  107. .imr_ofst = 0x80,
  108. .emr_ofst = 0x84,
  109. .rtsr_ofst = 0x00,
  110. .ftsr_ofst = 0x04,
  111. .swier_ofst = 0x08,
  112. .rpr_ofst = 0x0C,
  113. .fpr_ofst = 0x10,
  114. };
  115. static const struct stm32_exti_bank stm32mp1_exti_b2 = {
  116. .imr_ofst = 0x90,
  117. .emr_ofst = 0x94,
  118. .rtsr_ofst = 0x20,
  119. .ftsr_ofst = 0x24,
  120. .swier_ofst = 0x28,
  121. .rpr_ofst = 0x2C,
  122. .fpr_ofst = 0x30,
  123. };
  124. static const struct stm32_exti_bank stm32mp1_exti_b3 = {
  125. .imr_ofst = 0xA0,
  126. .emr_ofst = 0xA4,
  127. .rtsr_ofst = 0x40,
  128. .ftsr_ofst = 0x44,
  129. .swier_ofst = 0x48,
  130. .rpr_ofst = 0x4C,
  131. .fpr_ofst = 0x50,
  132. };
  133. static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
  134. &stm32mp1_exti_b1,
  135. &stm32mp1_exti_b2,
  136. &stm32mp1_exti_b3,
  137. };
  138. static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
  139. { .exti = 0, .irq_parent = 6 },
  140. { .exti = 1, .irq_parent = 7 },
  141. { .exti = 2, .irq_parent = 8 },
  142. { .exti = 3, .irq_parent = 9 },
  143. { .exti = 4, .irq_parent = 10 },
  144. { .exti = 5, .irq_parent = 23 },
  145. { .exti = 6, .irq_parent = 64 },
  146. { .exti = 7, .irq_parent = 65 },
  147. { .exti = 8, .irq_parent = 66 },
  148. { .exti = 9, .irq_parent = 67 },
  149. { .exti = 10, .irq_parent = 40 },
  150. { .exti = 11, .irq_parent = 42 },
  151. { .exti = 12, .irq_parent = 76 },
  152. { .exti = 13, .irq_parent = 77 },
  153. { .exti = 14, .irq_parent = 121 },
  154. { .exti = 15, .irq_parent = 127 },
  155. { .exti = 16, .irq_parent = 1 },
  156. { .exti = 65, .irq_parent = 144 },
  157. { .exti = 68, .irq_parent = 143 },
  158. { .exti = 73, .irq_parent = 129 },
  159. };
  160. static const struct stm32_exti_drv_data stm32mp1_drv_data = {
  161. .exti_banks = stm32mp1_exti_banks,
  162. .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
  163. .desc_irqs = stm32mp1_desc_irq,
  164. .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
  165. };
  166. static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data,
  167. irq_hw_number_t hwirq)
  168. {
  169. const struct stm32_desc_irq *desc_irq;
  170. int i;
  171. if (!drv_data->desc_irqs)
  172. return -EINVAL;
  173. for (i = 0; i < drv_data->irq_nr; i++) {
  174. desc_irq = &drv_data->desc_irqs[i];
  175. if (desc_irq->exti == hwirq)
  176. return desc_irq->irq_parent;
  177. }
  178. return -EINVAL;
  179. }
  180. static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
  181. {
  182. struct stm32_exti_chip_data *chip_data = gc->private;
  183. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  184. unsigned long pending;
  185. pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
  186. if (stm32_bank->fpr_ofst != UNDEF_REG)
  187. pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
  188. return pending;
  189. }
  190. static void stm32_irq_handler(struct irq_desc *desc)
  191. {
  192. struct irq_domain *domain = irq_desc_get_handler_data(desc);
  193. struct irq_chip *chip = irq_desc_get_chip(desc);
  194. unsigned int virq, nbanks = domain->gc->num_chips;
  195. struct irq_chip_generic *gc;
  196. unsigned long pending;
  197. int n, i, irq_base = 0;
  198. chained_irq_enter(chip, desc);
  199. for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
  200. gc = irq_get_domain_generic_chip(domain, irq_base);
  201. while ((pending = stm32_exti_pending(gc))) {
  202. for_each_set_bit(n, &pending, IRQS_PER_BANK) {
  203. virq = irq_find_mapping(domain, irq_base + n);
  204. generic_handle_irq(virq);
  205. }
  206. }
  207. }
  208. chained_irq_exit(chip, desc);
  209. }
  210. static int stm32_exti_set_type(struct irq_data *d,
  211. unsigned int type, u32 *rtsr, u32 *ftsr)
  212. {
  213. u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
  214. switch (type) {
  215. case IRQ_TYPE_EDGE_RISING:
  216. *rtsr |= mask;
  217. *ftsr &= ~mask;
  218. break;
  219. case IRQ_TYPE_EDGE_FALLING:
  220. *rtsr &= ~mask;
  221. *ftsr |= mask;
  222. break;
  223. case IRQ_TYPE_EDGE_BOTH:
  224. *rtsr |= mask;
  225. *ftsr |= mask;
  226. break;
  227. default:
  228. return -EINVAL;
  229. }
  230. return 0;
  231. }
  232. static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
  233. {
  234. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  235. struct stm32_exti_chip_data *chip_data = gc->private;
  236. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  237. u32 rtsr, ftsr;
  238. int err;
  239. irq_gc_lock(gc);
  240. rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
  241. ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
  242. err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
  243. if (err) {
  244. irq_gc_unlock(gc);
  245. return err;
  246. }
  247. irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
  248. irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
  249. irq_gc_unlock(gc);
  250. return 0;
  251. }
  252. static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
  253. u32 wake_active)
  254. {
  255. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  256. void __iomem *base = chip_data->host_data->base;
  257. /* save rtsr, ftsr registers */
  258. chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
  259. chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
  260. writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
  261. }
  262. static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
  263. u32 mask_cache)
  264. {
  265. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  266. void __iomem *base = chip_data->host_data->base;
  267. /* restore rtsr, ftsr, registers */
  268. writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
  269. writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
  270. writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
  271. }
  272. static void stm32_irq_suspend(struct irq_chip_generic *gc)
  273. {
  274. struct stm32_exti_chip_data *chip_data = gc->private;
  275. irq_gc_lock(gc);
  276. stm32_chip_suspend(chip_data, gc->wake_active);
  277. irq_gc_unlock(gc);
  278. }
  279. static void stm32_irq_resume(struct irq_chip_generic *gc)
  280. {
  281. struct stm32_exti_chip_data *chip_data = gc->private;
  282. irq_gc_lock(gc);
  283. stm32_chip_resume(chip_data, gc->mask_cache);
  284. irq_gc_unlock(gc);
  285. }
  286. static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
  287. unsigned int nr_irqs, void *data)
  288. {
  289. struct irq_fwspec *fwspec = data;
  290. irq_hw_number_t hwirq;
  291. hwirq = fwspec->param[0];
  292. irq_map_generic_chip(d, virq, hwirq);
  293. return 0;
  294. }
  295. static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
  296. unsigned int nr_irqs)
  297. {
  298. struct irq_data *data = irq_domain_get_irq_data(d, virq);
  299. irq_domain_reset_irq_data(data);
  300. }
  301. static const struct irq_domain_ops irq_exti_domain_ops = {
  302. .map = irq_map_generic_chip,
  303. .alloc = stm32_exti_alloc,
  304. .free = stm32_exti_free,
  305. };
  306. static void stm32_irq_ack(struct irq_data *d)
  307. {
  308. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  309. struct stm32_exti_chip_data *chip_data = gc->private;
  310. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  311. irq_gc_lock(gc);
  312. irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
  313. if (stm32_bank->fpr_ofst != UNDEF_REG)
  314. irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
  315. irq_gc_unlock(gc);
  316. }
  317. /* directly set the target bit without reading first. */
  318. static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
  319. {
  320. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  321. void __iomem *base = chip_data->host_data->base;
  322. u32 val = BIT(d->hwirq % IRQS_PER_BANK);
  323. writel_relaxed(val, base + reg);
  324. }
  325. static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
  326. {
  327. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  328. void __iomem *base = chip_data->host_data->base;
  329. u32 val;
  330. val = readl_relaxed(base + reg);
  331. val |= BIT(d->hwirq % IRQS_PER_BANK);
  332. writel_relaxed(val, base + reg);
  333. return val;
  334. }
  335. static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
  336. {
  337. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  338. void __iomem *base = chip_data->host_data->base;
  339. u32 val;
  340. val = readl_relaxed(base + reg);
  341. val &= ~BIT(d->hwirq % IRQS_PER_BANK);
  342. writel_relaxed(val, base + reg);
  343. return val;
  344. }
  345. static void stm32_exti_h_eoi(struct irq_data *d)
  346. {
  347. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  348. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  349. raw_spin_lock(&chip_data->rlock);
  350. stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
  351. if (stm32_bank->fpr_ofst != UNDEF_REG)
  352. stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
  353. raw_spin_unlock(&chip_data->rlock);
  354. if (d->parent_data->chip)
  355. irq_chip_eoi_parent(d);
  356. }
  357. static void stm32_exti_h_mask(struct irq_data *d)
  358. {
  359. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  360. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  361. raw_spin_lock(&chip_data->rlock);
  362. chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
  363. raw_spin_unlock(&chip_data->rlock);
  364. if (d->parent_data->chip)
  365. irq_chip_mask_parent(d);
  366. }
  367. static void stm32_exti_h_unmask(struct irq_data *d)
  368. {
  369. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  370. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  371. raw_spin_lock(&chip_data->rlock);
  372. chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
  373. raw_spin_unlock(&chip_data->rlock);
  374. if (d->parent_data->chip)
  375. irq_chip_unmask_parent(d);
  376. }
  377. static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
  378. {
  379. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  380. const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
  381. void __iomem *base = chip_data->host_data->base;
  382. u32 rtsr, ftsr;
  383. int err;
  384. raw_spin_lock(&chip_data->rlock);
  385. rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
  386. ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
  387. err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
  388. if (err) {
  389. raw_spin_unlock(&chip_data->rlock);
  390. return err;
  391. }
  392. writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
  393. writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
  394. raw_spin_unlock(&chip_data->rlock);
  395. return 0;
  396. }
  397. static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
  398. {
  399. struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
  400. u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
  401. raw_spin_lock(&chip_data->rlock);
  402. if (on)
  403. chip_data->wake_active |= mask;
  404. else
  405. chip_data->wake_active &= ~mask;
  406. raw_spin_unlock(&chip_data->rlock);
  407. return 0;
  408. }
  409. static int stm32_exti_h_set_affinity(struct irq_data *d,
  410. const struct cpumask *dest, bool force)
  411. {
  412. if (d->parent_data->chip)
  413. return irq_chip_set_affinity_parent(d, dest, force);
  414. return -EINVAL;
  415. }
  416. #ifdef CONFIG_PM
  417. static int stm32_exti_h_suspend(void)
  418. {
  419. struct stm32_exti_chip_data *chip_data;
  420. int i;
  421. for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
  422. chip_data = &stm32_host_data->chips_data[i];
  423. raw_spin_lock(&chip_data->rlock);
  424. stm32_chip_suspend(chip_data, chip_data->wake_active);
  425. raw_spin_unlock(&chip_data->rlock);
  426. }
  427. return 0;
  428. }
  429. static void stm32_exti_h_resume(void)
  430. {
  431. struct stm32_exti_chip_data *chip_data;
  432. int i;
  433. for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
  434. chip_data = &stm32_host_data->chips_data[i];
  435. raw_spin_lock(&chip_data->rlock);
  436. stm32_chip_resume(chip_data, chip_data->mask_cache);
  437. raw_spin_unlock(&chip_data->rlock);
  438. }
  439. }
  440. static struct syscore_ops stm32_exti_h_syscore_ops = {
  441. .suspend = stm32_exti_h_suspend,
  442. .resume = stm32_exti_h_resume,
  443. };
  444. static void stm32_exti_h_syscore_init(void)
  445. {
  446. register_syscore_ops(&stm32_exti_h_syscore_ops);
  447. }
  448. #else
  449. static inline void stm32_exti_h_syscore_init(void) {}
  450. #endif
  451. static struct irq_chip stm32_exti_h_chip = {
  452. .name = "stm32-exti-h",
  453. .irq_eoi = stm32_exti_h_eoi,
  454. .irq_mask = stm32_exti_h_mask,
  455. .irq_unmask = stm32_exti_h_unmask,
  456. .irq_retrigger = irq_chip_retrigger_hierarchy,
  457. .irq_set_type = stm32_exti_h_set_type,
  458. .irq_set_wake = stm32_exti_h_set_wake,
  459. .flags = IRQCHIP_MASK_ON_SUSPEND,
  460. .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
  461. };
  462. static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
  463. unsigned int virq,
  464. unsigned int nr_irqs, void *data)
  465. {
  466. struct stm32_exti_host_data *host_data = dm->host_data;
  467. struct stm32_exti_chip_data *chip_data;
  468. struct irq_fwspec *fwspec = data;
  469. struct irq_fwspec p_fwspec;
  470. irq_hw_number_t hwirq;
  471. int p_irq, bank;
  472. hwirq = fwspec->param[0];
  473. bank = hwirq / IRQS_PER_BANK;
  474. chip_data = &host_data->chips_data[bank];
  475. irq_domain_set_hwirq_and_chip(dm, virq, hwirq,
  476. &stm32_exti_h_chip, chip_data);
  477. p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq);
  478. if (p_irq >= 0) {
  479. p_fwspec.fwnode = dm->parent->fwnode;
  480. p_fwspec.param_count = 3;
  481. p_fwspec.param[0] = GIC_SPI;
  482. p_fwspec.param[1] = p_irq;
  483. p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
  484. return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
  485. }
  486. return 0;
  487. }
  488. static struct
  489. stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
  490. struct device_node *node)
  491. {
  492. struct stm32_exti_host_data *host_data;
  493. host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
  494. if (!host_data)
  495. return NULL;
  496. host_data->drv_data = dd;
  497. host_data->chips_data = kcalloc(dd->bank_nr,
  498. sizeof(struct stm32_exti_chip_data),
  499. GFP_KERNEL);
  500. if (!host_data->chips_data)
  501. goto free_host_data;
  502. host_data->base = of_iomap(node, 0);
  503. if (!host_data->base) {
  504. pr_err("%pOF: Unable to map registers\n", node);
  505. goto free_chips_data;
  506. }
  507. stm32_host_data = host_data;
  508. return host_data;
  509. free_chips_data:
  510. kfree(host_data->chips_data);
  511. free_host_data:
  512. kfree(host_data);
  513. return NULL;
  514. }
  515. static struct
  516. stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
  517. u32 bank_idx,
  518. struct device_node *node)
  519. {
  520. const struct stm32_exti_bank *stm32_bank;
  521. struct stm32_exti_chip_data *chip_data;
  522. void __iomem *base = h_data->base;
  523. u32 irqs_mask;
  524. stm32_bank = h_data->drv_data->exti_banks[bank_idx];
  525. chip_data = &h_data->chips_data[bank_idx];
  526. chip_data->host_data = h_data;
  527. chip_data->reg_bank = stm32_bank;
  528. raw_spin_lock_init(&chip_data->rlock);
  529. /* Determine number of irqs supported */
  530. writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
  531. irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
  532. /*
  533. * This IP has no reset, so after hot reboot we should
  534. * clear registers to avoid residue
  535. */
  536. writel_relaxed(0, base + stm32_bank->imr_ofst);
  537. writel_relaxed(0, base + stm32_bank->emr_ofst);
  538. pr_info("%s: bank%d, External IRQs available:%#x\n",
  539. node->full_name, bank_idx, irqs_mask);
  540. return chip_data;
  541. }
  542. static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
  543. struct device_node *node)
  544. {
  545. struct stm32_exti_host_data *host_data;
  546. unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
  547. int nr_irqs, ret, i;
  548. struct irq_chip_generic *gc;
  549. struct irq_domain *domain;
  550. host_data = stm32_exti_host_init(drv_data, node);
  551. if (!host_data)
  552. return -ENOMEM;
  553. domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
  554. &irq_exti_domain_ops, NULL);
  555. if (!domain) {
  556. pr_err("%s: Could not register interrupt domain.\n",
  557. node->name);
  558. ret = -ENOMEM;
  559. goto out_unmap;
  560. }
  561. ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
  562. handle_edge_irq, clr, 0, 0);
  563. if (ret) {
  564. pr_err("%pOF: Could not allocate generic interrupt chip.\n",
  565. node);
  566. goto out_free_domain;
  567. }
  568. for (i = 0; i < drv_data->bank_nr; i++) {
  569. const struct stm32_exti_bank *stm32_bank;
  570. struct stm32_exti_chip_data *chip_data;
  571. stm32_bank = drv_data->exti_banks[i];
  572. chip_data = stm32_exti_chip_init(host_data, i, node);
  573. gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
  574. gc->reg_base = host_data->base;
  575. gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
  576. gc->chip_types->chip.irq_ack = stm32_irq_ack;
  577. gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
  578. gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
  579. gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
  580. gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
  581. gc->suspend = stm32_irq_suspend;
  582. gc->resume = stm32_irq_resume;
  583. gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
  584. gc->chip_types->regs.mask = stm32_bank->imr_ofst;
  585. gc->private = (void *)chip_data;
  586. }
  587. nr_irqs = of_irq_count(node);
  588. for (i = 0; i < nr_irqs; i++) {
  589. unsigned int irq = irq_of_parse_and_map(node, i);
  590. irq_set_handler_data(irq, domain);
  591. irq_set_chained_handler(irq, stm32_irq_handler);
  592. }
  593. return 0;
  594. out_free_domain:
  595. irq_domain_remove(domain);
  596. out_unmap:
  597. iounmap(host_data->base);
  598. kfree(host_data->chips_data);
  599. kfree(host_data);
  600. return ret;
  601. }
  602. static const struct irq_domain_ops stm32_exti_h_domain_ops = {
  603. .alloc = stm32_exti_h_domain_alloc,
  604. .free = irq_domain_free_irqs_common,
  605. };
  606. static int
  607. __init stm32_exti_hierarchy_init(const struct stm32_exti_drv_data *drv_data,
  608. struct device_node *node,
  609. struct device_node *parent)
  610. {
  611. struct irq_domain *parent_domain, *domain;
  612. struct stm32_exti_host_data *host_data;
  613. int ret, i;
  614. parent_domain = irq_find_host(parent);
  615. if (!parent_domain) {
  616. pr_err("interrupt-parent not found\n");
  617. return -EINVAL;
  618. }
  619. host_data = stm32_exti_host_init(drv_data, node);
  620. if (!host_data)
  621. return -ENOMEM;
  622. for (i = 0; i < drv_data->bank_nr; i++)
  623. stm32_exti_chip_init(host_data, i, node);
  624. domain = irq_domain_add_hierarchy(parent_domain, 0,
  625. drv_data->bank_nr * IRQS_PER_BANK,
  626. node, &stm32_exti_h_domain_ops,
  627. host_data);
  628. if (!domain) {
  629. pr_err("%s: Could not register exti domain.\n", node->name);
  630. ret = -ENOMEM;
  631. goto out_unmap;
  632. }
  633. stm32_exti_h_syscore_init();
  634. return 0;
  635. out_unmap:
  636. iounmap(host_data->base);
  637. kfree(host_data->chips_data);
  638. kfree(host_data);
  639. return ret;
  640. }
  641. static int __init stm32f4_exti_of_init(struct device_node *np,
  642. struct device_node *parent)
  643. {
  644. return stm32_exti_init(&stm32f4xx_drv_data, np);
  645. }
  646. IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
  647. static int __init stm32h7_exti_of_init(struct device_node *np,
  648. struct device_node *parent)
  649. {
  650. return stm32_exti_init(&stm32h7xx_drv_data, np);
  651. }
  652. IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
  653. static int __init stm32mp1_exti_of_init(struct device_node *np,
  654. struct device_node *parent)
  655. {
  656. return stm32_exti_hierarchy_init(&stm32mp1_drv_data, np, parent);
  657. }
  658. IRQCHIP_DECLARE(stm32mp1_exti, "st,stm32mp1-exti", stm32mp1_exti_of_init);