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hfc4s8s_l1.h

hfc4s8s_l1.h 2.4 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /***************************************************************/
    3. 

  3. /*  $Id: hfc4s8s_l1.h,v 1.1 2005/02/02 17:28:55 martinb1 Exp $ */
    4. 

  4. /*                                                             */
    5. 

  5. /*  This file is a minimal required extraction of hfc48scu.h   */
    6. 

  6. /*  (Genero 3.2, HFC XML 1.7a for HFC-E1, HFC-4S and HFC-8S)   */
    7. 

  7. /*                                                             */
    8. 

  8. /*  To get this complete register description contact          */
    9. 

  9. /*  Cologne Chip AG :                                          */
    10. 

  10. /*  Internet:  http://www.colognechip.com/                     */
    11. 

  11. /*  E-Mail:    info@colognechip.com                            */
    12. 

  12. /***************************************************************/
    13. 

  13. 

  14. #ifndef _HFC4S8S_L1_H_
    15. 

  15. #define _HFC4S8S_L1_H_
    16. 

  16. 

  17. 

  18. /*
    19. 

  19.  *  include Genero generated HFC-4S/8S header file hfc48scu.h
    20. 

  20.  *  for complete register description. This will define _HFC48SCU_H_
    21. 

  21.  *  to prevent redefinitions
    22. 

  22.  */
    23. 

  23. 

  24. // #include "hfc48scu.h"
    25. 

  25. 

  26. #ifndef _HFC48SCU_H_
    27. 

  27. #define _HFC48SCU_H_
    28. 

  28. 

  29. #ifndef PCI_VENDOR_ID_CCD
    30. 

  30. #define PCI_VENDOR_ID_CCD	0x1397
    31. 

  31. #endif
    32. 

  32. 

  33. #define CHIP_ID_4S		0x0C
    34. 

  34. #define CHIP_ID_8S		0x08
    35. 

  35. #define PCI_DEVICE_ID_4S	0x08B4
    36. 

  36. #define PCI_DEVICE_ID_8S	0x16B8
    37. 

  37. 

  38. #define R_IRQ_MISC	0x11
    39. 

  39. #define M_TI_IRQ	0x02
    40. 

  40. #define A_ST_RD_STA	0x30
    41. 

  41. #define A_ST_WR_STA	0x30
    42. 

  42. #define M_SET_G2_G3	0x80
    43. 

  43. #define A_ST_CTRL0	0x31
    44. 

  44. #define A_ST_CTRL2	0x33
    45. 

  45. #define A_ST_CLK_DLY	0x37
    46. 

  46. #define A_Z1		0x04
    47. 

  47. #define A_Z2		0x06
    48. 

  48. #define R_CIRM		0x00
    49. 

  49. #define M_SRES		0x08
    50. 

  50. #define R_CTRL		0x01
    51. 

  51. #define R_BRG_PCM_CFG	0x02
    52. 

  52. #define M_PCM_CLK	0x20
    53. 

  53. #define R_RAM_MISC	0x0C
    54. 

  54. #define M_FZ_MD		0x80
    55. 

  55. #define R_FIFO_MD	0x0D
    56. 

  56. #define A_INC_RES_FIFO	0x0E
    57. 

  57. #define R_FIFO		0x0F
    58. 

  58. #define A_F1		0x0C
    59. 

  59. #define A_F2		0x0D
    60. 

  60. #define R_IRQ_OVIEW	0x10
    61. 

  61. #define R_CHIP_ID	0x16
    62. 

  62. #define R_STATUS	0x1C
    63. 

  63. #define M_BUSY		0x01
    64. 

  64. #define M_MISC_IRQSTA	0x40
    65. 

  65. #define M_FR_IRQSTA	0x80
    66. 

  66. #define R_CHIP_RV	0x1F
    67. 

  67. #define R_IRQ_CTRL	0x13
    68. 

  68. #define M_FIFO_IRQ	0x01
    69. 

  69. #define M_GLOB_IRQ_EN	0x08
    70. 

  70. #define R_PCM_MD0	0x14
    71. 

  71. #define M_PCM_MD	0x01
    72. 

  72. #define A_FIFO_DATA0	0x80
    73. 

  73. #define R_TI_WD		0x1A
    74. 

  74. #define R_PWM1		0x39
    75. 

  75. #define R_PWM_MD	0x46
    76. 

  76. #define R_IRQ_FIFO_BL0	0xC8
    77. 

  77. #define A_CON_HDLC	0xFA
    78. 

  78. #define A_SUBCH_CFG	0xFB
    79. 

  79. #define A_IRQ_MSK	0xFF
    80. 

  80. #define R_SCI_MSK	0x12
    81. 

  81. #define R_ST_SEL	0x16
    82. 

  82. #define R_ST_SYNC	0x17
    83. 

  83. #define M_AUTO_SYNC	0x08
    84. 

  84. #define R_SCI		0x12
    85. 

  85. #define R_IRQMSK_MISC	0x11
    86. 

  86. #define M_TI_IRQMSK	0x02
    87. 

  87. 

  88. #endif	/* _HFC4S8S_L1_H_ */
    89. 

  89. #endif	/* _HFC48SCU_H_ */
    90.