bcm2835.c 37 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487
  1. /*
  2. * bcm2835 sdhost driver.
  3. *
  4. * The 2835 has two SD controllers: The Arasan sdhci controller
  5. * (supported by the iproc driver) and a custom sdhost controller
  6. * (supported by this driver).
  7. *
  8. * The sdhci controller supports both sdcard and sdio. The sdhost
  9. * controller supports the sdcard only, but has better performance.
  10. * Also note that the rpi3 has sdio wifi, so driving the sdcard with
  11. * the sdhost controller allows to use the sdhci controller for wifi
  12. * support.
  13. *
  14. * The configuration is done by devicetree via pin muxing. Both
  15. * SD controller are available on the same pins (2 pin groups = pin 22
  16. * to 27 + pin 48 to 53). So it's possible to use both SD controllers
  17. * at the same time with different pin groups.
  18. *
  19. * Author: Phil Elwell <phil@raspberrypi.org>
  20. * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
  21. *
  22. * Based on
  23. * mmc-bcm2835.c by Gellert Weisz
  24. * which is, in turn, based on
  25. * sdhci-bcm2708.c by Broadcom
  26. * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
  27. * sdhci.c and sdhci-pci.c by Pierre Ossman
  28. *
  29. * This program is free software; you can redistribute it and/or modify it
  30. * under the terms and conditions of the GNU General Public License,
  31. * version 2, as published by the Free Software Foundation.
  32. *
  33. * This program is distributed in the hope it will be useful, but WITHOUT
  34. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  35. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  36. * more details.
  37. *
  38. * You should have received a copy of the GNU General Public License
  39. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  40. */
  41. #include <linux/clk.h>
  42. #include <linux/delay.h>
  43. #include <linux/device.h>
  44. #include <linux/dmaengine.h>
  45. #include <linux/dma-mapping.h>
  46. #include <linux/err.h>
  47. #include <linux/highmem.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/io.h>
  50. #include <linux/iopoll.h>
  51. #include <linux/module.h>
  52. #include <linux/of_address.h>
  53. #include <linux/of_irq.h>
  54. #include <linux/platform_device.h>
  55. #include <linux/scatterlist.h>
  56. #include <linux/time.h>
  57. #include <linux/workqueue.h>
  58. #include <linux/mmc/host.h>
  59. #include <linux/mmc/mmc.h>
  60. #include <linux/mmc/sd.h>
  61. #define SDCMD 0x00 /* Command to SD card - 16 R/W */
  62. #define SDARG 0x04 /* Argument to SD card - 32 R/W */
  63. #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
  64. #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
  65. #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
  66. #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
  67. #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
  68. #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
  69. #define SDHSTS 0x20 /* SD host status - 11 R/W */
  70. #define SDVDD 0x30 /* SD card power control - 1 R/W */
  71. #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
  72. #define SDHCFG 0x38 /* Host configuration - 2 R/W */
  73. #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
  74. #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
  75. #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
  76. #define SDCMD_NEW_FLAG 0x8000
  77. #define SDCMD_FAIL_FLAG 0x4000
  78. #define SDCMD_BUSYWAIT 0x800
  79. #define SDCMD_NO_RESPONSE 0x400
  80. #define SDCMD_LONG_RESPONSE 0x200
  81. #define SDCMD_WRITE_CMD 0x80
  82. #define SDCMD_READ_CMD 0x40
  83. #define SDCMD_CMD_MASK 0x3f
  84. #define SDCDIV_MAX_CDIV 0x7ff
  85. #define SDHSTS_BUSY_IRPT 0x400
  86. #define SDHSTS_BLOCK_IRPT 0x200
  87. #define SDHSTS_SDIO_IRPT 0x100
  88. #define SDHSTS_REW_TIME_OUT 0x80
  89. #define SDHSTS_CMD_TIME_OUT 0x40
  90. #define SDHSTS_CRC16_ERROR 0x20
  91. #define SDHSTS_CRC7_ERROR 0x10
  92. #define SDHSTS_FIFO_ERROR 0x08
  93. /* Reserved */
  94. /* Reserved */
  95. #define SDHSTS_DATA_FLAG 0x01
  96. #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
  97. SDHSTS_CRC16_ERROR | \
  98. SDHSTS_REW_TIME_OUT | \
  99. SDHSTS_FIFO_ERROR)
  100. #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
  101. SDHSTS_TRANSFER_ERROR_MASK)
  102. #define SDHCFG_BUSY_IRPT_EN BIT(10)
  103. #define SDHCFG_BLOCK_IRPT_EN BIT(8)
  104. #define SDHCFG_SDIO_IRPT_EN BIT(5)
  105. #define SDHCFG_DATA_IRPT_EN BIT(4)
  106. #define SDHCFG_SLOW_CARD BIT(3)
  107. #define SDHCFG_WIDE_EXT_BUS BIT(2)
  108. #define SDHCFG_WIDE_INT_BUS BIT(1)
  109. #define SDHCFG_REL_CMD_LINE BIT(0)
  110. #define SDVDD_POWER_OFF 0
  111. #define SDVDD_POWER_ON 1
  112. #define SDEDM_FORCE_DATA_MODE BIT(19)
  113. #define SDEDM_CLOCK_PULSE BIT(20)
  114. #define SDEDM_BYPASS BIT(21)
  115. #define SDEDM_WRITE_THRESHOLD_SHIFT 9
  116. #define SDEDM_READ_THRESHOLD_SHIFT 14
  117. #define SDEDM_THRESHOLD_MASK 0x1f
  118. #define SDEDM_FSM_MASK 0xf
  119. #define SDEDM_FSM_IDENTMODE 0x0
  120. #define SDEDM_FSM_DATAMODE 0x1
  121. #define SDEDM_FSM_READDATA 0x2
  122. #define SDEDM_FSM_WRITEDATA 0x3
  123. #define SDEDM_FSM_READWAIT 0x4
  124. #define SDEDM_FSM_READCRC 0x5
  125. #define SDEDM_FSM_WRITECRC 0x6
  126. #define SDEDM_FSM_WRITEWAIT1 0x7
  127. #define SDEDM_FSM_POWERDOWN 0x8
  128. #define SDEDM_FSM_POWERUP 0x9
  129. #define SDEDM_FSM_WRITESTART1 0xa
  130. #define SDEDM_FSM_WRITESTART2 0xb
  131. #define SDEDM_FSM_GENPULSES 0xc
  132. #define SDEDM_FSM_WRITEWAIT2 0xd
  133. #define SDEDM_FSM_STARTPOWDOWN 0xf
  134. #define SDDATA_FIFO_WORDS 16
  135. #define FIFO_READ_THRESHOLD 4
  136. #define FIFO_WRITE_THRESHOLD 4
  137. #define SDDATA_FIFO_PIO_BURST 8
  138. #define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */
  139. struct bcm2835_host {
  140. spinlock_t lock;
  141. struct mutex mutex;
  142. void __iomem *ioaddr;
  143. u32 phys_addr;
  144. struct mmc_host *mmc;
  145. struct platform_device *pdev;
  146. int clock; /* Current clock speed */
  147. unsigned int max_clk; /* Max possible freq */
  148. struct work_struct dma_work;
  149. struct delayed_work timeout_work; /* Timer for timeouts */
  150. struct sg_mapping_iter sg_miter; /* SG state for PIO */
  151. unsigned int blocks; /* remaining PIO blocks */
  152. int irq; /* Device IRQ */
  153. u32 ns_per_fifo_word;
  154. /* cached registers */
  155. u32 hcfg;
  156. u32 cdiv;
  157. struct mmc_request *mrq; /* Current request */
  158. struct mmc_command *cmd; /* Current command */
  159. struct mmc_data *data; /* Current data request */
  160. bool data_complete:1;/* Data finished before cmd */
  161. bool use_busy:1; /* Wait for busy interrupt */
  162. bool use_sbc:1; /* Send CMD23 */
  163. /* for threaded irq handler */
  164. bool irq_block;
  165. bool irq_busy;
  166. bool irq_data;
  167. /* DMA part */
  168. struct dma_chan *dma_chan_rxtx;
  169. struct dma_chan *dma_chan;
  170. struct dma_slave_config dma_cfg_rx;
  171. struct dma_slave_config dma_cfg_tx;
  172. struct dma_async_tx_descriptor *dma_desc;
  173. u32 dma_dir;
  174. u32 drain_words;
  175. struct page *drain_page;
  176. u32 drain_offset;
  177. bool use_dma;
  178. };
  179. static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd,
  180. const char *label)
  181. {
  182. struct device *dev = &host->pdev->dev;
  183. if (!cmd)
  184. return;
  185. dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
  186. (cmd == host->cmd) ? '>' : ' ',
  187. label, cmd->opcode, cmd->arg, cmd->flags,
  188. cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
  189. cmd->error);
  190. }
  191. static void bcm2835_dumpregs(struct bcm2835_host *host)
  192. {
  193. struct mmc_request *mrq = host->mrq;
  194. struct device *dev = &host->pdev->dev;
  195. if (mrq) {
  196. bcm2835_dumpcmd(host, mrq->sbc, "sbc");
  197. bcm2835_dumpcmd(host, mrq->cmd, "cmd");
  198. if (mrq->data) {
  199. dev_dbg(dev, "data blocks %x blksz %x - err %d\n",
  200. mrq->data->blocks,
  201. mrq->data->blksz,
  202. mrq->data->error);
  203. }
  204. bcm2835_dumpcmd(host, mrq->stop, "stop");
  205. }
  206. dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
  207. dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
  208. dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
  209. dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
  210. dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
  211. dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
  212. dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
  213. dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
  214. dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
  215. dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
  216. dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
  217. dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
  218. dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
  219. dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
  220. dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
  221. dev_dbg(dev, "===========================================\n");
  222. }
  223. static void bcm2835_reset_internal(struct bcm2835_host *host)
  224. {
  225. u32 temp;
  226. writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
  227. writel(0, host->ioaddr + SDCMD);
  228. writel(0, host->ioaddr + SDARG);
  229. writel(0xf00000, host->ioaddr + SDTOUT);
  230. writel(0, host->ioaddr + SDCDIV);
  231. writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */
  232. writel(0, host->ioaddr + SDHCFG);
  233. writel(0, host->ioaddr + SDHBCT);
  234. writel(0, host->ioaddr + SDHBLC);
  235. /* Limit fifo usage due to silicon bug */
  236. temp = readl(host->ioaddr + SDEDM);
  237. temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
  238. (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
  239. temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
  240. (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
  241. writel(temp, host->ioaddr + SDEDM);
  242. msleep(20);
  243. writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
  244. msleep(20);
  245. host->clock = 0;
  246. writel(host->hcfg, host->ioaddr + SDHCFG);
  247. writel(host->cdiv, host->ioaddr + SDCDIV);
  248. }
  249. static void bcm2835_reset(struct mmc_host *mmc)
  250. {
  251. struct bcm2835_host *host = mmc_priv(mmc);
  252. if (host->dma_chan)
  253. dmaengine_terminate_sync(host->dma_chan);
  254. host->dma_chan = NULL;
  255. bcm2835_reset_internal(host);
  256. }
  257. static void bcm2835_finish_command(struct bcm2835_host *host);
  258. static void bcm2835_wait_transfer_complete(struct bcm2835_host *host)
  259. {
  260. int timediff;
  261. u32 alternate_idle;
  262. alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ?
  263. SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
  264. timediff = 0;
  265. while (1) {
  266. u32 edm, fsm;
  267. edm = readl(host->ioaddr + SDEDM);
  268. fsm = edm & SDEDM_FSM_MASK;
  269. if ((fsm == SDEDM_FSM_IDENTMODE) ||
  270. (fsm == SDEDM_FSM_DATAMODE))
  271. break;
  272. if (fsm == alternate_idle) {
  273. writel(edm | SDEDM_FORCE_DATA_MODE,
  274. host->ioaddr + SDEDM);
  275. break;
  276. }
  277. timediff++;
  278. if (timediff == 100000) {
  279. dev_err(&host->pdev->dev,
  280. "wait_transfer_complete - still waiting after %d retries\n",
  281. timediff);
  282. bcm2835_dumpregs(host);
  283. host->mrq->data->error = -ETIMEDOUT;
  284. return;
  285. }
  286. cpu_relax();
  287. }
  288. }
  289. static void bcm2835_dma_complete(void *param)
  290. {
  291. struct bcm2835_host *host = param;
  292. schedule_work(&host->dma_work);
  293. }
  294. static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
  295. {
  296. unsigned long flags;
  297. size_t blksize;
  298. unsigned long wait_max;
  299. blksize = host->data->blksz;
  300. wait_max = jiffies + msecs_to_jiffies(500);
  301. local_irq_save(flags);
  302. while (blksize) {
  303. int copy_words;
  304. u32 hsts = 0;
  305. size_t len;
  306. u32 *buf;
  307. if (!sg_miter_next(&host->sg_miter)) {
  308. host->data->error = -EINVAL;
  309. break;
  310. }
  311. len = min(host->sg_miter.length, blksize);
  312. if (len % 4) {
  313. host->data->error = -EINVAL;
  314. break;
  315. }
  316. blksize -= len;
  317. host->sg_miter.consumed = len;
  318. buf = (u32 *)host->sg_miter.addr;
  319. copy_words = len / 4;
  320. while (copy_words) {
  321. int burst_words, words;
  322. u32 edm;
  323. burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
  324. edm = readl(host->ioaddr + SDEDM);
  325. if (is_read)
  326. words = ((edm >> 4) & 0x1f);
  327. else
  328. words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f);
  329. if (words < burst_words) {
  330. int fsm_state = (edm & SDEDM_FSM_MASK);
  331. struct device *dev = &host->pdev->dev;
  332. if ((is_read &&
  333. (fsm_state != SDEDM_FSM_READDATA &&
  334. fsm_state != SDEDM_FSM_READWAIT &&
  335. fsm_state != SDEDM_FSM_READCRC)) ||
  336. (!is_read &&
  337. (fsm_state != SDEDM_FSM_WRITEDATA &&
  338. fsm_state != SDEDM_FSM_WRITESTART1 &&
  339. fsm_state != SDEDM_FSM_WRITESTART2))) {
  340. hsts = readl(host->ioaddr + SDHSTS);
  341. dev_err(dev, "fsm %x, hsts %08x\n",
  342. fsm_state, hsts);
  343. if (hsts & SDHSTS_ERROR_MASK)
  344. break;
  345. }
  346. if (time_after(jiffies, wait_max)) {
  347. dev_err(dev, "PIO %s timeout - EDM %08x\n",
  348. is_read ? "read" : "write",
  349. edm);
  350. hsts = SDHSTS_REW_TIME_OUT;
  351. break;
  352. }
  353. ndelay((burst_words - words) *
  354. host->ns_per_fifo_word);
  355. continue;
  356. } else if (words > copy_words) {
  357. words = copy_words;
  358. }
  359. copy_words -= words;
  360. while (words) {
  361. if (is_read)
  362. *(buf++) = readl(host->ioaddr + SDDATA);
  363. else
  364. writel(*(buf++), host->ioaddr + SDDATA);
  365. words--;
  366. }
  367. }
  368. if (hsts & SDHSTS_ERROR_MASK)
  369. break;
  370. }
  371. sg_miter_stop(&host->sg_miter);
  372. local_irq_restore(flags);
  373. }
  374. static void bcm2835_transfer_pio(struct bcm2835_host *host)
  375. {
  376. struct device *dev = &host->pdev->dev;
  377. u32 sdhsts;
  378. bool is_read;
  379. is_read = (host->data->flags & MMC_DATA_READ) != 0;
  380. bcm2835_transfer_block_pio(host, is_read);
  381. sdhsts = readl(host->ioaddr + SDHSTS);
  382. if (sdhsts & (SDHSTS_CRC16_ERROR |
  383. SDHSTS_CRC7_ERROR |
  384. SDHSTS_FIFO_ERROR)) {
  385. dev_err(dev, "%s transfer error - HSTS %08x\n",
  386. is_read ? "read" : "write", sdhsts);
  387. host->data->error = -EILSEQ;
  388. } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
  389. SDHSTS_REW_TIME_OUT))) {
  390. dev_err(dev, "%s timeout error - HSTS %08x\n",
  391. is_read ? "read" : "write", sdhsts);
  392. host->data->error = -ETIMEDOUT;
  393. }
  394. }
  395. static
  396. void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data)
  397. {
  398. int len, dir_data, dir_slave;
  399. struct dma_async_tx_descriptor *desc = NULL;
  400. struct dma_chan *dma_chan;
  401. dma_chan = host->dma_chan_rxtx;
  402. if (data->flags & MMC_DATA_READ) {
  403. dir_data = DMA_FROM_DEVICE;
  404. dir_slave = DMA_DEV_TO_MEM;
  405. } else {
  406. dir_data = DMA_TO_DEVICE;
  407. dir_slave = DMA_MEM_TO_DEV;
  408. }
  409. /* The block doesn't manage the FIFO DREQs properly for
  410. * multi-block transfers, so don't attempt to DMA the final
  411. * few words. Unfortunately this requires the final sg entry
  412. * to be trimmed. N.B. This code demands that the overspill
  413. * is contained in a single sg entry.
  414. */
  415. host->drain_words = 0;
  416. if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) {
  417. struct scatterlist *sg;
  418. u32 len;
  419. int i;
  420. len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4,
  421. (u32)data->blocks * data->blksz);
  422. for_each_sg(data->sg, sg, data->sg_len, i) {
  423. if (sg_is_last(sg)) {
  424. WARN_ON(sg->length < len);
  425. sg->length -= len;
  426. host->drain_page = sg_page(sg);
  427. host->drain_offset = sg->offset + sg->length;
  428. }
  429. }
  430. host->drain_words = len / 4;
  431. }
  432. /* The parameters have already been validated, so this will not fail */
  433. (void)dmaengine_slave_config(dma_chan,
  434. (dir_data == DMA_FROM_DEVICE) ?
  435. &host->dma_cfg_rx :
  436. &host->dma_cfg_tx);
  437. len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,
  438. dir_data);
  439. if (len > 0) {
  440. desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
  441. len, dir_slave,
  442. DMA_PREP_INTERRUPT |
  443. DMA_CTRL_ACK);
  444. }
  445. if (desc) {
  446. desc->callback = bcm2835_dma_complete;
  447. desc->callback_param = host;
  448. host->dma_desc = desc;
  449. host->dma_chan = dma_chan;
  450. host->dma_dir = dir_data;
  451. }
  452. }
  453. static void bcm2835_start_dma(struct bcm2835_host *host)
  454. {
  455. dmaengine_submit(host->dma_desc);
  456. dma_async_issue_pending(host->dma_chan);
  457. }
  458. static void bcm2835_set_transfer_irqs(struct bcm2835_host *host)
  459. {
  460. u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
  461. SDHCFG_BUSY_IRPT_EN;
  462. if (host->dma_desc) {
  463. host->hcfg = (host->hcfg & ~all_irqs) |
  464. SDHCFG_BUSY_IRPT_EN;
  465. } else {
  466. host->hcfg = (host->hcfg & ~all_irqs) |
  467. SDHCFG_DATA_IRPT_EN |
  468. SDHCFG_BUSY_IRPT_EN;
  469. }
  470. writel(host->hcfg, host->ioaddr + SDHCFG);
  471. }
  472. static
  473. void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
  474. {
  475. struct mmc_data *data = cmd->data;
  476. WARN_ON(host->data);
  477. host->data = data;
  478. if (!data)
  479. return;
  480. host->data_complete = false;
  481. host->data->bytes_xfered = 0;
  482. if (!host->dma_desc) {
  483. /* Use PIO */
  484. int flags = SG_MITER_ATOMIC;
  485. if (data->flags & MMC_DATA_READ)
  486. flags |= SG_MITER_TO_SG;
  487. else
  488. flags |= SG_MITER_FROM_SG;
  489. sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
  490. host->blocks = data->blocks;
  491. }
  492. bcm2835_set_transfer_irqs(host);
  493. writel(data->blksz, host->ioaddr + SDHBCT);
  494. writel(data->blocks, host->ioaddr + SDHBLC);
  495. }
  496. static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms)
  497. {
  498. struct device *dev = &host->pdev->dev;
  499. u32 value;
  500. int ret;
  501. ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
  502. !(value & SDCMD_NEW_FLAG), 1, 10);
  503. if (ret == -ETIMEDOUT)
  504. /* if it takes a while make poll interval bigger */
  505. ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
  506. !(value & SDCMD_NEW_FLAG),
  507. 10, max_ms * 1000);
  508. if (ret == -ETIMEDOUT)
  509. dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms);
  510. return value;
  511. }
  512. static void bcm2835_finish_request(struct bcm2835_host *host)
  513. {
  514. struct dma_chan *terminate_chan = NULL;
  515. struct mmc_request *mrq;
  516. cancel_delayed_work(&host->timeout_work);
  517. mrq = host->mrq;
  518. host->mrq = NULL;
  519. host->cmd = NULL;
  520. host->data = NULL;
  521. host->dma_desc = NULL;
  522. terminate_chan = host->dma_chan;
  523. host->dma_chan = NULL;
  524. if (terminate_chan) {
  525. int err = dmaengine_terminate_all(terminate_chan);
  526. if (err)
  527. dev_err(&host->pdev->dev,
  528. "failed to terminate DMA (%d)\n", err);
  529. }
  530. mmc_request_done(host->mmc, mrq);
  531. }
  532. static
  533. bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
  534. {
  535. struct device *dev = &host->pdev->dev;
  536. u32 sdcmd, sdhsts;
  537. unsigned long timeout;
  538. WARN_ON(host->cmd);
  539. sdcmd = bcm2835_read_wait_sdcmd(host, 100);
  540. if (sdcmd & SDCMD_NEW_FLAG) {
  541. dev_err(dev, "previous command never completed.\n");
  542. bcm2835_dumpregs(host);
  543. cmd->error = -EILSEQ;
  544. bcm2835_finish_request(host);
  545. return false;
  546. }
  547. if (!cmd->data && cmd->busy_timeout > 9000)
  548. timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
  549. else
  550. timeout = 10 * HZ;
  551. schedule_delayed_work(&host->timeout_work, timeout);
  552. host->cmd = cmd;
  553. /* Clear any error flags */
  554. sdhsts = readl(host->ioaddr + SDHSTS);
  555. if (sdhsts & SDHSTS_ERROR_MASK)
  556. writel(sdhsts, host->ioaddr + SDHSTS);
  557. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  558. dev_err(dev, "unsupported response type!\n");
  559. cmd->error = -EINVAL;
  560. bcm2835_finish_request(host);
  561. return false;
  562. }
  563. bcm2835_prepare_data(host, cmd);
  564. writel(cmd->arg, host->ioaddr + SDARG);
  565. sdcmd = cmd->opcode & SDCMD_CMD_MASK;
  566. host->use_busy = false;
  567. if (!(cmd->flags & MMC_RSP_PRESENT)) {
  568. sdcmd |= SDCMD_NO_RESPONSE;
  569. } else {
  570. if (cmd->flags & MMC_RSP_136)
  571. sdcmd |= SDCMD_LONG_RESPONSE;
  572. if (cmd->flags & MMC_RSP_BUSY) {
  573. sdcmd |= SDCMD_BUSYWAIT;
  574. host->use_busy = true;
  575. }
  576. }
  577. if (cmd->data) {
  578. if (cmd->data->flags & MMC_DATA_WRITE)
  579. sdcmd |= SDCMD_WRITE_CMD;
  580. if (cmd->data->flags & MMC_DATA_READ)
  581. sdcmd |= SDCMD_READ_CMD;
  582. }
  583. writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
  584. return true;
  585. }
  586. static void bcm2835_transfer_complete(struct bcm2835_host *host)
  587. {
  588. struct mmc_data *data;
  589. WARN_ON(!host->data_complete);
  590. data = host->data;
  591. host->data = NULL;
  592. /* Need to send CMD12 if -
  593. * a) open-ended multiblock transfer (no CMD23)
  594. * b) error in multiblock transfer
  595. */
  596. if (host->mrq->stop && (data->error || !host->use_sbc)) {
  597. if (bcm2835_send_command(host, host->mrq->stop)) {
  598. /* No busy, so poll for completion */
  599. if (!host->use_busy)
  600. bcm2835_finish_command(host);
  601. }
  602. } else {
  603. bcm2835_wait_transfer_complete(host);
  604. bcm2835_finish_request(host);
  605. }
  606. }
  607. static void bcm2835_finish_data(struct bcm2835_host *host)
  608. {
  609. struct device *dev = &host->pdev->dev;
  610. struct mmc_data *data;
  611. data = host->data;
  612. host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
  613. writel(host->hcfg, host->ioaddr + SDHCFG);
  614. data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks);
  615. host->data_complete = true;
  616. if (host->cmd) {
  617. /* Data managed to finish before the
  618. * command completed. Make sure we do
  619. * things in the proper order.
  620. */
  621. dev_dbg(dev, "Finished early - HSTS %08x\n",
  622. readl(host->ioaddr + SDHSTS));
  623. } else {
  624. bcm2835_transfer_complete(host);
  625. }
  626. }
  627. static void bcm2835_finish_command(struct bcm2835_host *host)
  628. {
  629. struct device *dev = &host->pdev->dev;
  630. struct mmc_command *cmd = host->cmd;
  631. u32 sdcmd;
  632. sdcmd = bcm2835_read_wait_sdcmd(host, 100);
  633. /* Check for errors */
  634. if (sdcmd & SDCMD_NEW_FLAG) {
  635. dev_err(dev, "command never completed.\n");
  636. bcm2835_dumpregs(host);
  637. host->cmd->error = -EIO;
  638. bcm2835_finish_request(host);
  639. return;
  640. } else if (sdcmd & SDCMD_FAIL_FLAG) {
  641. u32 sdhsts = readl(host->ioaddr + SDHSTS);
  642. /* Clear the errors */
  643. writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
  644. if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
  645. (host->cmd->opcode != MMC_SEND_OP_COND)) {
  646. u32 edm, fsm;
  647. if (sdhsts & SDHSTS_CMD_TIME_OUT) {
  648. host->cmd->error = -ETIMEDOUT;
  649. } else {
  650. dev_err(dev, "unexpected command %d error\n",
  651. host->cmd->opcode);
  652. bcm2835_dumpregs(host);
  653. host->cmd->error = -EILSEQ;
  654. }
  655. edm = readl(host->ioaddr + SDEDM);
  656. fsm = edm & SDEDM_FSM_MASK;
  657. if (fsm == SDEDM_FSM_READWAIT ||
  658. fsm == SDEDM_FSM_WRITESTART1)
  659. /* Kick the FSM out of its wait */
  660. writel(edm | SDEDM_FORCE_DATA_MODE,
  661. host->ioaddr + SDEDM);
  662. bcm2835_finish_request(host);
  663. return;
  664. }
  665. }
  666. if (cmd->flags & MMC_RSP_PRESENT) {
  667. if (cmd->flags & MMC_RSP_136) {
  668. int i;
  669. for (i = 0; i < 4; i++) {
  670. cmd->resp[3 - i] =
  671. readl(host->ioaddr + SDRSP0 + i * 4);
  672. }
  673. } else {
  674. cmd->resp[0] = readl(host->ioaddr + SDRSP0);
  675. }
  676. }
  677. if (cmd == host->mrq->sbc) {
  678. /* Finished CMD23, now send actual command. */
  679. host->cmd = NULL;
  680. if (bcm2835_send_command(host, host->mrq->cmd)) {
  681. if (host->data && host->dma_desc)
  682. /* DMA transfer starts now, PIO starts
  683. * after irq
  684. */
  685. bcm2835_start_dma(host);
  686. if (!host->use_busy)
  687. bcm2835_finish_command(host);
  688. }
  689. } else if (cmd == host->mrq->stop) {
  690. /* Finished CMD12 */
  691. bcm2835_finish_request(host);
  692. } else {
  693. /* Processed actual command. */
  694. host->cmd = NULL;
  695. if (!host->data)
  696. bcm2835_finish_request(host);
  697. else if (host->data_complete)
  698. bcm2835_transfer_complete(host);
  699. }
  700. }
  701. static void bcm2835_timeout(struct work_struct *work)
  702. {
  703. struct delayed_work *d = to_delayed_work(work);
  704. struct bcm2835_host *host =
  705. container_of(d, struct bcm2835_host, timeout_work);
  706. struct device *dev = &host->pdev->dev;
  707. mutex_lock(&host->mutex);
  708. if (host->mrq) {
  709. dev_err(dev, "timeout waiting for hardware interrupt.\n");
  710. bcm2835_dumpregs(host);
  711. bcm2835_reset(host->mmc);
  712. if (host->data) {
  713. host->data->error = -ETIMEDOUT;
  714. bcm2835_finish_data(host);
  715. } else {
  716. if (host->cmd)
  717. host->cmd->error = -ETIMEDOUT;
  718. else
  719. host->mrq->cmd->error = -ETIMEDOUT;
  720. bcm2835_finish_request(host);
  721. }
  722. }
  723. mutex_unlock(&host->mutex);
  724. }
  725. static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
  726. {
  727. struct device *dev = &host->pdev->dev;
  728. if (!(intmask & SDHSTS_ERROR_MASK))
  729. return false;
  730. if (!host->cmd)
  731. return true;
  732. dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask);
  733. if (intmask & SDHSTS_CRC7_ERROR) {
  734. host->cmd->error = -EILSEQ;
  735. } else if (intmask & (SDHSTS_CRC16_ERROR |
  736. SDHSTS_FIFO_ERROR)) {
  737. if (host->mrq->data)
  738. host->mrq->data->error = -EILSEQ;
  739. else
  740. host->cmd->error = -EILSEQ;
  741. } else if (intmask & SDHSTS_REW_TIME_OUT) {
  742. if (host->mrq->data)
  743. host->mrq->data->error = -ETIMEDOUT;
  744. else
  745. host->cmd->error = -ETIMEDOUT;
  746. } else if (intmask & SDHSTS_CMD_TIME_OUT) {
  747. host->cmd->error = -ETIMEDOUT;
  748. }
  749. bcm2835_dumpregs(host);
  750. return true;
  751. }
  752. static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
  753. {
  754. if (!host->data)
  755. return;
  756. if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
  757. host->data->error = -EILSEQ;
  758. if (intmask & SDHSTS_REW_TIME_OUT)
  759. host->data->error = -ETIMEDOUT;
  760. }
  761. static void bcm2835_busy_irq(struct bcm2835_host *host)
  762. {
  763. if (WARN_ON(!host->cmd)) {
  764. bcm2835_dumpregs(host);
  765. return;
  766. }
  767. if (WARN_ON(!host->use_busy)) {
  768. bcm2835_dumpregs(host);
  769. return;
  770. }
  771. host->use_busy = false;
  772. bcm2835_finish_command(host);
  773. }
  774. static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask)
  775. {
  776. /* There are no dedicated data/space available interrupt
  777. * status bits, so it is necessary to use the single shared
  778. * data/space available FIFO status bits. It is therefore not
  779. * an error to get here when there is no data transfer in
  780. * progress.
  781. */
  782. if (!host->data)
  783. return;
  784. bcm2835_check_data_error(host, intmask);
  785. if (host->data->error)
  786. goto finished;
  787. if (host->data->flags & MMC_DATA_WRITE) {
  788. /* Use the block interrupt for writes after the first block */
  789. host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
  790. host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
  791. writel(host->hcfg, host->ioaddr + SDHCFG);
  792. bcm2835_transfer_pio(host);
  793. } else {
  794. bcm2835_transfer_pio(host);
  795. host->blocks--;
  796. if ((host->blocks == 0) || host->data->error)
  797. goto finished;
  798. }
  799. return;
  800. finished:
  801. host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
  802. writel(host->hcfg, host->ioaddr + SDHCFG);
  803. }
  804. static void bcm2835_data_threaded_irq(struct bcm2835_host *host)
  805. {
  806. if (!host->data)
  807. return;
  808. if ((host->blocks == 0) || host->data->error)
  809. bcm2835_finish_data(host);
  810. }
  811. static void bcm2835_block_irq(struct bcm2835_host *host)
  812. {
  813. if (WARN_ON(!host->data)) {
  814. bcm2835_dumpregs(host);
  815. return;
  816. }
  817. if (!host->dma_desc) {
  818. WARN_ON(!host->blocks);
  819. if (host->data->error || (--host->blocks == 0))
  820. bcm2835_finish_data(host);
  821. else
  822. bcm2835_transfer_pio(host);
  823. } else if (host->data->flags & MMC_DATA_WRITE) {
  824. bcm2835_finish_data(host);
  825. }
  826. }
  827. static irqreturn_t bcm2835_irq(int irq, void *dev_id)
  828. {
  829. irqreturn_t result = IRQ_NONE;
  830. struct bcm2835_host *host = dev_id;
  831. u32 intmask;
  832. spin_lock(&host->lock);
  833. intmask = readl(host->ioaddr + SDHSTS);
  834. writel(SDHSTS_BUSY_IRPT |
  835. SDHSTS_BLOCK_IRPT |
  836. SDHSTS_SDIO_IRPT |
  837. SDHSTS_DATA_FLAG,
  838. host->ioaddr + SDHSTS);
  839. if (intmask & SDHSTS_BLOCK_IRPT) {
  840. bcm2835_check_data_error(host, intmask);
  841. host->irq_block = true;
  842. result = IRQ_WAKE_THREAD;
  843. }
  844. if (intmask & SDHSTS_BUSY_IRPT) {
  845. if (!bcm2835_check_cmd_error(host, intmask)) {
  846. host->irq_busy = true;
  847. result = IRQ_WAKE_THREAD;
  848. } else {
  849. result = IRQ_HANDLED;
  850. }
  851. }
  852. /* There is no true data interrupt status bit, so it is
  853. * necessary to qualify the data flag with the interrupt
  854. * enable bit.
  855. */
  856. if ((intmask & SDHSTS_DATA_FLAG) &&
  857. (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
  858. bcm2835_data_irq(host, intmask);
  859. host->irq_data = true;
  860. result = IRQ_WAKE_THREAD;
  861. }
  862. spin_unlock(&host->lock);
  863. return result;
  864. }
  865. static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id)
  866. {
  867. struct bcm2835_host *host = dev_id;
  868. unsigned long flags;
  869. bool block, busy, data;
  870. spin_lock_irqsave(&host->lock, flags);
  871. block = host->irq_block;
  872. busy = host->irq_busy;
  873. data = host->irq_data;
  874. host->irq_block = false;
  875. host->irq_busy = false;
  876. host->irq_data = false;
  877. spin_unlock_irqrestore(&host->lock, flags);
  878. mutex_lock(&host->mutex);
  879. if (block)
  880. bcm2835_block_irq(host);
  881. if (busy)
  882. bcm2835_busy_irq(host);
  883. if (data)
  884. bcm2835_data_threaded_irq(host);
  885. mutex_unlock(&host->mutex);
  886. return IRQ_HANDLED;
  887. }
  888. static void bcm2835_dma_complete_work(struct work_struct *work)
  889. {
  890. struct bcm2835_host *host =
  891. container_of(work, struct bcm2835_host, dma_work);
  892. struct mmc_data *data = host->data;
  893. mutex_lock(&host->mutex);
  894. if (host->dma_chan) {
  895. dma_unmap_sg(host->dma_chan->device->dev,
  896. data->sg, data->sg_len,
  897. host->dma_dir);
  898. host->dma_chan = NULL;
  899. }
  900. if (host->drain_words) {
  901. unsigned long flags;
  902. void *page;
  903. u32 *buf;
  904. if (host->drain_offset & PAGE_MASK) {
  905. host->drain_page += host->drain_offset >> PAGE_SHIFT;
  906. host->drain_offset &= ~PAGE_MASK;
  907. }
  908. local_irq_save(flags);
  909. page = kmap_atomic(host->drain_page);
  910. buf = page + host->drain_offset;
  911. while (host->drain_words) {
  912. u32 edm = readl(host->ioaddr + SDEDM);
  913. if ((edm >> 4) & 0x1f)
  914. *(buf++) = readl(host->ioaddr + SDDATA);
  915. host->drain_words--;
  916. }
  917. kunmap_atomic(page);
  918. local_irq_restore(flags);
  919. }
  920. bcm2835_finish_data(host);
  921. mutex_unlock(&host->mutex);
  922. }
  923. static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
  924. {
  925. int div;
  926. /* The SDCDIV register has 11 bits, and holds (div - 2). But
  927. * in data mode the max is 50MHz wihout a minimum, and only
  928. * the bottom 3 bits are used. Since the switch over is
  929. * automatic (unless we have marked the card as slow...),
  930. * chosen values have to make sense in both modes. Ident mode
  931. * must be 100-400KHz, so can range check the requested
  932. * clock. CMD15 must be used to return to data mode, so this
  933. * can be monitored.
  934. *
  935. * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
  936. * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
  937. *
  938. * 623->400KHz/27.8MHz
  939. * reset value (507)->491159/50MHz
  940. *
  941. * BUT, the 3-bit clock divisor in data mode is too small if
  942. * the core clock is higher than 250MHz, so instead use the
  943. * SLOW_CARD configuration bit to force the use of the ident
  944. * clock divisor at all times.
  945. */
  946. if (clock < 100000) {
  947. /* Can't stop the clock, but make it as slow as possible
  948. * to show willing
  949. */
  950. host->cdiv = SDCDIV_MAX_CDIV;
  951. writel(host->cdiv, host->ioaddr + SDCDIV);
  952. return;
  953. }
  954. div = host->max_clk / clock;
  955. if (div < 2)
  956. div = 2;
  957. if ((host->max_clk / div) > clock)
  958. div++;
  959. div -= 2;
  960. if (div > SDCDIV_MAX_CDIV)
  961. div = SDCDIV_MAX_CDIV;
  962. clock = host->max_clk / (div + 2);
  963. host->mmc->actual_clock = clock;
  964. /* Calibrate some delays */
  965. host->ns_per_fifo_word = (1000000000 / clock) *
  966. ((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32);
  967. host->cdiv = div;
  968. writel(host->cdiv, host->ioaddr + SDCDIV);
  969. /* Set the timeout to 500ms */
  970. writel(host->mmc->actual_clock / 2, host->ioaddr + SDTOUT);
  971. }
  972. static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq)
  973. {
  974. struct bcm2835_host *host = mmc_priv(mmc);
  975. struct device *dev = &host->pdev->dev;
  976. u32 edm, fsm;
  977. /* Reset the error statuses in case this is a retry */
  978. if (mrq->sbc)
  979. mrq->sbc->error = 0;
  980. if (mrq->cmd)
  981. mrq->cmd->error = 0;
  982. if (mrq->data)
  983. mrq->data->error = 0;
  984. if (mrq->stop)
  985. mrq->stop->error = 0;
  986. if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
  987. dev_err(dev, "unsupported block size (%d bytes)\n",
  988. mrq->data->blksz);
  989. if (mrq->cmd)
  990. mrq->cmd->error = -EINVAL;
  991. mmc_request_done(mmc, mrq);
  992. return;
  993. }
  994. if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD))
  995. bcm2835_prepare_dma(host, mrq->data);
  996. mutex_lock(&host->mutex);
  997. WARN_ON(host->mrq);
  998. host->mrq = mrq;
  999. edm = readl(host->ioaddr + SDEDM);
  1000. fsm = edm & SDEDM_FSM_MASK;
  1001. if ((fsm != SDEDM_FSM_IDENTMODE) &&
  1002. (fsm != SDEDM_FSM_DATAMODE)) {
  1003. dev_err(dev, "previous command (%d) not complete (EDM %08x)\n",
  1004. readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK,
  1005. edm);
  1006. bcm2835_dumpregs(host);
  1007. if (mrq->cmd)
  1008. mrq->cmd->error = -EILSEQ;
  1009. bcm2835_finish_request(host);
  1010. mutex_unlock(&host->mutex);
  1011. return;
  1012. }
  1013. host->use_sbc = !!mrq->sbc && host->mrq->data &&
  1014. (host->mrq->data->flags & MMC_DATA_READ);
  1015. if (host->use_sbc) {
  1016. if (bcm2835_send_command(host, mrq->sbc)) {
  1017. if (!host->use_busy)
  1018. bcm2835_finish_command(host);
  1019. }
  1020. } else if (mrq->cmd && bcm2835_send_command(host, mrq->cmd)) {
  1021. if (host->data && host->dma_desc) {
  1022. /* DMA transfer starts now, PIO starts after irq */
  1023. bcm2835_start_dma(host);
  1024. }
  1025. if (!host->use_busy)
  1026. bcm2835_finish_command(host);
  1027. }
  1028. mutex_unlock(&host->mutex);
  1029. }
  1030. static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1031. {
  1032. struct bcm2835_host *host = mmc_priv(mmc);
  1033. mutex_lock(&host->mutex);
  1034. if (!ios->clock || ios->clock != host->clock) {
  1035. bcm2835_set_clock(host, ios->clock);
  1036. host->clock = ios->clock;
  1037. }
  1038. /* set bus width */
  1039. host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
  1040. if (ios->bus_width == MMC_BUS_WIDTH_4)
  1041. host->hcfg |= SDHCFG_WIDE_EXT_BUS;
  1042. host->hcfg |= SDHCFG_WIDE_INT_BUS;
  1043. /* Disable clever clock switching, to cope with fast core clocks */
  1044. host->hcfg |= SDHCFG_SLOW_CARD;
  1045. writel(host->hcfg, host->ioaddr + SDHCFG);
  1046. mutex_unlock(&host->mutex);
  1047. }
  1048. static const struct mmc_host_ops bcm2835_ops = {
  1049. .request = bcm2835_request,
  1050. .set_ios = bcm2835_set_ios,
  1051. .hw_reset = bcm2835_reset,
  1052. };
  1053. static int bcm2835_add_host(struct bcm2835_host *host)
  1054. {
  1055. struct mmc_host *mmc = host->mmc;
  1056. struct device *dev = &host->pdev->dev;
  1057. char pio_limit_string[20];
  1058. int ret;
  1059. if (!mmc->f_max || mmc->f_max > host->max_clk)
  1060. mmc->f_max = host->max_clk;
  1061. mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
  1062. mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000);
  1063. dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n",
  1064. mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
  1065. /* host controller capabilities */
  1066. mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
  1067. MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE |
  1068. MMC_CAP_CMD23;
  1069. spin_lock_init(&host->lock);
  1070. mutex_init(&host->mutex);
  1071. if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) {
  1072. dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n");
  1073. host->use_dma = false;
  1074. } else {
  1075. host->use_dma = true;
  1076. host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1077. host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1078. host->dma_cfg_tx.slave_id = 13; /* DREQ channel */
  1079. host->dma_cfg_tx.direction = DMA_MEM_TO_DEV;
  1080. host->dma_cfg_tx.src_addr = 0;
  1081. host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA;
  1082. host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1083. host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1084. host->dma_cfg_rx.slave_id = 13; /* DREQ channel */
  1085. host->dma_cfg_rx.direction = DMA_DEV_TO_MEM;
  1086. host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA;
  1087. host->dma_cfg_rx.dst_addr = 0;
  1088. if (dmaengine_slave_config(host->dma_chan_rxtx,
  1089. &host->dma_cfg_tx) != 0 ||
  1090. dmaengine_slave_config(host->dma_chan_rxtx,
  1091. &host->dma_cfg_rx) != 0)
  1092. host->use_dma = false;
  1093. }
  1094. mmc->max_segs = 128;
  1095. mmc->max_req_size = 524288;
  1096. mmc->max_seg_size = mmc->max_req_size;
  1097. mmc->max_blk_size = 1024;
  1098. mmc->max_blk_count = 65535;
  1099. /* report supported voltage ranges */
  1100. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  1101. INIT_WORK(&host->dma_work, bcm2835_dma_complete_work);
  1102. INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout);
  1103. /* Set interrupt enables */
  1104. host->hcfg = SDHCFG_BUSY_IRPT_EN;
  1105. bcm2835_reset_internal(host);
  1106. ret = request_threaded_irq(host->irq, bcm2835_irq,
  1107. bcm2835_threaded_irq,
  1108. 0, mmc_hostname(mmc), host);
  1109. if (ret) {
  1110. dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret);
  1111. return ret;
  1112. }
  1113. ret = mmc_add_host(mmc);
  1114. if (ret) {
  1115. free_irq(host->irq, host);
  1116. return ret;
  1117. }
  1118. pio_limit_string[0] = '\0';
  1119. if (host->use_dma && (PIO_THRESHOLD > 0))
  1120. sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD);
  1121. dev_info(dev, "loaded - DMA %s%s\n",
  1122. host->use_dma ? "enabled" : "disabled", pio_limit_string);
  1123. return 0;
  1124. }
  1125. static int bcm2835_probe(struct platform_device *pdev)
  1126. {
  1127. struct device *dev = &pdev->dev;
  1128. struct clk *clk;
  1129. struct resource *iomem;
  1130. struct bcm2835_host *host;
  1131. struct mmc_host *mmc;
  1132. const __be32 *regaddr_p;
  1133. int ret;
  1134. dev_dbg(dev, "%s\n", __func__);
  1135. mmc = mmc_alloc_host(sizeof(*host), dev);
  1136. if (!mmc)
  1137. return -ENOMEM;
  1138. mmc->ops = &bcm2835_ops;
  1139. host = mmc_priv(mmc);
  1140. host->mmc = mmc;
  1141. host->pdev = pdev;
  1142. spin_lock_init(&host->lock);
  1143. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1144. host->ioaddr = devm_ioremap_resource(dev, iomem);
  1145. if (IS_ERR(host->ioaddr)) {
  1146. ret = PTR_ERR(host->ioaddr);
  1147. goto err;
  1148. }
  1149. /* Parse OF address directly to get the physical address for
  1150. * DMA to our registers.
  1151. */
  1152. regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
  1153. if (!regaddr_p) {
  1154. dev_err(dev, "Can't get phys address\n");
  1155. ret = -EINVAL;
  1156. goto err;
  1157. }
  1158. host->phys_addr = be32_to_cpup(regaddr_p);
  1159. host->dma_chan = NULL;
  1160. host->dma_desc = NULL;
  1161. host->dma_chan_rxtx = dma_request_slave_channel(dev, "rx-tx");
  1162. clk = devm_clk_get(dev, NULL);
  1163. if (IS_ERR(clk)) {
  1164. ret = PTR_ERR(clk);
  1165. if (ret != -EPROBE_DEFER)
  1166. dev_err(dev, "could not get clk: %d\n", ret);
  1167. goto err;
  1168. }
  1169. host->max_clk = clk_get_rate(clk);
  1170. host->irq = platform_get_irq(pdev, 0);
  1171. if (host->irq <= 0) {
  1172. dev_err(dev, "get IRQ failed\n");
  1173. ret = -EINVAL;
  1174. goto err;
  1175. }
  1176. ret = mmc_of_parse(mmc);
  1177. if (ret)
  1178. goto err;
  1179. ret = bcm2835_add_host(host);
  1180. if (ret)
  1181. goto err;
  1182. platform_set_drvdata(pdev, host);
  1183. dev_dbg(dev, "%s -> OK\n", __func__);
  1184. return 0;
  1185. err:
  1186. dev_dbg(dev, "%s -> err %d\n", __func__, ret);
  1187. if (host->dma_chan_rxtx)
  1188. dma_release_channel(host->dma_chan_rxtx);
  1189. mmc_free_host(mmc);
  1190. return ret;
  1191. }
  1192. static int bcm2835_remove(struct platform_device *pdev)
  1193. {
  1194. struct bcm2835_host *host = platform_get_drvdata(pdev);
  1195. mmc_remove_host(host->mmc);
  1196. writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
  1197. free_irq(host->irq, host);
  1198. cancel_work_sync(&host->dma_work);
  1199. cancel_delayed_work_sync(&host->timeout_work);
  1200. mmc_free_host(host->mmc);
  1201. platform_set_drvdata(pdev, NULL);
  1202. return 0;
  1203. }
  1204. static const struct of_device_id bcm2835_match[] = {
  1205. { .compatible = "brcm,bcm2835-sdhost" },
  1206. { }
  1207. };
  1208. MODULE_DEVICE_TABLE(of, bcm2835_match);
  1209. static struct platform_driver bcm2835_driver = {
  1210. .probe = bcm2835_probe,
  1211. .remove = bcm2835_remove,
  1212. .driver = {
  1213. .name = "sdhost-bcm2835",
  1214. .of_match_table = bcm2835_match,
  1215. },
  1216. };
  1217. module_platform_driver(bcm2835_driver);
  1218. MODULE_ALIAS("platform:sdhost-bcm2835");
  1219. MODULE_DESCRIPTION("BCM2835 SDHost driver");
  1220. MODULE_LICENSE("GPL v2");
  1221. MODULE_AUTHOR("Phil Elwell");