cqhci.h 6.0 KB

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  1. /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #ifndef LINUX_MMC_CQHCI_H
  13. #define LINUX_MMC_CQHCI_H
  14. #include <linux/compiler.h>
  15. #include <linux/bitops.h>
  16. #include <linux/spinlock_types.h>
  17. #include <linux/types.h>
  18. #include <linux/completion.h>
  19. #include <linux/wait.h>
  20. #include <linux/irqreturn.h>
  21. #include <asm/io.h>
  22. /* registers */
  23. /* version */
  24. #define CQHCI_VER 0x00
  25. #define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8)
  26. #define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4)
  27. #define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0))
  28. /* capabilities */
  29. #define CQHCI_CAP 0x04
  30. /* configuration */
  31. #define CQHCI_CFG 0x08
  32. #define CQHCI_DCMD 0x00001000
  33. #define CQHCI_TASK_DESC_SZ 0x00000100
  34. #define CQHCI_ENABLE 0x00000001
  35. /* control */
  36. #define CQHCI_CTL 0x0C
  37. #define CQHCI_CLEAR_ALL_TASKS 0x00000100
  38. #define CQHCI_HALT 0x00000001
  39. /* interrupt status */
  40. #define CQHCI_IS 0x10
  41. #define CQHCI_IS_HAC BIT(0)
  42. #define CQHCI_IS_TCC BIT(1)
  43. #define CQHCI_IS_RED BIT(2)
  44. #define CQHCI_IS_TCL BIT(3)
  45. #define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED)
  46. /* interrupt status enable */
  47. #define CQHCI_ISTE 0x14
  48. /* interrupt signal enable */
  49. #define CQHCI_ISGE 0x18
  50. /* interrupt coalescing */
  51. #define CQHCI_IC 0x1C
  52. #define CQHCI_IC_ENABLE BIT(31)
  53. #define CQHCI_IC_RESET BIT(16)
  54. #define CQHCI_IC_ICCTHWEN BIT(15)
  55. #define CQHCI_IC_ICCTH(x) (((x) & 0x1F) << 8)
  56. #define CQHCI_IC_ICTOVALWEN BIT(7)
  57. #define CQHCI_IC_ICTOVAL(x) ((x) & 0x7F)
  58. /* task list base address */
  59. #define CQHCI_TDLBA 0x20
  60. /* task list base address upper */
  61. #define CQHCI_TDLBAU 0x24
  62. /* door-bell */
  63. #define CQHCI_TDBR 0x28
  64. /* task completion notification */
  65. #define CQHCI_TCN 0x2C
  66. /* device queue status */
  67. #define CQHCI_DQS 0x30
  68. /* device pending tasks */
  69. #define CQHCI_DPT 0x34
  70. /* task clear */
  71. #define CQHCI_TCLR 0x38
  72. /* send status config 1 */
  73. #define CQHCI_SSC1 0x40
  74. /* send status config 2 */
  75. #define CQHCI_SSC2 0x44
  76. /* response for dcmd */
  77. #define CQHCI_CRDCT 0x48
  78. /* response mode error mask */
  79. #define CQHCI_RMEM 0x50
  80. /* task error info */
  81. #define CQHCI_TERRI 0x54
  82. #define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0))
  83. #define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8)
  84. #define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15))
  85. #define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16)
  86. #define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24)
  87. #define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31))
  88. /* command response index */
  89. #define CQHCI_CRI 0x58
  90. /* command response argument */
  91. #define CQHCI_CRA 0x5C
  92. #define CQHCI_INT_ALL 0xF
  93. #define CQHCI_IC_DEFAULT_ICCTH 31
  94. #define CQHCI_IC_DEFAULT_ICTOVAL 1
  95. /* attribute fields */
  96. #define CQHCI_VALID(x) (((x) & 1) << 0)
  97. #define CQHCI_END(x) (((x) & 1) << 1)
  98. #define CQHCI_INT(x) (((x) & 1) << 2)
  99. #define CQHCI_ACT(x) (((x) & 0x7) << 3)
  100. /* data command task descriptor fields */
  101. #define CQHCI_FORCED_PROG(x) (((x) & 1) << 6)
  102. #define CQHCI_CONTEXT(x) (((x) & 0xF) << 7)
  103. #define CQHCI_DATA_TAG(x) (((x) & 1) << 11)
  104. #define CQHCI_DATA_DIR(x) (((x) & 1) << 12)
  105. #define CQHCI_PRIORITY(x) (((x) & 1) << 13)
  106. #define CQHCI_QBAR(x) (((x) & 1) << 14)
  107. #define CQHCI_REL_WRITE(x) (((x) & 1) << 15)
  108. #define CQHCI_BLK_COUNT(x) (((x) & 0xFFFF) << 16)
  109. #define CQHCI_BLK_ADDR(x) (((x) & 0xFFFFFFFF) << 32)
  110. /* direct command task descriptor fields */
  111. #define CQHCI_CMD_INDEX(x) (((x) & 0x3F) << 16)
  112. #define CQHCI_CMD_TIMING(x) (((x) & 1) << 22)
  113. #define CQHCI_RESP_TYPE(x) (((x) & 0x3) << 23)
  114. /* transfer descriptor fields */
  115. #define CQHCI_DAT_LENGTH(x) (((x) & 0xFFFF) << 16)
  116. #define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32)
  117. #define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0)
  118. struct cqhci_host_ops;
  119. struct mmc_host;
  120. struct cqhci_slot;
  121. struct cqhci_host {
  122. const struct cqhci_host_ops *ops;
  123. void __iomem *mmio;
  124. struct mmc_host *mmc;
  125. spinlock_t lock;
  126. /* relative card address of device */
  127. unsigned int rca;
  128. /* 64 bit DMA */
  129. bool dma64;
  130. int num_slots;
  131. int qcnt;
  132. u32 dcmd_slot;
  133. u32 caps;
  134. #define CQHCI_TASK_DESC_SZ_128 0x1
  135. u32 quirks;
  136. #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
  137. bool enabled;
  138. bool halted;
  139. bool init_done;
  140. bool activated;
  141. bool waiting_for_idle;
  142. bool recovery_halt;
  143. size_t desc_size;
  144. size_t data_size;
  145. u8 *desc_base;
  146. /* total descriptor size */
  147. u8 slot_sz;
  148. /* 64/128 bit depends on CQHCI_CFG */
  149. u8 task_desc_len;
  150. /* 64 bit on 32-bit arch, 128 bit on 64-bit */
  151. u8 link_desc_len;
  152. u8 *trans_desc_base;
  153. /* same length as transfer descriptor */
  154. u8 trans_desc_len;
  155. dma_addr_t desc_dma_base;
  156. dma_addr_t trans_desc_dma_base;
  157. struct completion halt_comp;
  158. wait_queue_head_t wait_queue;
  159. struct cqhci_slot *slot;
  160. };
  161. struct cqhci_host_ops {
  162. void (*dumpregs)(struct mmc_host *mmc);
  163. void (*write_l)(struct cqhci_host *host, u32 val, int reg);
  164. u32 (*read_l)(struct cqhci_host *host, int reg);
  165. void (*enable)(struct mmc_host *mmc);
  166. void (*disable)(struct mmc_host *mmc, bool recovery);
  167. };
  168. static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
  169. {
  170. if (unlikely(host->ops->write_l))
  171. host->ops->write_l(host, val, reg);
  172. else
  173. writel_relaxed(val, host->mmio + reg);
  174. }
  175. static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
  176. {
  177. if (unlikely(host->ops->read_l))
  178. return host->ops->read_l(host, reg);
  179. else
  180. return readl_relaxed(host->mmio + reg);
  181. }
  182. struct platform_device;
  183. irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
  184. int data_error);
  185. int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
  186. struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
  187. int cqhci_suspend(struct mmc_host *mmc);
  188. int cqhci_resume(struct mmc_host *mmc);
  189. #endif