dw_mmc-k3.c 12 KB

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  1. /*
  2. * Copyright (c) 2013 Linaro Ltd.
  3. * Copyright (c) 2013 Hisilicon Limited.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/bitfield.h>
  12. #include <linux/clk.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/module.h>
  16. #include <linux/of_address.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/regmap.h>
  20. #include <linux/regulator/consumer.h>
  21. #include "dw_mmc.h"
  22. #include "dw_mmc-pltfm.h"
  23. /*
  24. * hi6220 sd only support io voltage 1.8v and 3v
  25. * Also need config AO_SCTRL_SEL18 accordingly
  26. */
  27. #define AO_SCTRL_SEL18 BIT(10)
  28. #define AO_SCTRL_CTRL3 0x40C
  29. #define DWMMC_SDIO_ID 2
  30. #define SOC_SCTRL_SCPERCTRL5 (0x314)
  31. #define SDCARD_IO_SEL18 BIT(2)
  32. #define SDCARD_RD_THRESHOLD (512)
  33. #define GENCLK_DIV (7)
  34. #define GPIO_CLK_ENABLE BIT(16)
  35. #define GPIO_CLK_DIV_MASK GENMASK(11, 8)
  36. #define GPIO_USE_SAMPLE_DLY_MASK GENMASK(13, 13)
  37. #define UHS_REG_EXT_SAMPLE_PHASE_MASK GENMASK(20, 16)
  38. #define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK GENMASK(25, 21)
  39. #define UHS_REG_EXT_SAMPLE_DLY_MASK GENMASK(30, 26)
  40. #define TIMING_MODE 3
  41. #define TIMING_CFG_NUM 10
  42. #define NUM_PHASES (40)
  43. #define ENABLE_SHIFT_MIN_SMPL (4)
  44. #define ENABLE_SHIFT_MAX_SMPL (12)
  45. #define USE_DLY_MIN_SMPL (11)
  46. #define USE_DLY_MAX_SMPL (14)
  47. struct k3_priv {
  48. int ctrl_id;
  49. u32 cur_speed;
  50. struct regmap *reg;
  51. };
  52. static unsigned long dw_mci_hi6220_caps[] = {
  53. MMC_CAP_CMD23,
  54. MMC_CAP_CMD23,
  55. 0
  56. };
  57. struct hs_timing {
  58. u32 drv_phase;
  59. u32 smpl_dly;
  60. u32 smpl_phase_max;
  61. u32 smpl_phase_min;
  62. };
  63. static struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
  64. { /* reserved */ },
  65. { /* SD */
  66. {7, 0, 15, 15,}, /* 0: LEGACY 400k */
  67. {6, 0, 4, 4,}, /* 1: MMC_HS */
  68. {6, 0, 3, 3,}, /* 2: SD_HS */
  69. {6, 0, 15, 15,}, /* 3: SDR12 */
  70. {6, 0, 2, 2,}, /* 4: SDR25 */
  71. {4, 0, 11, 0,}, /* 5: SDR50 */
  72. {6, 4, 15, 0,}, /* 6: SDR104 */
  73. {0}, /* 7: DDR50 */
  74. {0}, /* 8: DDR52 */
  75. {0}, /* 9: HS200 */
  76. },
  77. { /* SDIO */
  78. {7, 0, 15, 15,}, /* 0: LEGACY 400k */
  79. {0}, /* 1: MMC_HS */
  80. {6, 0, 15, 15,}, /* 2: SD_HS */
  81. {6, 0, 15, 15,}, /* 3: SDR12 */
  82. {6, 0, 0, 0,}, /* 4: SDR25 */
  83. {4, 0, 12, 0,}, /* 5: SDR50 */
  84. {5, 4, 15, 0,}, /* 6: SDR104 */
  85. {0}, /* 7: DDR50 */
  86. {0}, /* 8: DDR52 */
  87. {0}, /* 9: HS200 */
  88. }
  89. };
  90. static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  91. {
  92. int ret;
  93. ret = clk_set_rate(host->ciu_clk, ios->clock);
  94. if (ret)
  95. dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
  96. host->bus_hz = clk_get_rate(host->ciu_clk);
  97. }
  98. static const struct dw_mci_drv_data k3_drv_data = {
  99. .set_ios = dw_mci_k3_set_ios,
  100. };
  101. static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
  102. {
  103. struct k3_priv *priv;
  104. priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
  105. if (!priv)
  106. return -ENOMEM;
  107. priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node,
  108. "hisilicon,peripheral-syscon");
  109. if (IS_ERR(priv->reg))
  110. priv->reg = NULL;
  111. priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
  112. if (priv->ctrl_id < 0)
  113. priv->ctrl_id = 0;
  114. if (priv->ctrl_id >= TIMING_MODE)
  115. return -EINVAL;
  116. host->priv = priv;
  117. return 0;
  118. }
  119. static int dw_mci_hi6220_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
  120. {
  121. struct dw_mci_slot *slot = mmc_priv(mmc);
  122. struct k3_priv *priv;
  123. struct dw_mci *host;
  124. int min_uv, max_uv;
  125. int ret;
  126. host = slot->host;
  127. priv = host->priv;
  128. if (!priv || !priv->reg)
  129. return 0;
  130. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
  131. ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
  132. AO_SCTRL_SEL18, 0);
  133. min_uv = 3000000;
  134. max_uv = 3000000;
  135. } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  136. ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
  137. AO_SCTRL_SEL18, AO_SCTRL_SEL18);
  138. min_uv = 1800000;
  139. max_uv = 1800000;
  140. } else {
  141. dev_dbg(host->dev, "voltage not supported\n");
  142. return -EINVAL;
  143. }
  144. if (ret) {
  145. dev_dbg(host->dev, "switch voltage failed\n");
  146. return ret;
  147. }
  148. if (IS_ERR_OR_NULL(mmc->supply.vqmmc))
  149. return 0;
  150. ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
  151. if (ret) {
  152. dev_dbg(host->dev, "Regulator set error %d: %d - %d\n",
  153. ret, min_uv, max_uv);
  154. return ret;
  155. }
  156. return 0;
  157. }
  158. static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  159. {
  160. int ret;
  161. unsigned int clock;
  162. clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
  163. ret = clk_set_rate(host->biu_clk, clock);
  164. if (ret)
  165. dev_warn(host->dev, "failed to set rate %uHz\n", clock);
  166. host->bus_hz = clk_get_rate(host->biu_clk);
  167. }
  168. static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
  169. {
  170. return 0;
  171. }
  172. static const struct dw_mci_drv_data hi6220_data = {
  173. .caps = dw_mci_hi6220_caps,
  174. .num_caps = ARRAY_SIZE(dw_mci_hi6220_caps),
  175. .switch_voltage = dw_mci_hi6220_switch_voltage,
  176. .set_ios = dw_mci_hi6220_set_ios,
  177. .parse_dt = dw_mci_hi6220_parse_dt,
  178. .execute_tuning = dw_mci_hi6220_execute_tuning,
  179. };
  180. static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
  181. int smpl_phase)
  182. {
  183. u32 drv_phase;
  184. u32 smpl_dly;
  185. u32 use_smpl_dly = 0;
  186. u32 enable_shift = 0;
  187. u32 reg_value;
  188. int ctrl_id;
  189. struct k3_priv *priv;
  190. priv = host->priv;
  191. ctrl_id = priv->ctrl_id;
  192. drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
  193. smpl_dly = hs_timing_cfg[ctrl_id][timing].smpl_dly;
  194. if (smpl_phase == -1)
  195. smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
  196. hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
  197. switch (timing) {
  198. case MMC_TIMING_UHS_SDR104:
  199. if (smpl_phase >= USE_DLY_MIN_SMPL &&
  200. smpl_phase <= USE_DLY_MAX_SMPL)
  201. use_smpl_dly = 1;
  202. /* fallthrough */
  203. case MMC_TIMING_UHS_SDR50:
  204. if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL &&
  205. smpl_phase <= ENABLE_SHIFT_MAX_SMPL)
  206. enable_shift = 1;
  207. break;
  208. }
  209. mci_writel(host, GPIO, 0x0);
  210. usleep_range(5, 10);
  211. reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) |
  212. FIELD_PREP(UHS_REG_EXT_SAMPLE_DLY_MASK, smpl_dly) |
  213. FIELD_PREP(UHS_REG_EXT_SAMPLE_DRVPHASE_MASK, drv_phase);
  214. mci_writel(host, UHS_REG_EXT, reg_value);
  215. mci_writel(host, ENABLE_SHIFT, enable_shift);
  216. reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) |
  217. FIELD_PREP(GPIO_USE_SAMPLE_DLY_MASK, use_smpl_dly);
  218. mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE);
  219. /* We should delay 1ms wait for timing setting finished. */
  220. usleep_range(1000, 2000);
  221. }
  222. static int dw_mci_hi3660_init(struct dw_mci *host)
  223. {
  224. mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD,
  225. SDMMC_CARD_RD_THR_EN));
  226. dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1);
  227. host->bus_hz /= (GENCLK_DIV + 1);
  228. return 0;
  229. }
  230. static int dw_mci_set_sel18(struct dw_mci *host, bool set)
  231. {
  232. int ret;
  233. unsigned int val;
  234. struct k3_priv *priv;
  235. priv = host->priv;
  236. val = set ? SDCARD_IO_SEL18 : 0;
  237. ret = regmap_update_bits(priv->reg, SOC_SCTRL_SCPERCTRL5,
  238. SDCARD_IO_SEL18, val);
  239. if (ret) {
  240. dev_err(host->dev, "sel18 %u error\n", val);
  241. return ret;
  242. }
  243. return 0;
  244. }
  245. static void dw_mci_hi3660_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  246. {
  247. int ret;
  248. unsigned long wanted;
  249. unsigned long actual;
  250. struct k3_priv *priv = host->priv;
  251. if (!ios->clock || ios->clock == priv->cur_speed)
  252. return;
  253. wanted = ios->clock * (GENCLK_DIV + 1);
  254. ret = clk_set_rate(host->ciu_clk, wanted);
  255. if (ret) {
  256. dev_err(host->dev, "failed to set rate %luHz\n", wanted);
  257. return;
  258. }
  259. actual = clk_get_rate(host->ciu_clk);
  260. dw_mci_hs_set_timing(host, ios->timing, -1);
  261. host->bus_hz = actual / (GENCLK_DIV + 1);
  262. host->current_speed = 0;
  263. priv->cur_speed = host->bus_hz;
  264. }
  265. static int dw_mci_get_best_clksmpl(unsigned int sample_flag)
  266. {
  267. int i;
  268. int interval;
  269. unsigned int v;
  270. unsigned int len;
  271. unsigned int range_start = 0;
  272. unsigned int range_length = 0;
  273. unsigned int middle_range = 0;
  274. if (!sample_flag)
  275. return -EIO;
  276. if (~sample_flag == 0)
  277. return 0;
  278. i = ffs(sample_flag) - 1;
  279. /*
  280. * A clock cycle is divided into 32 phases,
  281. * each of which is represented by a bit,
  282. * finding the optimal phase.
  283. */
  284. while (i < 32) {
  285. v = ror32(sample_flag, i);
  286. len = ffs(~v) - 1;
  287. if (len > range_length) {
  288. range_length = len;
  289. range_start = i;
  290. }
  291. interval = ffs(v >> len) - 1;
  292. if (interval < 0)
  293. break;
  294. i += len + interval;
  295. }
  296. middle_range = range_start + range_length / 2;
  297. if (middle_range >= 32)
  298. middle_range %= 32;
  299. return middle_range;
  300. }
  301. static int dw_mci_hi3660_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
  302. {
  303. int i = 0;
  304. struct dw_mci *host = slot->host;
  305. struct mmc_host *mmc = slot->mmc;
  306. int smpl_phase = 0;
  307. u32 tuning_sample_flag = 0;
  308. int best_clksmpl = 0;
  309. for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) {
  310. smpl_phase %= 32;
  311. mci_writel(host, TMOUT, ~0);
  312. dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase);
  313. if (!mmc_send_tuning(mmc, opcode, NULL))
  314. tuning_sample_flag |= (1 << smpl_phase);
  315. else
  316. tuning_sample_flag &= ~(1 << smpl_phase);
  317. }
  318. best_clksmpl = dw_mci_get_best_clksmpl(tuning_sample_flag);
  319. if (best_clksmpl < 0) {
  320. dev_err(host->dev, "All phases bad!\n");
  321. return -EIO;
  322. }
  323. dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl);
  324. dev_info(host->dev, "tuning ok best_clksmpl %u tuning_sample_flag %x\n",
  325. best_clksmpl, tuning_sample_flag);
  326. return 0;
  327. }
  328. static int dw_mci_hi3660_switch_voltage(struct mmc_host *mmc,
  329. struct mmc_ios *ios)
  330. {
  331. int ret = 0;
  332. struct dw_mci_slot *slot = mmc_priv(mmc);
  333. struct k3_priv *priv;
  334. struct dw_mci *host;
  335. host = slot->host;
  336. priv = host->priv;
  337. if (!priv || !priv->reg)
  338. return 0;
  339. if (priv->ctrl_id == DWMMC_SDIO_ID)
  340. return 0;
  341. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  342. ret = dw_mci_set_sel18(host, 0);
  343. else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  344. ret = dw_mci_set_sel18(host, 1);
  345. if (ret)
  346. return ret;
  347. if (!IS_ERR(mmc->supply.vqmmc)) {
  348. ret = mmc_regulator_set_vqmmc(mmc, ios);
  349. if (ret) {
  350. dev_err(host->dev, "Regulator set error %d\n", ret);
  351. return ret;
  352. }
  353. }
  354. return 0;
  355. }
  356. static const struct dw_mci_drv_data hi3660_data = {
  357. .init = dw_mci_hi3660_init,
  358. .set_ios = dw_mci_hi3660_set_ios,
  359. .parse_dt = dw_mci_hi6220_parse_dt,
  360. .execute_tuning = dw_mci_hi3660_execute_tuning,
  361. .switch_voltage = dw_mci_hi3660_switch_voltage,
  362. };
  363. static const struct of_device_id dw_mci_k3_match[] = {
  364. { .compatible = "hisilicon,hi3660-dw-mshc", .data = &hi3660_data, },
  365. { .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, },
  366. { .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, },
  367. {},
  368. };
  369. MODULE_DEVICE_TABLE(of, dw_mci_k3_match);
  370. static int dw_mci_k3_probe(struct platform_device *pdev)
  371. {
  372. const struct dw_mci_drv_data *drv_data;
  373. const struct of_device_id *match;
  374. match = of_match_node(dw_mci_k3_match, pdev->dev.of_node);
  375. drv_data = match->data;
  376. return dw_mci_pltfm_register(pdev, drv_data);
  377. }
  378. static const struct dev_pm_ops dw_mci_k3_dev_pm_ops = {
  379. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  380. pm_runtime_force_resume)
  381. SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
  382. dw_mci_runtime_resume,
  383. NULL)
  384. };
  385. static struct platform_driver dw_mci_k3_pltfm_driver = {
  386. .probe = dw_mci_k3_probe,
  387. .remove = dw_mci_pltfm_remove,
  388. .driver = {
  389. .name = "dwmmc_k3",
  390. .of_match_table = dw_mci_k3_match,
  391. .pm = &dw_mci_k3_dev_pm_ops,
  392. },
  393. };
  394. module_platform_driver(dw_mci_k3_pltfm_driver);
  395. MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension");
  396. MODULE_LICENSE("GPL v2");
  397. MODULE_ALIAS("platform:dwmmc_k3");