dw_mmc.c 90 KB

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  1. /*
  2. * Synopsys DesignWare Multimedia Card Interface driver
  3. * (Based on NXP driver for lpc 31xx)
  4. *
  5. * Copyright (C) 2009 NXP Semiconductors
  6. * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/blkdev.h>
  14. #include <linux/clk.h>
  15. #include <linux/debugfs.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/err.h>
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/iopoll.h>
  22. #include <linux/ioport.h>
  23. #include <linux/module.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/seq_file.h>
  27. #include <linux/slab.h>
  28. #include <linux/stat.h>
  29. #include <linux/delay.h>
  30. #include <linux/irq.h>
  31. #include <linux/mmc/card.h>
  32. #include <linux/mmc/host.h>
  33. #include <linux/mmc/mmc.h>
  34. #include <linux/mmc/sd.h>
  35. #include <linux/mmc/sdio.h>
  36. #include <linux/bitops.h>
  37. #include <linux/regulator/consumer.h>
  38. #include <linux/of.h>
  39. #include <linux/of_gpio.h>
  40. #include <linux/mmc/slot-gpio.h>
  41. #include "dw_mmc.h"
  42. /* Common flag combinations */
  43. #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  44. SDMMC_INT_HTO | SDMMC_INT_SBE | \
  45. SDMMC_INT_EBE | SDMMC_INT_HLE)
  46. #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  47. SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  48. #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
  49. DW_MCI_CMD_ERROR_FLAGS)
  50. #define DW_MCI_SEND_STATUS 1
  51. #define DW_MCI_RECV_STATUS 2
  52. #define DW_MCI_DMA_THRESHOLD 16
  53. #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
  54. #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
  55. #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  56. SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  57. SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  58. SDMMC_IDMAC_INT_TI)
  59. #define DESC_RING_BUF_SZ PAGE_SIZE
  60. struct idmac_desc_64addr {
  61. u32 des0; /* Control Descriptor */
  62. #define IDMAC_OWN_CLR64(x) \
  63. !((x) & cpu_to_le32(IDMAC_DES0_OWN))
  64. u32 des1; /* Reserved */
  65. u32 des2; /*Buffer sizes */
  66. #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  67. ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  68. ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  69. u32 des3; /* Reserved */
  70. u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
  71. u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
  72. u32 des6; /* Lower 32-bits of Next Descriptor Address */
  73. u32 des7; /* Upper 32-bits of Next Descriptor Address */
  74. };
  75. struct idmac_desc {
  76. __le32 des0; /* Control Descriptor */
  77. #define IDMAC_DES0_DIC BIT(1)
  78. #define IDMAC_DES0_LD BIT(2)
  79. #define IDMAC_DES0_FD BIT(3)
  80. #define IDMAC_DES0_CH BIT(4)
  81. #define IDMAC_DES0_ER BIT(5)
  82. #define IDMAC_DES0_CES BIT(30)
  83. #define IDMAC_DES0_OWN BIT(31)
  84. __le32 des1; /* Buffer sizes */
  85. #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  86. ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
  87. __le32 des2; /* buffer 1 physical address */
  88. __le32 des3; /* buffer 2 physical address */
  89. };
  90. /* Each descriptor can transfer up to 4KB of data in chained mode */
  91. #define DW_MCI_DESC_DATA_LENGTH 0x1000
  92. #if defined(CONFIG_DEBUG_FS)
  93. static int dw_mci_req_show(struct seq_file *s, void *v)
  94. {
  95. struct dw_mci_slot *slot = s->private;
  96. struct mmc_request *mrq;
  97. struct mmc_command *cmd;
  98. struct mmc_command *stop;
  99. struct mmc_data *data;
  100. /* Make sure we get a consistent snapshot */
  101. spin_lock_bh(&slot->host->lock);
  102. mrq = slot->mrq;
  103. if (mrq) {
  104. cmd = mrq->cmd;
  105. data = mrq->data;
  106. stop = mrq->stop;
  107. if (cmd)
  108. seq_printf(s,
  109. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  110. cmd->opcode, cmd->arg, cmd->flags,
  111. cmd->resp[0], cmd->resp[1], cmd->resp[2],
  112. cmd->resp[2], cmd->error);
  113. if (data)
  114. seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
  115. data->bytes_xfered, data->blocks,
  116. data->blksz, data->flags, data->error);
  117. if (stop)
  118. seq_printf(s,
  119. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  120. stop->opcode, stop->arg, stop->flags,
  121. stop->resp[0], stop->resp[1], stop->resp[2],
  122. stop->resp[2], stop->error);
  123. }
  124. spin_unlock_bh(&slot->host->lock);
  125. return 0;
  126. }
  127. DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
  128. static int dw_mci_regs_show(struct seq_file *s, void *v)
  129. {
  130. struct dw_mci *host = s->private;
  131. pm_runtime_get_sync(host->dev);
  132. seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
  133. seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
  134. seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
  135. seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
  136. seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
  137. seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
  138. pm_runtime_put_autosuspend(host->dev);
  139. return 0;
  140. }
  141. DEFINE_SHOW_ATTRIBUTE(dw_mci_regs);
  142. static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
  143. {
  144. struct mmc_host *mmc = slot->mmc;
  145. struct dw_mci *host = slot->host;
  146. struct dentry *root;
  147. struct dentry *node;
  148. root = mmc->debugfs_root;
  149. if (!root)
  150. return;
  151. node = debugfs_create_file("regs", S_IRUSR, root, host,
  152. &dw_mci_regs_fops);
  153. if (!node)
  154. goto err;
  155. node = debugfs_create_file("req", S_IRUSR, root, slot,
  156. &dw_mci_req_fops);
  157. if (!node)
  158. goto err;
  159. node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
  160. if (!node)
  161. goto err;
  162. node = debugfs_create_x32("pending_events", S_IRUSR, root,
  163. (u32 *)&host->pending_events);
  164. if (!node)
  165. goto err;
  166. node = debugfs_create_x32("completed_events", S_IRUSR, root,
  167. (u32 *)&host->completed_events);
  168. if (!node)
  169. goto err;
  170. return;
  171. err:
  172. dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
  173. }
  174. #endif /* defined(CONFIG_DEBUG_FS) */
  175. static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
  176. {
  177. u32 ctrl;
  178. ctrl = mci_readl(host, CTRL);
  179. ctrl |= reset;
  180. mci_writel(host, CTRL, ctrl);
  181. /* wait till resets clear */
  182. if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
  183. !(ctrl & reset),
  184. 1, 500 * USEC_PER_MSEC)) {
  185. dev_err(host->dev,
  186. "Timeout resetting block (ctrl reset %#x)\n",
  187. ctrl & reset);
  188. return false;
  189. }
  190. return true;
  191. }
  192. static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
  193. {
  194. u32 status;
  195. /*
  196. * Databook says that before issuing a new data transfer command
  197. * we need to check to see if the card is busy. Data transfer commands
  198. * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
  199. *
  200. * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
  201. * expected.
  202. */
  203. if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
  204. !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
  205. if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
  206. status,
  207. !(status & SDMMC_STATUS_BUSY),
  208. 10, 500 * USEC_PER_MSEC))
  209. dev_err(host->dev, "Busy; trying anyway\n");
  210. }
  211. }
  212. static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
  213. {
  214. struct dw_mci *host = slot->host;
  215. unsigned int cmd_status = 0;
  216. mci_writel(host, CMDARG, arg);
  217. wmb(); /* drain writebuffer */
  218. dw_mci_wait_while_busy(host, cmd);
  219. mci_writel(host, CMD, SDMMC_CMD_START | cmd);
  220. if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
  221. !(cmd_status & SDMMC_CMD_START),
  222. 1, 500 * USEC_PER_MSEC))
  223. dev_err(&slot->mmc->class_dev,
  224. "Timeout sending command (cmd %#x arg %#x status %#x)\n",
  225. cmd, arg, cmd_status);
  226. }
  227. static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
  228. {
  229. struct dw_mci_slot *slot = mmc_priv(mmc);
  230. struct dw_mci *host = slot->host;
  231. u32 cmdr;
  232. cmd->error = -EINPROGRESS;
  233. cmdr = cmd->opcode;
  234. if (cmd->opcode == MMC_STOP_TRANSMISSION ||
  235. cmd->opcode == MMC_GO_IDLE_STATE ||
  236. cmd->opcode == MMC_GO_INACTIVE_STATE ||
  237. (cmd->opcode == SD_IO_RW_DIRECT &&
  238. ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
  239. cmdr |= SDMMC_CMD_STOP;
  240. else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
  241. cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
  242. if (cmd->opcode == SD_SWITCH_VOLTAGE) {
  243. u32 clk_en_a;
  244. /* Special bit makes CMD11 not die */
  245. cmdr |= SDMMC_CMD_VOLT_SWITCH;
  246. /* Change state to continue to handle CMD11 weirdness */
  247. WARN_ON(slot->host->state != STATE_SENDING_CMD);
  248. slot->host->state = STATE_SENDING_CMD11;
  249. /*
  250. * We need to disable low power mode (automatic clock stop)
  251. * while doing voltage switch so we don't confuse the card,
  252. * since stopping the clock is a specific part of the UHS
  253. * voltage change dance.
  254. *
  255. * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
  256. * unconditionally turned back on in dw_mci_setup_bus() if it's
  257. * ever called with a non-zero clock. That shouldn't happen
  258. * until the voltage change is all done.
  259. */
  260. clk_en_a = mci_readl(host, CLKENA);
  261. clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
  262. mci_writel(host, CLKENA, clk_en_a);
  263. mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
  264. SDMMC_CMD_PRV_DAT_WAIT, 0);
  265. }
  266. if (cmd->flags & MMC_RSP_PRESENT) {
  267. /* We expect a response, so set this bit */
  268. cmdr |= SDMMC_CMD_RESP_EXP;
  269. if (cmd->flags & MMC_RSP_136)
  270. cmdr |= SDMMC_CMD_RESP_LONG;
  271. }
  272. if (cmd->flags & MMC_RSP_CRC)
  273. cmdr |= SDMMC_CMD_RESP_CRC;
  274. if (cmd->data) {
  275. cmdr |= SDMMC_CMD_DAT_EXP;
  276. if (cmd->data->flags & MMC_DATA_WRITE)
  277. cmdr |= SDMMC_CMD_DAT_WR;
  278. }
  279. if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
  280. cmdr |= SDMMC_CMD_USE_HOLD_REG;
  281. return cmdr;
  282. }
  283. static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
  284. {
  285. struct mmc_command *stop;
  286. u32 cmdr;
  287. if (!cmd->data)
  288. return 0;
  289. stop = &host->stop_abort;
  290. cmdr = cmd->opcode;
  291. memset(stop, 0, sizeof(struct mmc_command));
  292. if (cmdr == MMC_READ_SINGLE_BLOCK ||
  293. cmdr == MMC_READ_MULTIPLE_BLOCK ||
  294. cmdr == MMC_WRITE_BLOCK ||
  295. cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
  296. cmdr == MMC_SEND_TUNING_BLOCK ||
  297. cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
  298. stop->opcode = MMC_STOP_TRANSMISSION;
  299. stop->arg = 0;
  300. stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
  301. } else if (cmdr == SD_IO_RW_EXTENDED) {
  302. stop->opcode = SD_IO_RW_DIRECT;
  303. stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
  304. ((cmd->arg >> 28) & 0x7);
  305. stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
  306. } else {
  307. return 0;
  308. }
  309. cmdr = stop->opcode | SDMMC_CMD_STOP |
  310. SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
  311. if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
  312. cmdr |= SDMMC_CMD_USE_HOLD_REG;
  313. return cmdr;
  314. }
  315. static inline void dw_mci_set_cto(struct dw_mci *host)
  316. {
  317. unsigned int cto_clks;
  318. unsigned int cto_div;
  319. unsigned int cto_ms;
  320. unsigned long irqflags;
  321. cto_clks = mci_readl(host, TMOUT) & 0xff;
  322. cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
  323. if (cto_div == 0)
  324. cto_div = 1;
  325. cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
  326. host->bus_hz);
  327. /* add a bit spare time */
  328. cto_ms += 10;
  329. /*
  330. * The durations we're working with are fairly short so we have to be
  331. * extra careful about synchronization here. Specifically in hardware a
  332. * command timeout is _at most_ 5.1 ms, so that means we expect an
  333. * interrupt (either command done or timeout) to come rather quickly
  334. * after the mci_writel. ...but just in case we have a long interrupt
  335. * latency let's add a bit of paranoia.
  336. *
  337. * In general we'll assume that at least an interrupt will be asserted
  338. * in hardware by the time the cto_timer runs. ...and if it hasn't
  339. * been asserted in hardware by that time then we'll assume it'll never
  340. * come.
  341. */
  342. spin_lock_irqsave(&host->irq_lock, irqflags);
  343. if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
  344. mod_timer(&host->cto_timer,
  345. jiffies + msecs_to_jiffies(cto_ms) + 1);
  346. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  347. }
  348. static void dw_mci_start_command(struct dw_mci *host,
  349. struct mmc_command *cmd, u32 cmd_flags)
  350. {
  351. host->cmd = cmd;
  352. dev_vdbg(host->dev,
  353. "start command: ARGR=0x%08x CMDR=0x%08x\n",
  354. cmd->arg, cmd_flags);
  355. mci_writel(host, CMDARG, cmd->arg);
  356. wmb(); /* drain writebuffer */
  357. dw_mci_wait_while_busy(host, cmd_flags);
  358. mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
  359. /* response expected command only */
  360. if (cmd_flags & SDMMC_CMD_RESP_EXP)
  361. dw_mci_set_cto(host);
  362. }
  363. static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
  364. {
  365. struct mmc_command *stop = &host->stop_abort;
  366. dw_mci_start_command(host, stop, host->stop_cmdr);
  367. }
  368. /* DMA interface functions */
  369. static void dw_mci_stop_dma(struct dw_mci *host)
  370. {
  371. if (host->using_dma) {
  372. host->dma_ops->stop(host);
  373. host->dma_ops->cleanup(host);
  374. }
  375. /* Data transfer was stopped by the interrupt handler */
  376. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  377. }
  378. static void dw_mci_dma_cleanup(struct dw_mci *host)
  379. {
  380. struct mmc_data *data = host->data;
  381. if (data && data->host_cookie == COOKIE_MAPPED) {
  382. dma_unmap_sg(host->dev,
  383. data->sg,
  384. data->sg_len,
  385. mmc_get_dma_dir(data));
  386. data->host_cookie = COOKIE_UNMAPPED;
  387. }
  388. }
  389. static void dw_mci_idmac_reset(struct dw_mci *host)
  390. {
  391. u32 bmod = mci_readl(host, BMOD);
  392. /* Software reset of DMA */
  393. bmod |= SDMMC_IDMAC_SWRESET;
  394. mci_writel(host, BMOD, bmod);
  395. }
  396. static void dw_mci_idmac_stop_dma(struct dw_mci *host)
  397. {
  398. u32 temp;
  399. /* Disable and reset the IDMAC interface */
  400. temp = mci_readl(host, CTRL);
  401. temp &= ~SDMMC_CTRL_USE_IDMAC;
  402. temp |= SDMMC_CTRL_DMA_RESET;
  403. mci_writel(host, CTRL, temp);
  404. /* Stop the IDMAC running */
  405. temp = mci_readl(host, BMOD);
  406. temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
  407. temp |= SDMMC_IDMAC_SWRESET;
  408. mci_writel(host, BMOD, temp);
  409. }
  410. static void dw_mci_dmac_complete_dma(void *arg)
  411. {
  412. struct dw_mci *host = arg;
  413. struct mmc_data *data = host->data;
  414. dev_vdbg(host->dev, "DMA complete\n");
  415. if ((host->use_dma == TRANS_MODE_EDMAC) &&
  416. data && (data->flags & MMC_DATA_READ))
  417. /* Invalidate cache after read */
  418. dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
  419. data->sg,
  420. data->sg_len,
  421. DMA_FROM_DEVICE);
  422. host->dma_ops->cleanup(host);
  423. /*
  424. * If the card was removed, data will be NULL. No point in trying to
  425. * send the stop command or waiting for NBUSY in this case.
  426. */
  427. if (data) {
  428. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  429. tasklet_schedule(&host->tasklet);
  430. }
  431. }
  432. static int dw_mci_idmac_init(struct dw_mci *host)
  433. {
  434. int i;
  435. if (host->dma_64bit_address == 1) {
  436. struct idmac_desc_64addr *p;
  437. /* Number of descriptors in the ring buffer */
  438. host->ring_size =
  439. DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
  440. /* Forward link the descriptor list */
  441. for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
  442. i++, p++) {
  443. p->des6 = (host->sg_dma +
  444. (sizeof(struct idmac_desc_64addr) *
  445. (i + 1))) & 0xffffffff;
  446. p->des7 = (u64)(host->sg_dma +
  447. (sizeof(struct idmac_desc_64addr) *
  448. (i + 1))) >> 32;
  449. /* Initialize reserved and buffer size fields to "0" */
  450. p->des0 = 0;
  451. p->des1 = 0;
  452. p->des2 = 0;
  453. p->des3 = 0;
  454. }
  455. /* Set the last descriptor as the end-of-ring descriptor */
  456. p->des6 = host->sg_dma & 0xffffffff;
  457. p->des7 = (u64)host->sg_dma >> 32;
  458. p->des0 = IDMAC_DES0_ER;
  459. } else {
  460. struct idmac_desc *p;
  461. /* Number of descriptors in the ring buffer */
  462. host->ring_size =
  463. DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
  464. /* Forward link the descriptor list */
  465. for (i = 0, p = host->sg_cpu;
  466. i < host->ring_size - 1;
  467. i++, p++) {
  468. p->des3 = cpu_to_le32(host->sg_dma +
  469. (sizeof(struct idmac_desc) * (i + 1)));
  470. p->des0 = 0;
  471. p->des1 = 0;
  472. }
  473. /* Set the last descriptor as the end-of-ring descriptor */
  474. p->des3 = cpu_to_le32(host->sg_dma);
  475. p->des0 = cpu_to_le32(IDMAC_DES0_ER);
  476. }
  477. dw_mci_idmac_reset(host);
  478. if (host->dma_64bit_address == 1) {
  479. /* Mask out interrupts - get Tx & Rx complete only */
  480. mci_writel(host, IDSTS64, IDMAC_INT_CLR);
  481. mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
  482. SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
  483. /* Set the descriptor base address */
  484. mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
  485. mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
  486. } else {
  487. /* Mask out interrupts - get Tx & Rx complete only */
  488. mci_writel(host, IDSTS, IDMAC_INT_CLR);
  489. mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
  490. SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
  491. /* Set the descriptor base address */
  492. mci_writel(host, DBADDR, host->sg_dma);
  493. }
  494. return 0;
  495. }
  496. static inline int dw_mci_prepare_desc64(struct dw_mci *host,
  497. struct mmc_data *data,
  498. unsigned int sg_len)
  499. {
  500. unsigned int desc_len;
  501. struct idmac_desc_64addr *desc_first, *desc_last, *desc;
  502. u32 val;
  503. int i;
  504. desc_first = desc_last = desc = host->sg_cpu;
  505. for (i = 0; i < sg_len; i++) {
  506. unsigned int length = sg_dma_len(&data->sg[i]);
  507. u64 mem_addr = sg_dma_address(&data->sg[i]);
  508. for ( ; length ; desc++) {
  509. desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
  510. length : DW_MCI_DESC_DATA_LENGTH;
  511. length -= desc_len;
  512. /*
  513. * Wait for the former clear OWN bit operation
  514. * of IDMAC to make sure that this descriptor
  515. * isn't still owned by IDMAC as IDMAC's write
  516. * ops and CPU's read ops are asynchronous.
  517. */
  518. if (readl_poll_timeout_atomic(&desc->des0, val,
  519. !(val & IDMAC_DES0_OWN),
  520. 10, 100 * USEC_PER_MSEC))
  521. goto err_own_bit;
  522. /*
  523. * Set the OWN bit and disable interrupts
  524. * for this descriptor
  525. */
  526. desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
  527. IDMAC_DES0_CH;
  528. /* Buffer length */
  529. IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
  530. /* Physical address to DMA to/from */
  531. desc->des4 = mem_addr & 0xffffffff;
  532. desc->des5 = mem_addr >> 32;
  533. /* Update physical address for the next desc */
  534. mem_addr += desc_len;
  535. /* Save pointer to the last descriptor */
  536. desc_last = desc;
  537. }
  538. }
  539. /* Set first descriptor */
  540. desc_first->des0 |= IDMAC_DES0_FD;
  541. /* Set last descriptor */
  542. desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
  543. desc_last->des0 |= IDMAC_DES0_LD;
  544. return 0;
  545. err_own_bit:
  546. /* restore the descriptor chain as it's polluted */
  547. dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
  548. memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
  549. dw_mci_idmac_init(host);
  550. return -EINVAL;
  551. }
  552. static inline int dw_mci_prepare_desc32(struct dw_mci *host,
  553. struct mmc_data *data,
  554. unsigned int sg_len)
  555. {
  556. unsigned int desc_len;
  557. struct idmac_desc *desc_first, *desc_last, *desc;
  558. u32 val;
  559. int i;
  560. desc_first = desc_last = desc = host->sg_cpu;
  561. for (i = 0; i < sg_len; i++) {
  562. unsigned int length = sg_dma_len(&data->sg[i]);
  563. u32 mem_addr = sg_dma_address(&data->sg[i]);
  564. for ( ; length ; desc++) {
  565. desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
  566. length : DW_MCI_DESC_DATA_LENGTH;
  567. length -= desc_len;
  568. /*
  569. * Wait for the former clear OWN bit operation
  570. * of IDMAC to make sure that this descriptor
  571. * isn't still owned by IDMAC as IDMAC's write
  572. * ops and CPU's read ops are asynchronous.
  573. */
  574. if (readl_poll_timeout_atomic(&desc->des0, val,
  575. IDMAC_OWN_CLR64(val),
  576. 10,
  577. 100 * USEC_PER_MSEC))
  578. goto err_own_bit;
  579. /*
  580. * Set the OWN bit and disable interrupts
  581. * for this descriptor
  582. */
  583. desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
  584. IDMAC_DES0_DIC |
  585. IDMAC_DES0_CH);
  586. /* Buffer length */
  587. IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
  588. /* Physical address to DMA to/from */
  589. desc->des2 = cpu_to_le32(mem_addr);
  590. /* Update physical address for the next desc */
  591. mem_addr += desc_len;
  592. /* Save pointer to the last descriptor */
  593. desc_last = desc;
  594. }
  595. }
  596. /* Set first descriptor */
  597. desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
  598. /* Set last descriptor */
  599. desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
  600. IDMAC_DES0_DIC));
  601. desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
  602. return 0;
  603. err_own_bit:
  604. /* restore the descriptor chain as it's polluted */
  605. dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
  606. memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
  607. dw_mci_idmac_init(host);
  608. return -EINVAL;
  609. }
  610. static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
  611. {
  612. u32 temp;
  613. int ret;
  614. if (host->dma_64bit_address == 1)
  615. ret = dw_mci_prepare_desc64(host, host->data, sg_len);
  616. else
  617. ret = dw_mci_prepare_desc32(host, host->data, sg_len);
  618. if (ret)
  619. goto out;
  620. /* drain writebuffer */
  621. wmb();
  622. /* Make sure to reset DMA in case we did PIO before this */
  623. dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
  624. dw_mci_idmac_reset(host);
  625. /* Select IDMAC interface */
  626. temp = mci_readl(host, CTRL);
  627. temp |= SDMMC_CTRL_USE_IDMAC;
  628. mci_writel(host, CTRL, temp);
  629. /* drain writebuffer */
  630. wmb();
  631. /* Enable the IDMAC */
  632. temp = mci_readl(host, BMOD);
  633. temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
  634. mci_writel(host, BMOD, temp);
  635. /* Start it running */
  636. mci_writel(host, PLDMND, 1);
  637. out:
  638. return ret;
  639. }
  640. static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
  641. .init = dw_mci_idmac_init,
  642. .start = dw_mci_idmac_start_dma,
  643. .stop = dw_mci_idmac_stop_dma,
  644. .complete = dw_mci_dmac_complete_dma,
  645. .cleanup = dw_mci_dma_cleanup,
  646. };
  647. static void dw_mci_edmac_stop_dma(struct dw_mci *host)
  648. {
  649. dmaengine_terminate_async(host->dms->ch);
  650. }
  651. static int dw_mci_edmac_start_dma(struct dw_mci *host,
  652. unsigned int sg_len)
  653. {
  654. struct dma_slave_config cfg;
  655. struct dma_async_tx_descriptor *desc = NULL;
  656. struct scatterlist *sgl = host->data->sg;
  657. static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
  658. u32 sg_elems = host->data->sg_len;
  659. u32 fifoth_val;
  660. u32 fifo_offset = host->fifo_reg - host->regs;
  661. int ret = 0;
  662. /* Set external dma config: burst size, burst width */
  663. cfg.dst_addr = host->phy_regs + fifo_offset;
  664. cfg.src_addr = cfg.dst_addr;
  665. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  666. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  667. /* Match burst msize with external dma config */
  668. fifoth_val = mci_readl(host, FIFOTH);
  669. cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
  670. cfg.src_maxburst = cfg.dst_maxburst;
  671. if (host->data->flags & MMC_DATA_WRITE)
  672. cfg.direction = DMA_MEM_TO_DEV;
  673. else
  674. cfg.direction = DMA_DEV_TO_MEM;
  675. cfg.device_fc = false;
  676. ret = dmaengine_slave_config(host->dms->ch, &cfg);
  677. if (ret) {
  678. dev_err(host->dev, "Failed to config edmac.\n");
  679. return -EBUSY;
  680. }
  681. desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
  682. sg_len, cfg.direction,
  683. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  684. if (!desc) {
  685. dev_err(host->dev, "Can't prepare slave sg.\n");
  686. return -EBUSY;
  687. }
  688. /* Set dw_mci_dmac_complete_dma as callback */
  689. desc->callback = dw_mci_dmac_complete_dma;
  690. desc->callback_param = (void *)host;
  691. dmaengine_submit(desc);
  692. /* Flush cache before write */
  693. if (host->data->flags & MMC_DATA_WRITE)
  694. dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
  695. sg_elems, DMA_TO_DEVICE);
  696. dma_async_issue_pending(host->dms->ch);
  697. return 0;
  698. }
  699. static int dw_mci_edmac_init(struct dw_mci *host)
  700. {
  701. /* Request external dma channel */
  702. host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
  703. if (!host->dms)
  704. return -ENOMEM;
  705. host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
  706. if (!host->dms->ch) {
  707. dev_err(host->dev, "Failed to get external DMA channel.\n");
  708. kfree(host->dms);
  709. host->dms = NULL;
  710. return -ENXIO;
  711. }
  712. return 0;
  713. }
  714. static void dw_mci_edmac_exit(struct dw_mci *host)
  715. {
  716. if (host->dms) {
  717. if (host->dms->ch) {
  718. dma_release_channel(host->dms->ch);
  719. host->dms->ch = NULL;
  720. }
  721. kfree(host->dms);
  722. host->dms = NULL;
  723. }
  724. }
  725. static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
  726. .init = dw_mci_edmac_init,
  727. .exit = dw_mci_edmac_exit,
  728. .start = dw_mci_edmac_start_dma,
  729. .stop = dw_mci_edmac_stop_dma,
  730. .complete = dw_mci_dmac_complete_dma,
  731. .cleanup = dw_mci_dma_cleanup,
  732. };
  733. static int dw_mci_pre_dma_transfer(struct dw_mci *host,
  734. struct mmc_data *data,
  735. int cookie)
  736. {
  737. struct scatterlist *sg;
  738. unsigned int i, sg_len;
  739. if (data->host_cookie == COOKIE_PRE_MAPPED)
  740. return data->sg_len;
  741. /*
  742. * We don't do DMA on "complex" transfers, i.e. with
  743. * non-word-aligned buffers or lengths. Also, we don't bother
  744. * with all the DMA setup overhead for short transfers.
  745. */
  746. if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
  747. return -EINVAL;
  748. if (data->blksz & 3)
  749. return -EINVAL;
  750. for_each_sg(data->sg, sg, data->sg_len, i) {
  751. if (sg->offset & 3 || sg->length & 3)
  752. return -EINVAL;
  753. }
  754. sg_len = dma_map_sg(host->dev,
  755. data->sg,
  756. data->sg_len,
  757. mmc_get_dma_dir(data));
  758. if (sg_len == 0)
  759. return -EINVAL;
  760. data->host_cookie = cookie;
  761. return sg_len;
  762. }
  763. static void dw_mci_pre_req(struct mmc_host *mmc,
  764. struct mmc_request *mrq)
  765. {
  766. struct dw_mci_slot *slot = mmc_priv(mmc);
  767. struct mmc_data *data = mrq->data;
  768. if (!slot->host->use_dma || !data)
  769. return;
  770. /* This data might be unmapped at this time */
  771. data->host_cookie = COOKIE_UNMAPPED;
  772. if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
  773. COOKIE_PRE_MAPPED) < 0)
  774. data->host_cookie = COOKIE_UNMAPPED;
  775. }
  776. static void dw_mci_post_req(struct mmc_host *mmc,
  777. struct mmc_request *mrq,
  778. int err)
  779. {
  780. struct dw_mci_slot *slot = mmc_priv(mmc);
  781. struct mmc_data *data = mrq->data;
  782. if (!slot->host->use_dma || !data)
  783. return;
  784. if (data->host_cookie != COOKIE_UNMAPPED)
  785. dma_unmap_sg(slot->host->dev,
  786. data->sg,
  787. data->sg_len,
  788. mmc_get_dma_dir(data));
  789. data->host_cookie = COOKIE_UNMAPPED;
  790. }
  791. static int dw_mci_get_cd(struct mmc_host *mmc)
  792. {
  793. int present;
  794. struct dw_mci_slot *slot = mmc_priv(mmc);
  795. struct dw_mci *host = slot->host;
  796. int gpio_cd = mmc_gpio_get_cd(mmc);
  797. /* Use platform get_cd function, else try onboard card detect */
  798. if (((mmc->caps & MMC_CAP_NEEDS_POLL)
  799. || !mmc_card_is_removable(mmc))) {
  800. present = 1;
  801. if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
  802. if (mmc->caps & MMC_CAP_NEEDS_POLL) {
  803. dev_info(&mmc->class_dev,
  804. "card is polling.\n");
  805. } else {
  806. dev_info(&mmc->class_dev,
  807. "card is non-removable.\n");
  808. }
  809. set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
  810. }
  811. return present;
  812. } else if (gpio_cd >= 0)
  813. present = gpio_cd;
  814. else
  815. present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
  816. == 0 ? 1 : 0;
  817. spin_lock_bh(&host->lock);
  818. if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
  819. dev_dbg(&mmc->class_dev, "card is present\n");
  820. else if (!present &&
  821. !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
  822. dev_dbg(&mmc->class_dev, "card is not present\n");
  823. spin_unlock_bh(&host->lock);
  824. return present;
  825. }
  826. static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
  827. {
  828. unsigned int blksz = data->blksz;
  829. static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
  830. u32 fifo_width = 1 << host->data_shift;
  831. u32 blksz_depth = blksz / fifo_width, fifoth_val;
  832. u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
  833. int idx = ARRAY_SIZE(mszs) - 1;
  834. /* pio should ship this scenario */
  835. if (!host->use_dma)
  836. return;
  837. tx_wmark = (host->fifo_depth) / 2;
  838. tx_wmark_invers = host->fifo_depth - tx_wmark;
  839. /*
  840. * MSIZE is '1',
  841. * if blksz is not a multiple of the FIFO width
  842. */
  843. if (blksz % fifo_width)
  844. goto done;
  845. do {
  846. if (!((blksz_depth % mszs[idx]) ||
  847. (tx_wmark_invers % mszs[idx]))) {
  848. msize = idx;
  849. rx_wmark = mszs[idx] - 1;
  850. break;
  851. }
  852. } while (--idx > 0);
  853. /*
  854. * If idx is '0', it won't be tried
  855. * Thus, initial values are uesed
  856. */
  857. done:
  858. fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
  859. mci_writel(host, FIFOTH, fifoth_val);
  860. }
  861. static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
  862. {
  863. unsigned int blksz = data->blksz;
  864. u32 blksz_depth, fifo_depth;
  865. u16 thld_size;
  866. u8 enable;
  867. /*
  868. * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
  869. * in the FIFO region, so we really shouldn't access it).
  870. */
  871. if (host->verid < DW_MMC_240A ||
  872. (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
  873. return;
  874. /*
  875. * Card write Threshold is introduced since 2.80a
  876. * It's used when HS400 mode is enabled.
  877. */
  878. if (data->flags & MMC_DATA_WRITE &&
  879. host->timing != MMC_TIMING_MMC_HS400)
  880. goto disable;
  881. if (data->flags & MMC_DATA_WRITE)
  882. enable = SDMMC_CARD_WR_THR_EN;
  883. else
  884. enable = SDMMC_CARD_RD_THR_EN;
  885. if (host->timing != MMC_TIMING_MMC_HS200 &&
  886. host->timing != MMC_TIMING_UHS_SDR104 &&
  887. host->timing != MMC_TIMING_MMC_HS400)
  888. goto disable;
  889. blksz_depth = blksz / (1 << host->data_shift);
  890. fifo_depth = host->fifo_depth;
  891. if (blksz_depth > fifo_depth)
  892. goto disable;
  893. /*
  894. * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
  895. * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
  896. * Currently just choose blksz.
  897. */
  898. thld_size = blksz;
  899. mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
  900. return;
  901. disable:
  902. mci_writel(host, CDTHRCTL, 0);
  903. }
  904. static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
  905. {
  906. unsigned long irqflags;
  907. int sg_len;
  908. u32 temp;
  909. host->using_dma = 0;
  910. /* If we don't have a channel, we can't do DMA */
  911. if (!host->use_dma)
  912. return -ENODEV;
  913. sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
  914. if (sg_len < 0) {
  915. host->dma_ops->stop(host);
  916. return sg_len;
  917. }
  918. host->using_dma = 1;
  919. if (host->use_dma == TRANS_MODE_IDMAC)
  920. dev_vdbg(host->dev,
  921. "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
  922. (unsigned long)host->sg_cpu,
  923. (unsigned long)host->sg_dma,
  924. sg_len);
  925. /*
  926. * Decide the MSIZE and RX/TX Watermark.
  927. * If current block size is same with previous size,
  928. * no need to update fifoth.
  929. */
  930. if (host->prev_blksz != data->blksz)
  931. dw_mci_adjust_fifoth(host, data);
  932. /* Enable the DMA interface */
  933. temp = mci_readl(host, CTRL);
  934. temp |= SDMMC_CTRL_DMA_ENABLE;
  935. mci_writel(host, CTRL, temp);
  936. /* Disable RX/TX IRQs, let DMA handle it */
  937. spin_lock_irqsave(&host->irq_lock, irqflags);
  938. temp = mci_readl(host, INTMASK);
  939. temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
  940. mci_writel(host, INTMASK, temp);
  941. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  942. if (host->dma_ops->start(host, sg_len)) {
  943. host->dma_ops->stop(host);
  944. /* We can't do DMA, try PIO for this one */
  945. dev_dbg(host->dev,
  946. "%s: fall back to PIO mode for current transfer\n",
  947. __func__);
  948. return -ENODEV;
  949. }
  950. return 0;
  951. }
  952. static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
  953. {
  954. unsigned long irqflags;
  955. int flags = SG_MITER_ATOMIC;
  956. u32 temp;
  957. data->error = -EINPROGRESS;
  958. WARN_ON(host->data);
  959. host->sg = NULL;
  960. host->data = data;
  961. if (data->flags & MMC_DATA_READ)
  962. host->dir_status = DW_MCI_RECV_STATUS;
  963. else
  964. host->dir_status = DW_MCI_SEND_STATUS;
  965. dw_mci_ctrl_thld(host, data);
  966. if (dw_mci_submit_data_dma(host, data)) {
  967. if (host->data->flags & MMC_DATA_READ)
  968. flags |= SG_MITER_TO_SG;
  969. else
  970. flags |= SG_MITER_FROM_SG;
  971. sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
  972. host->sg = data->sg;
  973. host->part_buf_start = 0;
  974. host->part_buf_count = 0;
  975. mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
  976. spin_lock_irqsave(&host->irq_lock, irqflags);
  977. temp = mci_readl(host, INTMASK);
  978. temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
  979. mci_writel(host, INTMASK, temp);
  980. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  981. temp = mci_readl(host, CTRL);
  982. temp &= ~SDMMC_CTRL_DMA_ENABLE;
  983. mci_writel(host, CTRL, temp);
  984. /*
  985. * Use the initial fifoth_val for PIO mode. If wm_algined
  986. * is set, we set watermark same as data size.
  987. * If next issued data may be transfered by DMA mode,
  988. * prev_blksz should be invalidated.
  989. */
  990. if (host->wm_aligned)
  991. dw_mci_adjust_fifoth(host, data);
  992. else
  993. mci_writel(host, FIFOTH, host->fifoth_val);
  994. host->prev_blksz = 0;
  995. } else {
  996. /*
  997. * Keep the current block size.
  998. * It will be used to decide whether to update
  999. * fifoth register next time.
  1000. */
  1001. host->prev_blksz = data->blksz;
  1002. }
  1003. }
  1004. static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
  1005. {
  1006. struct dw_mci *host = slot->host;
  1007. unsigned int clock = slot->clock;
  1008. u32 div;
  1009. u32 clk_en_a;
  1010. u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
  1011. /* We must continue to set bit 28 in CMD until the change is complete */
  1012. if (host->state == STATE_WAITING_CMD11_DONE)
  1013. sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
  1014. slot->mmc->actual_clock = 0;
  1015. if (!clock) {
  1016. mci_writel(host, CLKENA, 0);
  1017. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1018. } else if (clock != host->current_speed || force_clkinit) {
  1019. div = host->bus_hz / clock;
  1020. if (host->bus_hz % clock && host->bus_hz > clock)
  1021. /*
  1022. * move the + 1 after the divide to prevent
  1023. * over-clocking the card.
  1024. */
  1025. div += 1;
  1026. div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
  1027. if ((clock != slot->__clk_old &&
  1028. !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
  1029. force_clkinit) {
  1030. /* Silent the verbose log if calling from PM context */
  1031. if (!force_clkinit)
  1032. dev_info(&slot->mmc->class_dev,
  1033. "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
  1034. slot->id, host->bus_hz, clock,
  1035. div ? ((host->bus_hz / div) >> 1) :
  1036. host->bus_hz, div);
  1037. /*
  1038. * If card is polling, display the message only
  1039. * one time at boot time.
  1040. */
  1041. if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
  1042. slot->mmc->f_min == clock)
  1043. set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
  1044. }
  1045. /* disable clock */
  1046. mci_writel(host, CLKENA, 0);
  1047. mci_writel(host, CLKSRC, 0);
  1048. /* inform CIU */
  1049. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1050. /* set clock to desired speed */
  1051. mci_writel(host, CLKDIV, div);
  1052. /* inform CIU */
  1053. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1054. /* enable clock; only low power if no SDIO */
  1055. clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
  1056. if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
  1057. clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
  1058. mci_writel(host, CLKENA, clk_en_a);
  1059. /* inform CIU */
  1060. mci_send_cmd(slot, sdmmc_cmd_bits, 0);
  1061. /* keep the last clock value that was requested from core */
  1062. slot->__clk_old = clock;
  1063. slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
  1064. host->bus_hz;
  1065. }
  1066. host->current_speed = clock;
  1067. /* Set the current slot bus width */
  1068. mci_writel(host, CTYPE, (slot->ctype << slot->id));
  1069. }
  1070. static void __dw_mci_start_request(struct dw_mci *host,
  1071. struct dw_mci_slot *slot,
  1072. struct mmc_command *cmd)
  1073. {
  1074. struct mmc_request *mrq;
  1075. struct mmc_data *data;
  1076. u32 cmdflags;
  1077. mrq = slot->mrq;
  1078. host->mrq = mrq;
  1079. host->pending_events = 0;
  1080. host->completed_events = 0;
  1081. host->cmd_status = 0;
  1082. host->data_status = 0;
  1083. host->dir_status = 0;
  1084. data = cmd->data;
  1085. if (data) {
  1086. mci_writel(host, TMOUT, 0xFFFFFFFF);
  1087. mci_writel(host, BYTCNT, data->blksz*data->blocks);
  1088. mci_writel(host, BLKSIZ, data->blksz);
  1089. }
  1090. cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
  1091. /* this is the first command, send the initialization clock */
  1092. if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
  1093. cmdflags |= SDMMC_CMD_INIT;
  1094. if (data) {
  1095. dw_mci_submit_data(host, data);
  1096. wmb(); /* drain writebuffer */
  1097. }
  1098. dw_mci_start_command(host, cmd, cmdflags);
  1099. if (cmd->opcode == SD_SWITCH_VOLTAGE) {
  1100. unsigned long irqflags;
  1101. /*
  1102. * Databook says to fail after 2ms w/ no response, but evidence
  1103. * shows that sometimes the cmd11 interrupt takes over 130ms.
  1104. * We'll set to 500ms, plus an extra jiffy just in case jiffies
  1105. * is just about to roll over.
  1106. *
  1107. * We do this whole thing under spinlock and only if the
  1108. * command hasn't already completed (indicating the the irq
  1109. * already ran so we don't want the timeout).
  1110. */
  1111. spin_lock_irqsave(&host->irq_lock, irqflags);
  1112. if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
  1113. mod_timer(&host->cmd11_timer,
  1114. jiffies + msecs_to_jiffies(500) + 1);
  1115. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  1116. }
  1117. host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
  1118. }
  1119. static void dw_mci_start_request(struct dw_mci *host,
  1120. struct dw_mci_slot *slot)
  1121. {
  1122. struct mmc_request *mrq = slot->mrq;
  1123. struct mmc_command *cmd;
  1124. cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
  1125. __dw_mci_start_request(host, slot, cmd);
  1126. }
  1127. /* must be called with host->lock held */
  1128. static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
  1129. struct mmc_request *mrq)
  1130. {
  1131. dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
  1132. host->state);
  1133. slot->mrq = mrq;
  1134. if (host->state == STATE_WAITING_CMD11_DONE) {
  1135. dev_warn(&slot->mmc->class_dev,
  1136. "Voltage change didn't complete\n");
  1137. /*
  1138. * this case isn't expected to happen, so we can
  1139. * either crash here or just try to continue on
  1140. * in the closest possible state
  1141. */
  1142. host->state = STATE_IDLE;
  1143. }
  1144. if (host->state == STATE_IDLE) {
  1145. host->state = STATE_SENDING_CMD;
  1146. dw_mci_start_request(host, slot);
  1147. } else {
  1148. list_add_tail(&slot->queue_node, &host->queue);
  1149. }
  1150. }
  1151. static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  1152. {
  1153. struct dw_mci_slot *slot = mmc_priv(mmc);
  1154. struct dw_mci *host = slot->host;
  1155. WARN_ON(slot->mrq);
  1156. /*
  1157. * The check for card presence and queueing of the request must be
  1158. * atomic, otherwise the card could be removed in between and the
  1159. * request wouldn't fail until another card was inserted.
  1160. */
  1161. if (!dw_mci_get_cd(mmc)) {
  1162. mrq->cmd->error = -ENOMEDIUM;
  1163. mmc_request_done(mmc, mrq);
  1164. return;
  1165. }
  1166. spin_lock_bh(&host->lock);
  1167. dw_mci_queue_request(host, slot, mrq);
  1168. spin_unlock_bh(&host->lock);
  1169. }
  1170. static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1171. {
  1172. struct dw_mci_slot *slot = mmc_priv(mmc);
  1173. const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
  1174. u32 regs;
  1175. int ret;
  1176. switch (ios->bus_width) {
  1177. case MMC_BUS_WIDTH_4:
  1178. slot->ctype = SDMMC_CTYPE_4BIT;
  1179. break;
  1180. case MMC_BUS_WIDTH_8:
  1181. slot->ctype = SDMMC_CTYPE_8BIT;
  1182. break;
  1183. default:
  1184. /* set default 1 bit mode */
  1185. slot->ctype = SDMMC_CTYPE_1BIT;
  1186. }
  1187. regs = mci_readl(slot->host, UHS_REG);
  1188. /* DDR mode set */
  1189. if (ios->timing == MMC_TIMING_MMC_DDR52 ||
  1190. ios->timing == MMC_TIMING_UHS_DDR50 ||
  1191. ios->timing == MMC_TIMING_MMC_HS400)
  1192. regs |= ((0x1 << slot->id) << 16);
  1193. else
  1194. regs &= ~((0x1 << slot->id) << 16);
  1195. mci_writel(slot->host, UHS_REG, regs);
  1196. slot->host->timing = ios->timing;
  1197. /*
  1198. * Use mirror of ios->clock to prevent race with mmc
  1199. * core ios update when finding the minimum.
  1200. */
  1201. slot->clock = ios->clock;
  1202. if (drv_data && drv_data->set_ios)
  1203. drv_data->set_ios(slot->host, ios);
  1204. switch (ios->power_mode) {
  1205. case MMC_POWER_UP:
  1206. if (!IS_ERR(mmc->supply.vmmc)) {
  1207. ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
  1208. ios->vdd);
  1209. if (ret) {
  1210. dev_err(slot->host->dev,
  1211. "failed to enable vmmc regulator\n");
  1212. /*return, if failed turn on vmmc*/
  1213. return;
  1214. }
  1215. }
  1216. set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
  1217. regs = mci_readl(slot->host, PWREN);
  1218. regs |= (1 << slot->id);
  1219. mci_writel(slot->host, PWREN, regs);
  1220. break;
  1221. case MMC_POWER_ON:
  1222. if (!slot->host->vqmmc_enabled) {
  1223. if (!IS_ERR(mmc->supply.vqmmc)) {
  1224. ret = regulator_enable(mmc->supply.vqmmc);
  1225. if (ret < 0)
  1226. dev_err(slot->host->dev,
  1227. "failed to enable vqmmc\n");
  1228. else
  1229. slot->host->vqmmc_enabled = true;
  1230. } else {
  1231. /* Keep track so we don't reset again */
  1232. slot->host->vqmmc_enabled = true;
  1233. }
  1234. /* Reset our state machine after powering on */
  1235. dw_mci_ctrl_reset(slot->host,
  1236. SDMMC_CTRL_ALL_RESET_FLAGS);
  1237. }
  1238. /* Adjust clock / bus width after power is up */
  1239. dw_mci_setup_bus(slot, false);
  1240. break;
  1241. case MMC_POWER_OFF:
  1242. /* Turn clock off before power goes down */
  1243. dw_mci_setup_bus(slot, false);
  1244. if (!IS_ERR(mmc->supply.vmmc))
  1245. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  1246. if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
  1247. regulator_disable(mmc->supply.vqmmc);
  1248. slot->host->vqmmc_enabled = false;
  1249. regs = mci_readl(slot->host, PWREN);
  1250. regs &= ~(1 << slot->id);
  1251. mci_writel(slot->host, PWREN, regs);
  1252. break;
  1253. default:
  1254. break;
  1255. }
  1256. if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
  1257. slot->host->state = STATE_IDLE;
  1258. }
  1259. static int dw_mci_card_busy(struct mmc_host *mmc)
  1260. {
  1261. struct dw_mci_slot *slot = mmc_priv(mmc);
  1262. u32 status;
  1263. /*
  1264. * Check the busy bit which is low when DAT[3:0]
  1265. * (the data lines) are 0000
  1266. */
  1267. status = mci_readl(slot->host, STATUS);
  1268. return !!(status & SDMMC_STATUS_BUSY);
  1269. }
  1270. static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
  1271. {
  1272. struct dw_mci_slot *slot = mmc_priv(mmc);
  1273. struct dw_mci *host = slot->host;
  1274. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1275. u32 uhs;
  1276. u32 v18 = SDMMC_UHS_18V << slot->id;
  1277. int ret;
  1278. if (drv_data && drv_data->switch_voltage)
  1279. return drv_data->switch_voltage(mmc, ios);
  1280. /*
  1281. * Program the voltage. Note that some instances of dw_mmc may use
  1282. * the UHS_REG for this. For other instances (like exynos) the UHS_REG
  1283. * does no harm but you need to set the regulator directly. Try both.
  1284. */
  1285. uhs = mci_readl(host, UHS_REG);
  1286. if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  1287. uhs &= ~v18;
  1288. else
  1289. uhs |= v18;
  1290. if (!IS_ERR(mmc->supply.vqmmc)) {
  1291. ret = mmc_regulator_set_vqmmc(mmc, ios);
  1292. if (ret) {
  1293. dev_dbg(&mmc->class_dev,
  1294. "Regulator set error %d - %s V\n",
  1295. ret, uhs & v18 ? "1.8" : "3.3");
  1296. return ret;
  1297. }
  1298. }
  1299. mci_writel(host, UHS_REG, uhs);
  1300. return 0;
  1301. }
  1302. static int dw_mci_get_ro(struct mmc_host *mmc)
  1303. {
  1304. int read_only;
  1305. struct dw_mci_slot *slot = mmc_priv(mmc);
  1306. int gpio_ro = mmc_gpio_get_ro(mmc);
  1307. /* Use platform get_ro function, else try on board write protect */
  1308. if (gpio_ro >= 0)
  1309. read_only = gpio_ro;
  1310. else
  1311. read_only =
  1312. mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
  1313. dev_dbg(&mmc->class_dev, "card is %s\n",
  1314. read_only ? "read-only" : "read-write");
  1315. return read_only;
  1316. }
  1317. static void dw_mci_hw_reset(struct mmc_host *mmc)
  1318. {
  1319. struct dw_mci_slot *slot = mmc_priv(mmc);
  1320. struct dw_mci *host = slot->host;
  1321. int reset;
  1322. if (host->use_dma == TRANS_MODE_IDMAC)
  1323. dw_mci_idmac_reset(host);
  1324. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
  1325. SDMMC_CTRL_FIFO_RESET))
  1326. return;
  1327. /*
  1328. * According to eMMC spec, card reset procedure:
  1329. * tRstW >= 1us: RST_n pulse width
  1330. * tRSCA >= 200us: RST_n to Command time
  1331. * tRSTH >= 1us: RST_n high period
  1332. */
  1333. reset = mci_readl(host, RST_N);
  1334. reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
  1335. mci_writel(host, RST_N, reset);
  1336. usleep_range(1, 2);
  1337. reset |= SDMMC_RST_HWACTIVE << slot->id;
  1338. mci_writel(host, RST_N, reset);
  1339. usleep_range(200, 300);
  1340. }
  1341. static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
  1342. {
  1343. struct dw_mci_slot *slot = mmc_priv(mmc);
  1344. struct dw_mci *host = slot->host;
  1345. /*
  1346. * Low power mode will stop the card clock when idle. According to the
  1347. * description of the CLKENA register we should disable low power mode
  1348. * for SDIO cards if we need SDIO interrupts to work.
  1349. */
  1350. if (mmc->caps & MMC_CAP_SDIO_IRQ) {
  1351. const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
  1352. u32 clk_en_a_old;
  1353. u32 clk_en_a;
  1354. clk_en_a_old = mci_readl(host, CLKENA);
  1355. if (card->type == MMC_TYPE_SDIO ||
  1356. card->type == MMC_TYPE_SD_COMBO) {
  1357. set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
  1358. clk_en_a = clk_en_a_old & ~clken_low_pwr;
  1359. } else {
  1360. clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
  1361. clk_en_a = clk_en_a_old | clken_low_pwr;
  1362. }
  1363. if (clk_en_a != clk_en_a_old) {
  1364. mci_writel(host, CLKENA, clk_en_a);
  1365. mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
  1366. SDMMC_CMD_PRV_DAT_WAIT, 0);
  1367. }
  1368. }
  1369. }
  1370. static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
  1371. {
  1372. struct dw_mci *host = slot->host;
  1373. unsigned long irqflags;
  1374. u32 int_mask;
  1375. spin_lock_irqsave(&host->irq_lock, irqflags);
  1376. /* Enable/disable Slot Specific SDIO interrupt */
  1377. int_mask = mci_readl(host, INTMASK);
  1378. if (enb)
  1379. int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
  1380. else
  1381. int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
  1382. mci_writel(host, INTMASK, int_mask);
  1383. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  1384. }
  1385. static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
  1386. {
  1387. struct dw_mci_slot *slot = mmc_priv(mmc);
  1388. struct dw_mci *host = slot->host;
  1389. __dw_mci_enable_sdio_irq(slot, enb);
  1390. /* Avoid runtime suspending the device when SDIO IRQ is enabled */
  1391. if (enb)
  1392. pm_runtime_get_noresume(host->dev);
  1393. else
  1394. pm_runtime_put_noidle(host->dev);
  1395. }
  1396. static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
  1397. {
  1398. struct dw_mci_slot *slot = mmc_priv(mmc);
  1399. __dw_mci_enable_sdio_irq(slot, 1);
  1400. }
  1401. static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
  1402. {
  1403. struct dw_mci_slot *slot = mmc_priv(mmc);
  1404. struct dw_mci *host = slot->host;
  1405. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1406. int err = -EINVAL;
  1407. if (drv_data && drv_data->execute_tuning)
  1408. err = drv_data->execute_tuning(slot, opcode);
  1409. return err;
  1410. }
  1411. static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
  1412. struct mmc_ios *ios)
  1413. {
  1414. struct dw_mci_slot *slot = mmc_priv(mmc);
  1415. struct dw_mci *host = slot->host;
  1416. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1417. if (drv_data && drv_data->prepare_hs400_tuning)
  1418. return drv_data->prepare_hs400_tuning(host, ios);
  1419. return 0;
  1420. }
  1421. static bool dw_mci_reset(struct dw_mci *host)
  1422. {
  1423. u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
  1424. bool ret = false;
  1425. u32 status = 0;
  1426. /*
  1427. * Resetting generates a block interrupt, hence setting
  1428. * the scatter-gather pointer to NULL.
  1429. */
  1430. if (host->sg) {
  1431. sg_miter_stop(&host->sg_miter);
  1432. host->sg = NULL;
  1433. }
  1434. if (host->use_dma)
  1435. flags |= SDMMC_CTRL_DMA_RESET;
  1436. if (dw_mci_ctrl_reset(host, flags)) {
  1437. /*
  1438. * In all cases we clear the RAWINTS
  1439. * register to clear any interrupts.
  1440. */
  1441. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  1442. if (!host->use_dma) {
  1443. ret = true;
  1444. goto ciu_out;
  1445. }
  1446. /* Wait for dma_req to be cleared */
  1447. if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
  1448. status,
  1449. !(status & SDMMC_STATUS_DMA_REQ),
  1450. 1, 500 * USEC_PER_MSEC)) {
  1451. dev_err(host->dev,
  1452. "%s: Timeout waiting for dma_req to be cleared\n",
  1453. __func__);
  1454. goto ciu_out;
  1455. }
  1456. /* when using DMA next we reset the fifo again */
  1457. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
  1458. goto ciu_out;
  1459. } else {
  1460. /* if the controller reset bit did clear, then set clock regs */
  1461. if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
  1462. dev_err(host->dev,
  1463. "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
  1464. __func__);
  1465. goto ciu_out;
  1466. }
  1467. }
  1468. if (host->use_dma == TRANS_MODE_IDMAC)
  1469. /* It is also required that we reinit idmac */
  1470. dw_mci_idmac_init(host);
  1471. ret = true;
  1472. ciu_out:
  1473. /* After a CTRL reset we need to have CIU set clock registers */
  1474. mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
  1475. return ret;
  1476. }
  1477. static const struct mmc_host_ops dw_mci_ops = {
  1478. .request = dw_mci_request,
  1479. .pre_req = dw_mci_pre_req,
  1480. .post_req = dw_mci_post_req,
  1481. .set_ios = dw_mci_set_ios,
  1482. .get_ro = dw_mci_get_ro,
  1483. .get_cd = dw_mci_get_cd,
  1484. .hw_reset = dw_mci_hw_reset,
  1485. .enable_sdio_irq = dw_mci_enable_sdio_irq,
  1486. .ack_sdio_irq = dw_mci_ack_sdio_irq,
  1487. .execute_tuning = dw_mci_execute_tuning,
  1488. .card_busy = dw_mci_card_busy,
  1489. .start_signal_voltage_switch = dw_mci_switch_voltage,
  1490. .init_card = dw_mci_init_card,
  1491. .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
  1492. };
  1493. static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
  1494. __releases(&host->lock)
  1495. __acquires(&host->lock)
  1496. {
  1497. struct dw_mci_slot *slot;
  1498. struct mmc_host *prev_mmc = host->slot->mmc;
  1499. WARN_ON(host->cmd || host->data);
  1500. host->slot->mrq = NULL;
  1501. host->mrq = NULL;
  1502. if (!list_empty(&host->queue)) {
  1503. slot = list_entry(host->queue.next,
  1504. struct dw_mci_slot, queue_node);
  1505. list_del(&slot->queue_node);
  1506. dev_vdbg(host->dev, "list not empty: %s is next\n",
  1507. mmc_hostname(slot->mmc));
  1508. host->state = STATE_SENDING_CMD;
  1509. dw_mci_start_request(host, slot);
  1510. } else {
  1511. dev_vdbg(host->dev, "list empty\n");
  1512. if (host->state == STATE_SENDING_CMD11)
  1513. host->state = STATE_WAITING_CMD11_DONE;
  1514. else
  1515. host->state = STATE_IDLE;
  1516. }
  1517. spin_unlock(&host->lock);
  1518. mmc_request_done(prev_mmc, mrq);
  1519. spin_lock(&host->lock);
  1520. }
  1521. static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
  1522. {
  1523. u32 status = host->cmd_status;
  1524. host->cmd_status = 0;
  1525. /* Read the response from the card (up to 16 bytes) */
  1526. if (cmd->flags & MMC_RSP_PRESENT) {
  1527. if (cmd->flags & MMC_RSP_136) {
  1528. cmd->resp[3] = mci_readl(host, RESP0);
  1529. cmd->resp[2] = mci_readl(host, RESP1);
  1530. cmd->resp[1] = mci_readl(host, RESP2);
  1531. cmd->resp[0] = mci_readl(host, RESP3);
  1532. } else {
  1533. cmd->resp[0] = mci_readl(host, RESP0);
  1534. cmd->resp[1] = 0;
  1535. cmd->resp[2] = 0;
  1536. cmd->resp[3] = 0;
  1537. }
  1538. }
  1539. if (status & SDMMC_INT_RTO)
  1540. cmd->error = -ETIMEDOUT;
  1541. else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
  1542. cmd->error = -EILSEQ;
  1543. else if (status & SDMMC_INT_RESP_ERR)
  1544. cmd->error = -EIO;
  1545. else
  1546. cmd->error = 0;
  1547. return cmd->error;
  1548. }
  1549. static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
  1550. {
  1551. u32 status = host->data_status;
  1552. if (status & DW_MCI_DATA_ERROR_FLAGS) {
  1553. if (status & SDMMC_INT_DRTO) {
  1554. data->error = -ETIMEDOUT;
  1555. } else if (status & SDMMC_INT_DCRC) {
  1556. data->error = -EILSEQ;
  1557. } else if (status & SDMMC_INT_EBE) {
  1558. if (host->dir_status ==
  1559. DW_MCI_SEND_STATUS) {
  1560. /*
  1561. * No data CRC status was returned.
  1562. * The number of bytes transferred
  1563. * will be exaggerated in PIO mode.
  1564. */
  1565. data->bytes_xfered = 0;
  1566. data->error = -ETIMEDOUT;
  1567. } else if (host->dir_status ==
  1568. DW_MCI_RECV_STATUS) {
  1569. data->error = -EILSEQ;
  1570. }
  1571. } else {
  1572. /* SDMMC_INT_SBE is included */
  1573. data->error = -EILSEQ;
  1574. }
  1575. dev_dbg(host->dev, "data error, status 0x%08x\n", status);
  1576. /*
  1577. * After an error, there may be data lingering
  1578. * in the FIFO
  1579. */
  1580. dw_mci_reset(host);
  1581. } else {
  1582. data->bytes_xfered = data->blocks * data->blksz;
  1583. data->error = 0;
  1584. }
  1585. return data->error;
  1586. }
  1587. static void dw_mci_set_drto(struct dw_mci *host)
  1588. {
  1589. unsigned int drto_clks;
  1590. unsigned int drto_div;
  1591. unsigned int drto_ms;
  1592. unsigned long irqflags;
  1593. drto_clks = mci_readl(host, TMOUT) >> 8;
  1594. drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
  1595. if (drto_div == 0)
  1596. drto_div = 1;
  1597. drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
  1598. host->bus_hz);
  1599. /* add a bit spare time */
  1600. drto_ms += 10;
  1601. spin_lock_irqsave(&host->irq_lock, irqflags);
  1602. if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
  1603. mod_timer(&host->dto_timer,
  1604. jiffies + msecs_to_jiffies(drto_ms));
  1605. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  1606. }
  1607. static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
  1608. {
  1609. if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
  1610. return false;
  1611. /*
  1612. * Really be certain that the timer has stopped. This is a bit of
  1613. * paranoia and could only really happen if we had really bad
  1614. * interrupt latency and the interrupt routine and timeout were
  1615. * running concurrently so that the del_timer() in the interrupt
  1616. * handler couldn't run.
  1617. */
  1618. WARN_ON(del_timer_sync(&host->cto_timer));
  1619. clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  1620. return true;
  1621. }
  1622. static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
  1623. {
  1624. if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
  1625. return false;
  1626. /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
  1627. WARN_ON(del_timer_sync(&host->dto_timer));
  1628. clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  1629. return true;
  1630. }
  1631. static void dw_mci_tasklet_func(unsigned long priv)
  1632. {
  1633. struct dw_mci *host = (struct dw_mci *)priv;
  1634. struct mmc_data *data;
  1635. struct mmc_command *cmd;
  1636. struct mmc_request *mrq;
  1637. enum dw_mci_state state;
  1638. enum dw_mci_state prev_state;
  1639. unsigned int err;
  1640. spin_lock(&host->lock);
  1641. state = host->state;
  1642. data = host->data;
  1643. mrq = host->mrq;
  1644. do {
  1645. prev_state = state;
  1646. switch (state) {
  1647. case STATE_IDLE:
  1648. case STATE_WAITING_CMD11_DONE:
  1649. break;
  1650. case STATE_SENDING_CMD11:
  1651. case STATE_SENDING_CMD:
  1652. if (!dw_mci_clear_pending_cmd_complete(host))
  1653. break;
  1654. cmd = host->cmd;
  1655. host->cmd = NULL;
  1656. set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
  1657. err = dw_mci_command_complete(host, cmd);
  1658. if (cmd == mrq->sbc && !err) {
  1659. __dw_mci_start_request(host, host->slot,
  1660. mrq->cmd);
  1661. goto unlock;
  1662. }
  1663. if (cmd->data && err) {
  1664. /*
  1665. * During UHS tuning sequence, sending the stop
  1666. * command after the response CRC error would
  1667. * throw the system into a confused state
  1668. * causing all future tuning phases to report
  1669. * failure.
  1670. *
  1671. * In such case controller will move into a data
  1672. * transfer state after a response error or
  1673. * response CRC error. Let's let that finish
  1674. * before trying to send a stop, so we'll go to
  1675. * STATE_SENDING_DATA.
  1676. *
  1677. * Although letting the data transfer take place
  1678. * will waste a bit of time (we already know
  1679. * the command was bad), it can't cause any
  1680. * errors since it's possible it would have
  1681. * taken place anyway if this tasklet got
  1682. * delayed. Allowing the transfer to take place
  1683. * avoids races and keeps things simple.
  1684. */
  1685. if (err != -ETIMEDOUT) {
  1686. state = STATE_SENDING_DATA;
  1687. continue;
  1688. }
  1689. dw_mci_stop_dma(host);
  1690. send_stop_abort(host, data);
  1691. state = STATE_SENDING_STOP;
  1692. break;
  1693. }
  1694. if (!cmd->data || err) {
  1695. dw_mci_request_end(host, mrq);
  1696. goto unlock;
  1697. }
  1698. prev_state = state = STATE_SENDING_DATA;
  1699. /* fall through */
  1700. case STATE_SENDING_DATA:
  1701. /*
  1702. * We could get a data error and never a transfer
  1703. * complete so we'd better check for it here.
  1704. *
  1705. * Note that we don't really care if we also got a
  1706. * transfer complete; stopping the DMA and sending an
  1707. * abort won't hurt.
  1708. */
  1709. if (test_and_clear_bit(EVENT_DATA_ERROR,
  1710. &host->pending_events)) {
  1711. dw_mci_stop_dma(host);
  1712. if (!(host->data_status & (SDMMC_INT_DRTO |
  1713. SDMMC_INT_EBE)))
  1714. send_stop_abort(host, data);
  1715. state = STATE_DATA_ERROR;
  1716. break;
  1717. }
  1718. if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
  1719. &host->pending_events)) {
  1720. /*
  1721. * If all data-related interrupts don't come
  1722. * within the given time in reading data state.
  1723. */
  1724. if (host->dir_status == DW_MCI_RECV_STATUS)
  1725. dw_mci_set_drto(host);
  1726. break;
  1727. }
  1728. set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
  1729. /*
  1730. * Handle an EVENT_DATA_ERROR that might have shown up
  1731. * before the transfer completed. This might not have
  1732. * been caught by the check above because the interrupt
  1733. * could have gone off between the previous check and
  1734. * the check for transfer complete.
  1735. *
  1736. * Technically this ought not be needed assuming we
  1737. * get a DATA_COMPLETE eventually (we'll notice the
  1738. * error and end the request), but it shouldn't hurt.
  1739. *
  1740. * This has the advantage of sending the stop command.
  1741. */
  1742. if (test_and_clear_bit(EVENT_DATA_ERROR,
  1743. &host->pending_events)) {
  1744. dw_mci_stop_dma(host);
  1745. if (!(host->data_status & (SDMMC_INT_DRTO |
  1746. SDMMC_INT_EBE)))
  1747. send_stop_abort(host, data);
  1748. state = STATE_DATA_ERROR;
  1749. break;
  1750. }
  1751. prev_state = state = STATE_DATA_BUSY;
  1752. /* fall through */
  1753. case STATE_DATA_BUSY:
  1754. if (!dw_mci_clear_pending_data_complete(host)) {
  1755. /*
  1756. * If data error interrupt comes but data over
  1757. * interrupt doesn't come within the given time.
  1758. * in reading data state.
  1759. */
  1760. if (host->dir_status == DW_MCI_RECV_STATUS)
  1761. dw_mci_set_drto(host);
  1762. break;
  1763. }
  1764. host->data = NULL;
  1765. set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
  1766. err = dw_mci_data_complete(host, data);
  1767. if (!err) {
  1768. if (!data->stop || mrq->sbc) {
  1769. if (mrq->sbc && data->stop)
  1770. data->stop->error = 0;
  1771. dw_mci_request_end(host, mrq);
  1772. goto unlock;
  1773. }
  1774. /* stop command for open-ended transfer*/
  1775. if (data->stop)
  1776. send_stop_abort(host, data);
  1777. } else {
  1778. /*
  1779. * If we don't have a command complete now we'll
  1780. * never get one since we just reset everything;
  1781. * better end the request.
  1782. *
  1783. * If we do have a command complete we'll fall
  1784. * through to the SENDING_STOP command and
  1785. * everything will be peachy keen.
  1786. */
  1787. if (!test_bit(EVENT_CMD_COMPLETE,
  1788. &host->pending_events)) {
  1789. host->cmd = NULL;
  1790. dw_mci_request_end(host, mrq);
  1791. goto unlock;
  1792. }
  1793. }
  1794. /*
  1795. * If err has non-zero,
  1796. * stop-abort command has been already issued.
  1797. */
  1798. prev_state = state = STATE_SENDING_STOP;
  1799. /* fall through */
  1800. case STATE_SENDING_STOP:
  1801. if (!dw_mci_clear_pending_cmd_complete(host))
  1802. break;
  1803. /* CMD error in data command */
  1804. if (mrq->cmd->error && mrq->data)
  1805. dw_mci_reset(host);
  1806. host->cmd = NULL;
  1807. host->data = NULL;
  1808. if (!mrq->sbc && mrq->stop)
  1809. dw_mci_command_complete(host, mrq->stop);
  1810. else
  1811. host->cmd_status = 0;
  1812. dw_mci_request_end(host, mrq);
  1813. goto unlock;
  1814. case STATE_DATA_ERROR:
  1815. if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
  1816. &host->pending_events))
  1817. break;
  1818. state = STATE_DATA_BUSY;
  1819. break;
  1820. }
  1821. } while (state != prev_state);
  1822. host->state = state;
  1823. unlock:
  1824. spin_unlock(&host->lock);
  1825. }
  1826. /* push final bytes to part_buf, only use during push */
  1827. static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1828. {
  1829. memcpy((void *)&host->part_buf, buf, cnt);
  1830. host->part_buf_count = cnt;
  1831. }
  1832. /* append bytes to part_buf, only use during push */
  1833. static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1834. {
  1835. cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
  1836. memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
  1837. host->part_buf_count += cnt;
  1838. return cnt;
  1839. }
  1840. /* pull first bytes from part_buf, only use during pull */
  1841. static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1842. {
  1843. cnt = min_t(int, cnt, host->part_buf_count);
  1844. if (cnt) {
  1845. memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
  1846. cnt);
  1847. host->part_buf_count -= cnt;
  1848. host->part_buf_start += cnt;
  1849. }
  1850. return cnt;
  1851. }
  1852. /* pull final bytes from the part_buf, assuming it's just been filled */
  1853. static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
  1854. {
  1855. memcpy(buf, &host->part_buf, cnt);
  1856. host->part_buf_start = cnt;
  1857. host->part_buf_count = (1 << host->data_shift) - cnt;
  1858. }
  1859. static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
  1860. {
  1861. struct mmc_data *data = host->data;
  1862. int init_cnt = cnt;
  1863. /* try and push anything in the part_buf */
  1864. if (unlikely(host->part_buf_count)) {
  1865. int len = dw_mci_push_part_bytes(host, buf, cnt);
  1866. buf += len;
  1867. cnt -= len;
  1868. if (host->part_buf_count == 2) {
  1869. mci_fifo_writew(host->fifo_reg, host->part_buf16);
  1870. host->part_buf_count = 0;
  1871. }
  1872. }
  1873. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1874. if (unlikely((unsigned long)buf & 0x1)) {
  1875. while (cnt >= 2) {
  1876. u16 aligned_buf[64];
  1877. int len = min(cnt & -2, (int)sizeof(aligned_buf));
  1878. int items = len >> 1;
  1879. int i;
  1880. /* memcpy from input buffer into aligned buffer */
  1881. memcpy(aligned_buf, buf, len);
  1882. buf += len;
  1883. cnt -= len;
  1884. /* push data from aligned buffer into fifo */
  1885. for (i = 0; i < items; ++i)
  1886. mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
  1887. }
  1888. } else
  1889. #endif
  1890. {
  1891. u16 *pdata = buf;
  1892. for (; cnt >= 2; cnt -= 2)
  1893. mci_fifo_writew(host->fifo_reg, *pdata++);
  1894. buf = pdata;
  1895. }
  1896. /* put anything remaining in the part_buf */
  1897. if (cnt) {
  1898. dw_mci_set_part_bytes(host, buf, cnt);
  1899. /* Push data if we have reached the expected data length */
  1900. if ((data->bytes_xfered + init_cnt) ==
  1901. (data->blksz * data->blocks))
  1902. mci_fifo_writew(host->fifo_reg, host->part_buf16);
  1903. }
  1904. }
  1905. static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
  1906. {
  1907. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1908. if (unlikely((unsigned long)buf & 0x1)) {
  1909. while (cnt >= 2) {
  1910. /* pull data from fifo into aligned buffer */
  1911. u16 aligned_buf[64];
  1912. int len = min(cnt & -2, (int)sizeof(aligned_buf));
  1913. int items = len >> 1;
  1914. int i;
  1915. for (i = 0; i < items; ++i)
  1916. aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
  1917. /* memcpy from aligned buffer into output buffer */
  1918. memcpy(buf, aligned_buf, len);
  1919. buf += len;
  1920. cnt -= len;
  1921. }
  1922. } else
  1923. #endif
  1924. {
  1925. u16 *pdata = buf;
  1926. for (; cnt >= 2; cnt -= 2)
  1927. *pdata++ = mci_fifo_readw(host->fifo_reg);
  1928. buf = pdata;
  1929. }
  1930. if (cnt) {
  1931. host->part_buf16 = mci_fifo_readw(host->fifo_reg);
  1932. dw_mci_pull_final_bytes(host, buf, cnt);
  1933. }
  1934. }
  1935. static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
  1936. {
  1937. struct mmc_data *data = host->data;
  1938. int init_cnt = cnt;
  1939. /* try and push anything in the part_buf */
  1940. if (unlikely(host->part_buf_count)) {
  1941. int len = dw_mci_push_part_bytes(host, buf, cnt);
  1942. buf += len;
  1943. cnt -= len;
  1944. if (host->part_buf_count == 4) {
  1945. mci_fifo_writel(host->fifo_reg, host->part_buf32);
  1946. host->part_buf_count = 0;
  1947. }
  1948. }
  1949. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1950. if (unlikely((unsigned long)buf & 0x3)) {
  1951. while (cnt >= 4) {
  1952. u32 aligned_buf[32];
  1953. int len = min(cnt & -4, (int)sizeof(aligned_buf));
  1954. int items = len >> 2;
  1955. int i;
  1956. /* memcpy from input buffer into aligned buffer */
  1957. memcpy(aligned_buf, buf, len);
  1958. buf += len;
  1959. cnt -= len;
  1960. /* push data from aligned buffer into fifo */
  1961. for (i = 0; i < items; ++i)
  1962. mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
  1963. }
  1964. } else
  1965. #endif
  1966. {
  1967. u32 *pdata = buf;
  1968. for (; cnt >= 4; cnt -= 4)
  1969. mci_fifo_writel(host->fifo_reg, *pdata++);
  1970. buf = pdata;
  1971. }
  1972. /* put anything remaining in the part_buf */
  1973. if (cnt) {
  1974. dw_mci_set_part_bytes(host, buf, cnt);
  1975. /* Push data if we have reached the expected data length */
  1976. if ((data->bytes_xfered + init_cnt) ==
  1977. (data->blksz * data->blocks))
  1978. mci_fifo_writel(host->fifo_reg, host->part_buf32);
  1979. }
  1980. }
  1981. static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
  1982. {
  1983. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1984. if (unlikely((unsigned long)buf & 0x3)) {
  1985. while (cnt >= 4) {
  1986. /* pull data from fifo into aligned buffer */
  1987. u32 aligned_buf[32];
  1988. int len = min(cnt & -4, (int)sizeof(aligned_buf));
  1989. int items = len >> 2;
  1990. int i;
  1991. for (i = 0; i < items; ++i)
  1992. aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
  1993. /* memcpy from aligned buffer into output buffer */
  1994. memcpy(buf, aligned_buf, len);
  1995. buf += len;
  1996. cnt -= len;
  1997. }
  1998. } else
  1999. #endif
  2000. {
  2001. u32 *pdata = buf;
  2002. for (; cnt >= 4; cnt -= 4)
  2003. *pdata++ = mci_fifo_readl(host->fifo_reg);
  2004. buf = pdata;
  2005. }
  2006. if (cnt) {
  2007. host->part_buf32 = mci_fifo_readl(host->fifo_reg);
  2008. dw_mci_pull_final_bytes(host, buf, cnt);
  2009. }
  2010. }
  2011. static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
  2012. {
  2013. struct mmc_data *data = host->data;
  2014. int init_cnt = cnt;
  2015. /* try and push anything in the part_buf */
  2016. if (unlikely(host->part_buf_count)) {
  2017. int len = dw_mci_push_part_bytes(host, buf, cnt);
  2018. buf += len;
  2019. cnt -= len;
  2020. if (host->part_buf_count == 8) {
  2021. mci_fifo_writeq(host->fifo_reg, host->part_buf);
  2022. host->part_buf_count = 0;
  2023. }
  2024. }
  2025. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  2026. if (unlikely((unsigned long)buf & 0x7)) {
  2027. while (cnt >= 8) {
  2028. u64 aligned_buf[16];
  2029. int len = min(cnt & -8, (int)sizeof(aligned_buf));
  2030. int items = len >> 3;
  2031. int i;
  2032. /* memcpy from input buffer into aligned buffer */
  2033. memcpy(aligned_buf, buf, len);
  2034. buf += len;
  2035. cnt -= len;
  2036. /* push data from aligned buffer into fifo */
  2037. for (i = 0; i < items; ++i)
  2038. mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
  2039. }
  2040. } else
  2041. #endif
  2042. {
  2043. u64 *pdata = buf;
  2044. for (; cnt >= 8; cnt -= 8)
  2045. mci_fifo_writeq(host->fifo_reg, *pdata++);
  2046. buf = pdata;
  2047. }
  2048. /* put anything remaining in the part_buf */
  2049. if (cnt) {
  2050. dw_mci_set_part_bytes(host, buf, cnt);
  2051. /* Push data if we have reached the expected data length */
  2052. if ((data->bytes_xfered + init_cnt) ==
  2053. (data->blksz * data->blocks))
  2054. mci_fifo_writeq(host->fifo_reg, host->part_buf);
  2055. }
  2056. }
  2057. static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
  2058. {
  2059. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  2060. if (unlikely((unsigned long)buf & 0x7)) {
  2061. while (cnt >= 8) {
  2062. /* pull data from fifo into aligned buffer */
  2063. u64 aligned_buf[16];
  2064. int len = min(cnt & -8, (int)sizeof(aligned_buf));
  2065. int items = len >> 3;
  2066. int i;
  2067. for (i = 0; i < items; ++i)
  2068. aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
  2069. /* memcpy from aligned buffer into output buffer */
  2070. memcpy(buf, aligned_buf, len);
  2071. buf += len;
  2072. cnt -= len;
  2073. }
  2074. } else
  2075. #endif
  2076. {
  2077. u64 *pdata = buf;
  2078. for (; cnt >= 8; cnt -= 8)
  2079. *pdata++ = mci_fifo_readq(host->fifo_reg);
  2080. buf = pdata;
  2081. }
  2082. if (cnt) {
  2083. host->part_buf = mci_fifo_readq(host->fifo_reg);
  2084. dw_mci_pull_final_bytes(host, buf, cnt);
  2085. }
  2086. }
  2087. static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
  2088. {
  2089. int len;
  2090. /* get remaining partial bytes */
  2091. len = dw_mci_pull_part_bytes(host, buf, cnt);
  2092. if (unlikely(len == cnt))
  2093. return;
  2094. buf += len;
  2095. cnt -= len;
  2096. /* get the rest of the data */
  2097. host->pull_data(host, buf, cnt);
  2098. }
  2099. static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
  2100. {
  2101. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  2102. void *buf;
  2103. unsigned int offset;
  2104. struct mmc_data *data = host->data;
  2105. int shift = host->data_shift;
  2106. u32 status;
  2107. unsigned int len;
  2108. unsigned int remain, fcnt;
  2109. do {
  2110. if (!sg_miter_next(sg_miter))
  2111. goto done;
  2112. host->sg = sg_miter->piter.sg;
  2113. buf = sg_miter->addr;
  2114. remain = sg_miter->length;
  2115. offset = 0;
  2116. do {
  2117. fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
  2118. << shift) + host->part_buf_count;
  2119. len = min(remain, fcnt);
  2120. if (!len)
  2121. break;
  2122. dw_mci_pull_data(host, (void *)(buf + offset), len);
  2123. data->bytes_xfered += len;
  2124. offset += len;
  2125. remain -= len;
  2126. } while (remain);
  2127. sg_miter->consumed = offset;
  2128. status = mci_readl(host, MINTSTS);
  2129. mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
  2130. /* if the RXDR is ready read again */
  2131. } while ((status & SDMMC_INT_RXDR) ||
  2132. (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
  2133. if (!remain) {
  2134. if (!sg_miter_next(sg_miter))
  2135. goto done;
  2136. sg_miter->consumed = 0;
  2137. }
  2138. sg_miter_stop(sg_miter);
  2139. return;
  2140. done:
  2141. sg_miter_stop(sg_miter);
  2142. host->sg = NULL;
  2143. smp_wmb(); /* drain writebuffer */
  2144. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  2145. }
  2146. static void dw_mci_write_data_pio(struct dw_mci *host)
  2147. {
  2148. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  2149. void *buf;
  2150. unsigned int offset;
  2151. struct mmc_data *data = host->data;
  2152. int shift = host->data_shift;
  2153. u32 status;
  2154. unsigned int len;
  2155. unsigned int fifo_depth = host->fifo_depth;
  2156. unsigned int remain, fcnt;
  2157. do {
  2158. if (!sg_miter_next(sg_miter))
  2159. goto done;
  2160. host->sg = sg_miter->piter.sg;
  2161. buf = sg_miter->addr;
  2162. remain = sg_miter->length;
  2163. offset = 0;
  2164. do {
  2165. fcnt = ((fifo_depth -
  2166. SDMMC_GET_FCNT(mci_readl(host, STATUS)))
  2167. << shift) - host->part_buf_count;
  2168. len = min(remain, fcnt);
  2169. if (!len)
  2170. break;
  2171. host->push_data(host, (void *)(buf + offset), len);
  2172. data->bytes_xfered += len;
  2173. offset += len;
  2174. remain -= len;
  2175. } while (remain);
  2176. sg_miter->consumed = offset;
  2177. status = mci_readl(host, MINTSTS);
  2178. mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
  2179. } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
  2180. if (!remain) {
  2181. if (!sg_miter_next(sg_miter))
  2182. goto done;
  2183. sg_miter->consumed = 0;
  2184. }
  2185. sg_miter_stop(sg_miter);
  2186. return;
  2187. done:
  2188. sg_miter_stop(sg_miter);
  2189. host->sg = NULL;
  2190. smp_wmb(); /* drain writebuffer */
  2191. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  2192. }
  2193. static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
  2194. {
  2195. del_timer(&host->cto_timer);
  2196. if (!host->cmd_status)
  2197. host->cmd_status = status;
  2198. smp_wmb(); /* drain writebuffer */
  2199. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2200. tasklet_schedule(&host->tasklet);
  2201. }
  2202. static void dw_mci_handle_cd(struct dw_mci *host)
  2203. {
  2204. struct dw_mci_slot *slot = host->slot;
  2205. if (slot->mmc->ops->card_event)
  2206. slot->mmc->ops->card_event(slot->mmc);
  2207. mmc_detect_change(slot->mmc,
  2208. msecs_to_jiffies(host->pdata->detect_delay_ms));
  2209. }
  2210. static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
  2211. {
  2212. struct dw_mci *host = dev_id;
  2213. u32 pending;
  2214. struct dw_mci_slot *slot = host->slot;
  2215. unsigned long irqflags;
  2216. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  2217. if (pending) {
  2218. /* Check volt switch first, since it can look like an error */
  2219. if ((host->state == STATE_SENDING_CMD11) &&
  2220. (pending & SDMMC_INT_VOLT_SWITCH)) {
  2221. mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
  2222. pending &= ~SDMMC_INT_VOLT_SWITCH;
  2223. /*
  2224. * Hold the lock; we know cmd11_timer can't be kicked
  2225. * off after the lock is released, so safe to delete.
  2226. */
  2227. spin_lock_irqsave(&host->irq_lock, irqflags);
  2228. dw_mci_cmd_interrupt(host, pending);
  2229. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2230. del_timer(&host->cmd11_timer);
  2231. }
  2232. if (pending & DW_MCI_CMD_ERROR_FLAGS) {
  2233. spin_lock_irqsave(&host->irq_lock, irqflags);
  2234. del_timer(&host->cto_timer);
  2235. mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
  2236. host->cmd_status = pending;
  2237. smp_wmb(); /* drain writebuffer */
  2238. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2239. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2240. }
  2241. if (pending & DW_MCI_DATA_ERROR_FLAGS) {
  2242. /* if there is an error report DATA_ERROR */
  2243. mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
  2244. host->data_status = pending;
  2245. smp_wmb(); /* drain writebuffer */
  2246. set_bit(EVENT_DATA_ERROR, &host->pending_events);
  2247. tasklet_schedule(&host->tasklet);
  2248. }
  2249. if (pending & SDMMC_INT_DATA_OVER) {
  2250. spin_lock_irqsave(&host->irq_lock, irqflags);
  2251. del_timer(&host->dto_timer);
  2252. mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
  2253. if (!host->data_status)
  2254. host->data_status = pending;
  2255. smp_wmb(); /* drain writebuffer */
  2256. if (host->dir_status == DW_MCI_RECV_STATUS) {
  2257. if (host->sg != NULL)
  2258. dw_mci_read_data_pio(host, true);
  2259. }
  2260. set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  2261. tasklet_schedule(&host->tasklet);
  2262. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2263. }
  2264. if (pending & SDMMC_INT_RXDR) {
  2265. mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
  2266. if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
  2267. dw_mci_read_data_pio(host, false);
  2268. }
  2269. if (pending & SDMMC_INT_TXDR) {
  2270. mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
  2271. if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
  2272. dw_mci_write_data_pio(host);
  2273. }
  2274. if (pending & SDMMC_INT_CMD_DONE) {
  2275. spin_lock_irqsave(&host->irq_lock, irqflags);
  2276. mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
  2277. dw_mci_cmd_interrupt(host, pending);
  2278. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2279. }
  2280. if (pending & SDMMC_INT_CD) {
  2281. mci_writel(host, RINTSTS, SDMMC_INT_CD);
  2282. dw_mci_handle_cd(host);
  2283. }
  2284. if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
  2285. mci_writel(host, RINTSTS,
  2286. SDMMC_INT_SDIO(slot->sdio_id));
  2287. __dw_mci_enable_sdio_irq(slot, 0);
  2288. sdio_signal_irq(slot->mmc);
  2289. }
  2290. }
  2291. if (host->use_dma != TRANS_MODE_IDMAC)
  2292. return IRQ_HANDLED;
  2293. /* Handle IDMA interrupts */
  2294. if (host->dma_64bit_address == 1) {
  2295. pending = mci_readl(host, IDSTS64);
  2296. if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
  2297. mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
  2298. SDMMC_IDMAC_INT_RI);
  2299. mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
  2300. if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
  2301. host->dma_ops->complete((void *)host);
  2302. }
  2303. } else {
  2304. pending = mci_readl(host, IDSTS);
  2305. if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
  2306. mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
  2307. SDMMC_IDMAC_INT_RI);
  2308. mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
  2309. if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
  2310. host->dma_ops->complete((void *)host);
  2311. }
  2312. }
  2313. return IRQ_HANDLED;
  2314. }
  2315. static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
  2316. {
  2317. struct dw_mci *host = slot->host;
  2318. const struct dw_mci_drv_data *drv_data = host->drv_data;
  2319. struct mmc_host *mmc = slot->mmc;
  2320. int ctrl_id;
  2321. if (host->pdata->caps)
  2322. mmc->caps = host->pdata->caps;
  2323. /*
  2324. * Support MMC_CAP_ERASE by default.
  2325. * It needs to use trim/discard/erase commands.
  2326. */
  2327. mmc->caps |= MMC_CAP_ERASE;
  2328. if (host->pdata->pm_caps)
  2329. mmc->pm_caps = host->pdata->pm_caps;
  2330. if (host->dev->of_node) {
  2331. ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
  2332. if (ctrl_id < 0)
  2333. ctrl_id = 0;
  2334. } else {
  2335. ctrl_id = to_platform_device(host->dev)->id;
  2336. }
  2337. if (drv_data && drv_data->caps) {
  2338. if (ctrl_id >= drv_data->num_caps) {
  2339. dev_err(host->dev, "invalid controller id %d\n",
  2340. ctrl_id);
  2341. return -EINVAL;
  2342. }
  2343. mmc->caps |= drv_data->caps[ctrl_id];
  2344. }
  2345. if (host->pdata->caps2)
  2346. mmc->caps2 = host->pdata->caps2;
  2347. mmc->f_min = DW_MCI_FREQ_MIN;
  2348. if (!mmc->f_max)
  2349. mmc->f_max = DW_MCI_FREQ_MAX;
  2350. /* Process SDIO IRQs through the sdio_irq_work. */
  2351. if (mmc->caps & MMC_CAP_SDIO_IRQ)
  2352. mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
  2353. return 0;
  2354. }
  2355. static int dw_mci_init_slot(struct dw_mci *host)
  2356. {
  2357. struct mmc_host *mmc;
  2358. struct dw_mci_slot *slot;
  2359. int ret;
  2360. mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
  2361. if (!mmc)
  2362. return -ENOMEM;
  2363. slot = mmc_priv(mmc);
  2364. slot->id = 0;
  2365. slot->sdio_id = host->sdio_id0 + slot->id;
  2366. slot->mmc = mmc;
  2367. slot->host = host;
  2368. host->slot = slot;
  2369. mmc->ops = &dw_mci_ops;
  2370. /*if there are external regulators, get them*/
  2371. ret = mmc_regulator_get_supply(mmc);
  2372. if (ret)
  2373. goto err_host_allocated;
  2374. if (!mmc->ocr_avail)
  2375. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  2376. ret = mmc_of_parse(mmc);
  2377. if (ret)
  2378. goto err_host_allocated;
  2379. ret = dw_mci_init_slot_caps(slot);
  2380. if (ret)
  2381. goto err_host_allocated;
  2382. /* Useful defaults if platform data is unset. */
  2383. if (host->use_dma == TRANS_MODE_IDMAC) {
  2384. mmc->max_segs = host->ring_size;
  2385. mmc->max_blk_size = 65535;
  2386. mmc->max_seg_size = 0x1000;
  2387. mmc->max_req_size = mmc->max_seg_size * host->ring_size;
  2388. mmc->max_blk_count = mmc->max_req_size / 512;
  2389. } else if (host->use_dma == TRANS_MODE_EDMAC) {
  2390. mmc->max_segs = 64;
  2391. mmc->max_blk_size = 65535;
  2392. mmc->max_blk_count = 65535;
  2393. mmc->max_req_size =
  2394. mmc->max_blk_size * mmc->max_blk_count;
  2395. mmc->max_seg_size = mmc->max_req_size;
  2396. } else {
  2397. /* TRANS_MODE_PIO */
  2398. mmc->max_segs = 64;
  2399. mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
  2400. mmc->max_blk_count = 512;
  2401. mmc->max_req_size = mmc->max_blk_size *
  2402. mmc->max_blk_count;
  2403. mmc->max_seg_size = mmc->max_req_size;
  2404. }
  2405. dw_mci_get_cd(mmc);
  2406. ret = mmc_add_host(mmc);
  2407. if (ret)
  2408. goto err_host_allocated;
  2409. #if defined(CONFIG_DEBUG_FS)
  2410. dw_mci_init_debugfs(slot);
  2411. #endif
  2412. return 0;
  2413. err_host_allocated:
  2414. mmc_free_host(mmc);
  2415. return ret;
  2416. }
  2417. static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
  2418. {
  2419. /* Debugfs stuff is cleaned up by mmc core */
  2420. mmc_remove_host(slot->mmc);
  2421. slot->host->slot = NULL;
  2422. mmc_free_host(slot->mmc);
  2423. }
  2424. static void dw_mci_init_dma(struct dw_mci *host)
  2425. {
  2426. int addr_config;
  2427. struct device *dev = host->dev;
  2428. /*
  2429. * Check tansfer mode from HCON[17:16]
  2430. * Clear the ambiguous description of dw_mmc databook:
  2431. * 2b'00: No DMA Interface -> Actually means using Internal DMA block
  2432. * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
  2433. * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
  2434. * 2b'11: Non DW DMA Interface -> pio only
  2435. * Compared to DesignWare DMA Interface, Generic DMA Interface has a
  2436. * simpler request/acknowledge handshake mechanism and both of them
  2437. * are regarded as external dma master for dw_mmc.
  2438. */
  2439. host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
  2440. if (host->use_dma == DMA_INTERFACE_IDMA) {
  2441. host->use_dma = TRANS_MODE_IDMAC;
  2442. } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
  2443. host->use_dma == DMA_INTERFACE_GDMA) {
  2444. host->use_dma = TRANS_MODE_EDMAC;
  2445. } else {
  2446. goto no_dma;
  2447. }
  2448. /* Determine which DMA interface to use */
  2449. if (host->use_dma == TRANS_MODE_IDMAC) {
  2450. /*
  2451. * Check ADDR_CONFIG bit in HCON to find
  2452. * IDMAC address bus width
  2453. */
  2454. addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
  2455. if (addr_config == 1) {
  2456. /* host supports IDMAC in 64-bit address mode */
  2457. host->dma_64bit_address = 1;
  2458. dev_info(host->dev,
  2459. "IDMAC supports 64-bit address mode.\n");
  2460. if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
  2461. dma_set_coherent_mask(host->dev,
  2462. DMA_BIT_MASK(64));
  2463. } else {
  2464. /* host supports IDMAC in 32-bit address mode */
  2465. host->dma_64bit_address = 0;
  2466. dev_info(host->dev,
  2467. "IDMAC supports 32-bit address mode.\n");
  2468. }
  2469. /* Alloc memory for sg translation */
  2470. host->sg_cpu = dmam_alloc_coherent(host->dev,
  2471. DESC_RING_BUF_SZ,
  2472. &host->sg_dma, GFP_KERNEL);
  2473. if (!host->sg_cpu) {
  2474. dev_err(host->dev,
  2475. "%s: could not alloc DMA memory\n",
  2476. __func__);
  2477. goto no_dma;
  2478. }
  2479. host->dma_ops = &dw_mci_idmac_ops;
  2480. dev_info(host->dev, "Using internal DMA controller.\n");
  2481. } else {
  2482. /* TRANS_MODE_EDMAC: check dma bindings again */
  2483. if ((device_property_read_string_array(dev, "dma-names",
  2484. NULL, 0) < 0) ||
  2485. !device_property_present(dev, "dmas")) {
  2486. goto no_dma;
  2487. }
  2488. host->dma_ops = &dw_mci_edmac_ops;
  2489. dev_info(host->dev, "Using external DMA controller.\n");
  2490. }
  2491. if (host->dma_ops->init && host->dma_ops->start &&
  2492. host->dma_ops->stop && host->dma_ops->cleanup) {
  2493. if (host->dma_ops->init(host)) {
  2494. dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
  2495. __func__);
  2496. goto no_dma;
  2497. }
  2498. } else {
  2499. dev_err(host->dev, "DMA initialization not found.\n");
  2500. goto no_dma;
  2501. }
  2502. return;
  2503. no_dma:
  2504. dev_info(host->dev, "Using PIO mode.\n");
  2505. host->use_dma = TRANS_MODE_PIO;
  2506. }
  2507. static void dw_mci_cmd11_timer(struct timer_list *t)
  2508. {
  2509. struct dw_mci *host = from_timer(host, t, cmd11_timer);
  2510. if (host->state != STATE_SENDING_CMD11) {
  2511. dev_warn(host->dev, "Unexpected CMD11 timeout\n");
  2512. return;
  2513. }
  2514. host->cmd_status = SDMMC_INT_RTO;
  2515. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2516. tasklet_schedule(&host->tasklet);
  2517. }
  2518. static void dw_mci_cto_timer(struct timer_list *t)
  2519. {
  2520. struct dw_mci *host = from_timer(host, t, cto_timer);
  2521. unsigned long irqflags;
  2522. u32 pending;
  2523. spin_lock_irqsave(&host->irq_lock, irqflags);
  2524. /*
  2525. * If somehow we have very bad interrupt latency it's remotely possible
  2526. * that the timer could fire while the interrupt is still pending or
  2527. * while the interrupt is midway through running. Let's be paranoid
  2528. * and detect those two cases. Note that this is paranoia is somewhat
  2529. * justified because in this function we don't actually cancel the
  2530. * pending command in the controller--we just assume it will never come.
  2531. */
  2532. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  2533. if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
  2534. /* The interrupt should fire; no need to act but we can warn */
  2535. dev_warn(host->dev, "Unexpected interrupt latency\n");
  2536. goto exit;
  2537. }
  2538. if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
  2539. /* Presumably interrupt handler couldn't delete the timer */
  2540. dev_warn(host->dev, "CTO timeout when already completed\n");
  2541. goto exit;
  2542. }
  2543. /*
  2544. * Continued paranoia to make sure we're in the state we expect.
  2545. * This paranoia isn't really justified but it seems good to be safe.
  2546. */
  2547. switch (host->state) {
  2548. case STATE_SENDING_CMD11:
  2549. case STATE_SENDING_CMD:
  2550. case STATE_SENDING_STOP:
  2551. /*
  2552. * If CMD_DONE interrupt does NOT come in sending command
  2553. * state, we should notify the driver to terminate current
  2554. * transfer and report a command timeout to the core.
  2555. */
  2556. host->cmd_status = SDMMC_INT_RTO;
  2557. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  2558. tasklet_schedule(&host->tasklet);
  2559. break;
  2560. default:
  2561. dev_warn(host->dev, "Unexpected command timeout, state %d\n",
  2562. host->state);
  2563. break;
  2564. }
  2565. exit:
  2566. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2567. }
  2568. static void dw_mci_dto_timer(struct timer_list *t)
  2569. {
  2570. struct dw_mci *host = from_timer(host, t, dto_timer);
  2571. unsigned long irqflags;
  2572. u32 pending;
  2573. spin_lock_irqsave(&host->irq_lock, irqflags);
  2574. /*
  2575. * The DTO timer is much longer than the CTO timer, so it's even less
  2576. * likely that we'll these cases, but it pays to be paranoid.
  2577. */
  2578. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  2579. if (pending & SDMMC_INT_DATA_OVER) {
  2580. /* The interrupt should fire; no need to act but we can warn */
  2581. dev_warn(host->dev, "Unexpected data interrupt latency\n");
  2582. goto exit;
  2583. }
  2584. if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
  2585. /* Presumably interrupt handler couldn't delete the timer */
  2586. dev_warn(host->dev, "DTO timeout when already completed\n");
  2587. goto exit;
  2588. }
  2589. /*
  2590. * Continued paranoia to make sure we're in the state we expect.
  2591. * This paranoia isn't really justified but it seems good to be safe.
  2592. */
  2593. switch (host->state) {
  2594. case STATE_SENDING_DATA:
  2595. case STATE_DATA_BUSY:
  2596. /*
  2597. * If DTO interrupt does NOT come in sending data state,
  2598. * we should notify the driver to terminate current transfer
  2599. * and report a data timeout to the core.
  2600. */
  2601. host->data_status = SDMMC_INT_DRTO;
  2602. set_bit(EVENT_DATA_ERROR, &host->pending_events);
  2603. set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  2604. tasklet_schedule(&host->tasklet);
  2605. break;
  2606. default:
  2607. dev_warn(host->dev, "Unexpected data timeout, state %d\n",
  2608. host->state);
  2609. break;
  2610. }
  2611. exit:
  2612. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2613. }
  2614. #ifdef CONFIG_OF
  2615. static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
  2616. {
  2617. struct dw_mci_board *pdata;
  2618. struct device *dev = host->dev;
  2619. const struct dw_mci_drv_data *drv_data = host->drv_data;
  2620. int ret;
  2621. u32 clock_frequency;
  2622. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  2623. if (!pdata)
  2624. return ERR_PTR(-ENOMEM);
  2625. /* find reset controller when exist */
  2626. pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
  2627. if (IS_ERR(pdata->rstc)) {
  2628. if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
  2629. return ERR_PTR(-EPROBE_DEFER);
  2630. }
  2631. if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
  2632. dev_info(dev,
  2633. "fifo-depth property not found, using value of FIFOTH register as default\n");
  2634. device_property_read_u32(dev, "card-detect-delay",
  2635. &pdata->detect_delay_ms);
  2636. device_property_read_u32(dev, "data-addr", &host->data_addr_override);
  2637. if (device_property_present(dev, "fifo-watermark-aligned"))
  2638. host->wm_aligned = true;
  2639. if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
  2640. pdata->bus_hz = clock_frequency;
  2641. if (drv_data && drv_data->parse_dt) {
  2642. ret = drv_data->parse_dt(host);
  2643. if (ret)
  2644. return ERR_PTR(ret);
  2645. }
  2646. return pdata;
  2647. }
  2648. #else /* CONFIG_OF */
  2649. static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
  2650. {
  2651. return ERR_PTR(-EINVAL);
  2652. }
  2653. #endif /* CONFIG_OF */
  2654. static void dw_mci_enable_cd(struct dw_mci *host)
  2655. {
  2656. unsigned long irqflags;
  2657. u32 temp;
  2658. /*
  2659. * No need for CD if all slots have a non-error GPIO
  2660. * as well as broken card detection is found.
  2661. */
  2662. if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
  2663. return;
  2664. if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
  2665. spin_lock_irqsave(&host->irq_lock, irqflags);
  2666. temp = mci_readl(host, INTMASK);
  2667. temp |= SDMMC_INT_CD;
  2668. mci_writel(host, INTMASK, temp);
  2669. spin_unlock_irqrestore(&host->irq_lock, irqflags);
  2670. }
  2671. }
  2672. int dw_mci_probe(struct dw_mci *host)
  2673. {
  2674. const struct dw_mci_drv_data *drv_data = host->drv_data;
  2675. int width, i, ret = 0;
  2676. u32 fifo_size;
  2677. if (!host->pdata) {
  2678. host->pdata = dw_mci_parse_dt(host);
  2679. if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
  2680. return -EPROBE_DEFER;
  2681. } else if (IS_ERR(host->pdata)) {
  2682. dev_err(host->dev, "platform data not available\n");
  2683. return -EINVAL;
  2684. }
  2685. }
  2686. host->biu_clk = devm_clk_get(host->dev, "biu");
  2687. if (IS_ERR(host->biu_clk)) {
  2688. dev_dbg(host->dev, "biu clock not available\n");
  2689. } else {
  2690. ret = clk_prepare_enable(host->biu_clk);
  2691. if (ret) {
  2692. dev_err(host->dev, "failed to enable biu clock\n");
  2693. return ret;
  2694. }
  2695. }
  2696. host->ciu_clk = devm_clk_get(host->dev, "ciu");
  2697. if (IS_ERR(host->ciu_clk)) {
  2698. dev_dbg(host->dev, "ciu clock not available\n");
  2699. host->bus_hz = host->pdata->bus_hz;
  2700. } else {
  2701. ret = clk_prepare_enable(host->ciu_clk);
  2702. if (ret) {
  2703. dev_err(host->dev, "failed to enable ciu clock\n");
  2704. goto err_clk_biu;
  2705. }
  2706. if (host->pdata->bus_hz) {
  2707. ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
  2708. if (ret)
  2709. dev_warn(host->dev,
  2710. "Unable to set bus rate to %uHz\n",
  2711. host->pdata->bus_hz);
  2712. }
  2713. host->bus_hz = clk_get_rate(host->ciu_clk);
  2714. }
  2715. if (!host->bus_hz) {
  2716. dev_err(host->dev,
  2717. "Platform data must supply bus speed\n");
  2718. ret = -ENODEV;
  2719. goto err_clk_ciu;
  2720. }
  2721. if (!IS_ERR(host->pdata->rstc)) {
  2722. reset_control_assert(host->pdata->rstc);
  2723. usleep_range(10, 50);
  2724. reset_control_deassert(host->pdata->rstc);
  2725. }
  2726. if (drv_data && drv_data->init) {
  2727. ret = drv_data->init(host);
  2728. if (ret) {
  2729. dev_err(host->dev,
  2730. "implementation specific init failed\n");
  2731. goto err_clk_ciu;
  2732. }
  2733. }
  2734. timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
  2735. timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
  2736. timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
  2737. spin_lock_init(&host->lock);
  2738. spin_lock_init(&host->irq_lock);
  2739. INIT_LIST_HEAD(&host->queue);
  2740. /*
  2741. * Get the host data width - this assumes that HCON has been set with
  2742. * the correct values.
  2743. */
  2744. i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
  2745. if (!i) {
  2746. host->push_data = dw_mci_push_data16;
  2747. host->pull_data = dw_mci_pull_data16;
  2748. width = 16;
  2749. host->data_shift = 1;
  2750. } else if (i == 2) {
  2751. host->push_data = dw_mci_push_data64;
  2752. host->pull_data = dw_mci_pull_data64;
  2753. width = 64;
  2754. host->data_shift = 3;
  2755. } else {
  2756. /* Check for a reserved value, and warn if it is */
  2757. WARN((i != 1),
  2758. "HCON reports a reserved host data width!\n"
  2759. "Defaulting to 32-bit access.\n");
  2760. host->push_data = dw_mci_push_data32;
  2761. host->pull_data = dw_mci_pull_data32;
  2762. width = 32;
  2763. host->data_shift = 2;
  2764. }
  2765. /* Reset all blocks */
  2766. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
  2767. ret = -ENODEV;
  2768. goto err_clk_ciu;
  2769. }
  2770. host->dma_ops = host->pdata->dma_ops;
  2771. dw_mci_init_dma(host);
  2772. /* Clear the interrupts for the host controller */
  2773. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2774. mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
  2775. /* Put in max timeout */
  2776. mci_writel(host, TMOUT, 0xFFFFFFFF);
  2777. /*
  2778. * FIFO threshold settings RxMark = fifo_size / 2 - 1,
  2779. * Tx Mark = fifo_size / 2 DMA Size = 8
  2780. */
  2781. if (!host->pdata->fifo_depth) {
  2782. /*
  2783. * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
  2784. * have been overwritten by the bootloader, just like we're
  2785. * about to do, so if you know the value for your hardware, you
  2786. * should put it in the platform data.
  2787. */
  2788. fifo_size = mci_readl(host, FIFOTH);
  2789. fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
  2790. } else {
  2791. fifo_size = host->pdata->fifo_depth;
  2792. }
  2793. host->fifo_depth = fifo_size;
  2794. host->fifoth_val =
  2795. SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
  2796. mci_writel(host, FIFOTH, host->fifoth_val);
  2797. /* disable clock to CIU */
  2798. mci_writel(host, CLKENA, 0);
  2799. mci_writel(host, CLKSRC, 0);
  2800. /*
  2801. * In 2.40a spec, Data offset is changed.
  2802. * Need to check the version-id and set data-offset for DATA register.
  2803. */
  2804. host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
  2805. dev_info(host->dev, "Version ID is %04x\n", host->verid);
  2806. if (host->data_addr_override)
  2807. host->fifo_reg = host->regs + host->data_addr_override;
  2808. else if (host->verid < DW_MMC_240A)
  2809. host->fifo_reg = host->regs + DATA_OFFSET;
  2810. else
  2811. host->fifo_reg = host->regs + DATA_240A_OFFSET;
  2812. tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
  2813. ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
  2814. host->irq_flags, "dw-mci", host);
  2815. if (ret)
  2816. goto err_dmaunmap;
  2817. /*
  2818. * Enable interrupts for command done, data over, data empty,
  2819. * receive ready and error such as transmit, receive timeout, crc error
  2820. */
  2821. mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
  2822. SDMMC_INT_TXDR | SDMMC_INT_RXDR |
  2823. DW_MCI_ERROR_FLAGS);
  2824. /* Enable mci interrupt */
  2825. mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
  2826. dev_info(host->dev,
  2827. "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
  2828. host->irq, width, fifo_size);
  2829. /* We need at least one slot to succeed */
  2830. ret = dw_mci_init_slot(host);
  2831. if (ret) {
  2832. dev_dbg(host->dev, "slot %d init failed\n", i);
  2833. goto err_dmaunmap;
  2834. }
  2835. /* Now that slots are all setup, we can enable card detect */
  2836. dw_mci_enable_cd(host);
  2837. return 0;
  2838. err_dmaunmap:
  2839. if (host->use_dma && host->dma_ops->exit)
  2840. host->dma_ops->exit(host);
  2841. if (!IS_ERR(host->pdata->rstc))
  2842. reset_control_assert(host->pdata->rstc);
  2843. err_clk_ciu:
  2844. clk_disable_unprepare(host->ciu_clk);
  2845. err_clk_biu:
  2846. clk_disable_unprepare(host->biu_clk);
  2847. return ret;
  2848. }
  2849. EXPORT_SYMBOL(dw_mci_probe);
  2850. void dw_mci_remove(struct dw_mci *host)
  2851. {
  2852. dev_dbg(host->dev, "remove slot\n");
  2853. if (host->slot)
  2854. dw_mci_cleanup_slot(host->slot);
  2855. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2856. mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
  2857. /* disable clock to CIU */
  2858. mci_writel(host, CLKENA, 0);
  2859. mci_writel(host, CLKSRC, 0);
  2860. if (host->use_dma && host->dma_ops->exit)
  2861. host->dma_ops->exit(host);
  2862. if (!IS_ERR(host->pdata->rstc))
  2863. reset_control_assert(host->pdata->rstc);
  2864. clk_disable_unprepare(host->ciu_clk);
  2865. clk_disable_unprepare(host->biu_clk);
  2866. }
  2867. EXPORT_SYMBOL(dw_mci_remove);
  2868. #ifdef CONFIG_PM
  2869. int dw_mci_runtime_suspend(struct device *dev)
  2870. {
  2871. struct dw_mci *host = dev_get_drvdata(dev);
  2872. if (host->use_dma && host->dma_ops->exit)
  2873. host->dma_ops->exit(host);
  2874. clk_disable_unprepare(host->ciu_clk);
  2875. if (host->slot &&
  2876. (mmc_can_gpio_cd(host->slot->mmc) ||
  2877. !mmc_card_is_removable(host->slot->mmc)))
  2878. clk_disable_unprepare(host->biu_clk);
  2879. return 0;
  2880. }
  2881. EXPORT_SYMBOL(dw_mci_runtime_suspend);
  2882. int dw_mci_runtime_resume(struct device *dev)
  2883. {
  2884. int ret = 0;
  2885. struct dw_mci *host = dev_get_drvdata(dev);
  2886. if (host->slot &&
  2887. (mmc_can_gpio_cd(host->slot->mmc) ||
  2888. !mmc_card_is_removable(host->slot->mmc))) {
  2889. ret = clk_prepare_enable(host->biu_clk);
  2890. if (ret)
  2891. return ret;
  2892. }
  2893. ret = clk_prepare_enable(host->ciu_clk);
  2894. if (ret)
  2895. goto err;
  2896. if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
  2897. clk_disable_unprepare(host->ciu_clk);
  2898. ret = -ENODEV;
  2899. goto err;
  2900. }
  2901. if (host->use_dma && host->dma_ops->init)
  2902. host->dma_ops->init(host);
  2903. /*
  2904. * Restore the initial value at FIFOTH register
  2905. * And Invalidate the prev_blksz with zero
  2906. */
  2907. mci_writel(host, FIFOTH, host->fifoth_val);
  2908. host->prev_blksz = 0;
  2909. /* Put in max timeout */
  2910. mci_writel(host, TMOUT, 0xFFFFFFFF);
  2911. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2912. mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
  2913. SDMMC_INT_TXDR | SDMMC_INT_RXDR |
  2914. DW_MCI_ERROR_FLAGS);
  2915. mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
  2916. if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
  2917. dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
  2918. /* Force setup bus to guarantee available clock output */
  2919. dw_mci_setup_bus(host->slot, true);
  2920. /* Re-enable SDIO interrupts. */
  2921. if (sdio_irq_claimed(host->slot->mmc))
  2922. __dw_mci_enable_sdio_irq(host->slot, 1);
  2923. /* Now that slots are all setup, we can enable card detect */
  2924. dw_mci_enable_cd(host);
  2925. return 0;
  2926. err:
  2927. if (host->slot &&
  2928. (mmc_can_gpio_cd(host->slot->mmc) ||
  2929. !mmc_card_is_removable(host->slot->mmc)))
  2930. clk_disable_unprepare(host->biu_clk);
  2931. return ret;
  2932. }
  2933. EXPORT_SYMBOL(dw_mci_runtime_resume);
  2934. #endif /* CONFIG_PM */
  2935. #if 0
  2936. static int __init dw_mci_init(void)
  2937. {
  2938. pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
  2939. return 0;
  2940. }
  2941. static void __exit dw_mci_exit(void)
  2942. {
  2943. }
  2944. module_init(dw_mci_init);
  2945. module_exit(dw_mci_exit);
  2946. MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
  2947. MODULE_AUTHOR("NXP Semiconductor VietNam");
  2948. MODULE_AUTHOR("Imagination Technologies Ltd");
  2949. MODULE_LICENSE("GPL v2");
  2950. #endif