jz4740_mmc.c 29 KB

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  1. /*
  2. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3. * Copyright (C) 2013, Imagination Technologies
  4. *
  5. * JZ4740 SD/MMC controller driver
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. * You should have received a copy of the GNU General Public License along
  13. * with this program; if not, write to the Free Software Foundation, Inc.,
  14. * 675 Mass Ave, Cambridge, MA 02139, USA.
  15. *
  16. */
  17. #include <linux/bitops.h>
  18. #include <linux/clk.h>
  19. #include <linux/delay.h>
  20. #include <linux/dmaengine.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/err.h>
  23. #include <linux/gpio.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/io.h>
  26. #include <linux/irq.h>
  27. #include <linux/mmc/host.h>
  28. #include <linux/mmc/slot-gpio.h>
  29. #include <linux/module.h>
  30. #include <linux/of_device.h>
  31. #include <linux/pinctrl/consumer.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/scatterlist.h>
  34. #include <asm/cacheflush.h>
  35. #include <asm/mach-jz4740/dma.h>
  36. #include <asm/mach-jz4740/jz4740_mmc.h>
  37. #define JZ_REG_MMC_STRPCL 0x00
  38. #define JZ_REG_MMC_STATUS 0x04
  39. #define JZ_REG_MMC_CLKRT 0x08
  40. #define JZ_REG_MMC_CMDAT 0x0C
  41. #define JZ_REG_MMC_RESTO 0x10
  42. #define JZ_REG_MMC_RDTO 0x14
  43. #define JZ_REG_MMC_BLKLEN 0x18
  44. #define JZ_REG_MMC_NOB 0x1C
  45. #define JZ_REG_MMC_SNOB 0x20
  46. #define JZ_REG_MMC_IMASK 0x24
  47. #define JZ_REG_MMC_IREG 0x28
  48. #define JZ_REG_MMC_CMD 0x2C
  49. #define JZ_REG_MMC_ARG 0x30
  50. #define JZ_REG_MMC_RESP_FIFO 0x34
  51. #define JZ_REG_MMC_RXFIFO 0x38
  52. #define JZ_REG_MMC_TXFIFO 0x3C
  53. #define JZ_REG_MMC_DMAC 0x44
  54. #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
  55. #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
  56. #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
  57. #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
  58. #define JZ_MMC_STRPCL_RESET BIT(3)
  59. #define JZ_MMC_STRPCL_START_OP BIT(2)
  60. #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
  61. #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
  62. #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
  63. #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
  64. #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
  65. #define JZ_MMC_STATUS_PRG_DONE BIT(13)
  66. #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
  67. #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
  68. #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
  69. #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
  70. #define JZ_MMC_STATUS_CLK_EN BIT(8)
  71. #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
  72. #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
  73. #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
  74. #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
  75. #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
  76. #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
  77. #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
  78. #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
  79. #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
  80. #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
  81. #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
  82. #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
  83. #define JZ_MMC_CMDAT_DMA_EN BIT(8)
  84. #define JZ_MMC_CMDAT_INIT BIT(7)
  85. #define JZ_MMC_CMDAT_BUSY BIT(6)
  86. #define JZ_MMC_CMDAT_STREAM BIT(5)
  87. #define JZ_MMC_CMDAT_WRITE BIT(4)
  88. #define JZ_MMC_CMDAT_DATA_EN BIT(3)
  89. #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
  90. #define JZ_MMC_CMDAT_RSP_R1 1
  91. #define JZ_MMC_CMDAT_RSP_R2 2
  92. #define JZ_MMC_CMDAT_RSP_R3 3
  93. #define JZ_MMC_IRQ_SDIO BIT(7)
  94. #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
  95. #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
  96. #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
  97. #define JZ_MMC_IRQ_PRG_DONE BIT(1)
  98. #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
  99. #define JZ_MMC_DMAC_DMA_SEL BIT(1)
  100. #define JZ_MMC_DMAC_DMA_EN BIT(0)
  101. #define JZ_MMC_CLK_RATE 24000000
  102. enum jz4740_mmc_version {
  103. JZ_MMC_JZ4740,
  104. JZ_MMC_JZ4750,
  105. JZ_MMC_JZ4780,
  106. };
  107. enum jz4740_mmc_state {
  108. JZ4740_MMC_STATE_READ_RESPONSE,
  109. JZ4740_MMC_STATE_TRANSFER_DATA,
  110. JZ4740_MMC_STATE_SEND_STOP,
  111. JZ4740_MMC_STATE_DONE,
  112. };
  113. struct jz4740_mmc_host_next {
  114. int sg_len;
  115. s32 cookie;
  116. };
  117. struct jz4740_mmc_host {
  118. struct mmc_host *mmc;
  119. struct platform_device *pdev;
  120. struct jz4740_mmc_platform_data *pdata;
  121. struct clk *clk;
  122. enum jz4740_mmc_version version;
  123. int irq;
  124. int card_detect_irq;
  125. void __iomem *base;
  126. struct resource *mem_res;
  127. struct mmc_request *req;
  128. struct mmc_command *cmd;
  129. unsigned long waiting;
  130. uint32_t cmdat;
  131. uint32_t irq_mask;
  132. spinlock_t lock;
  133. struct timer_list timeout_timer;
  134. struct sg_mapping_iter miter;
  135. enum jz4740_mmc_state state;
  136. /* DMA support */
  137. struct dma_chan *dma_rx;
  138. struct dma_chan *dma_tx;
  139. struct jz4740_mmc_host_next next_data;
  140. bool use_dma;
  141. int sg_len;
  142. /* The DMA trigger level is 8 words, that is to say, the DMA read
  143. * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write
  144. * trigger is when data words in MSC_TXFIFO is < 8.
  145. */
  146. #define JZ4740_MMC_FIFO_HALF_SIZE 8
  147. };
  148. static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host,
  149. uint32_t val)
  150. {
  151. if (host->version >= JZ_MMC_JZ4750)
  152. return writel(val, host->base + JZ_REG_MMC_IMASK);
  153. else
  154. return writew(val, host->base + JZ_REG_MMC_IMASK);
  155. }
  156. static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host,
  157. uint32_t val)
  158. {
  159. if (host->version >= JZ_MMC_JZ4780)
  160. return writel(val, host->base + JZ_REG_MMC_IREG);
  161. else
  162. return writew(val, host->base + JZ_REG_MMC_IREG);
  163. }
  164. static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host)
  165. {
  166. if (host->version >= JZ_MMC_JZ4780)
  167. return readl(host->base + JZ_REG_MMC_IREG);
  168. else
  169. return readw(host->base + JZ_REG_MMC_IREG);
  170. }
  171. /*----------------------------------------------------------------------------*/
  172. /* DMA infrastructure */
  173. static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
  174. {
  175. if (!host->use_dma)
  176. return;
  177. dma_release_channel(host->dma_tx);
  178. dma_release_channel(host->dma_rx);
  179. }
  180. static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
  181. {
  182. host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
  183. if (IS_ERR(host->dma_tx)) {
  184. dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
  185. return PTR_ERR(host->dma_tx);
  186. }
  187. host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
  188. if (IS_ERR(host->dma_rx)) {
  189. dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
  190. dma_release_channel(host->dma_tx);
  191. return PTR_ERR(host->dma_rx);
  192. }
  193. /* Initialize DMA pre request cookie */
  194. host->next_data.cookie = 1;
  195. return 0;
  196. }
  197. static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host,
  198. struct mmc_data *data)
  199. {
  200. return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx;
  201. }
  202. static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
  203. struct mmc_data *data)
  204. {
  205. struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
  206. enum dma_data_direction dir = mmc_get_dma_dir(data);
  207. dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
  208. }
  209. /* Prepares DMA data for current/next transfer, returns non-zero on failure */
  210. static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host,
  211. struct mmc_data *data,
  212. struct jz4740_mmc_host_next *next,
  213. struct dma_chan *chan)
  214. {
  215. struct jz4740_mmc_host_next *next_data = &host->next_data;
  216. enum dma_data_direction dir = mmc_get_dma_dir(data);
  217. int sg_len;
  218. if (!next && data->host_cookie &&
  219. data->host_cookie != host->next_data.cookie) {
  220. dev_warn(mmc_dev(host->mmc),
  221. "[%s] invalid cookie: data->host_cookie %d host->next_data.cookie %d\n",
  222. __func__,
  223. data->host_cookie,
  224. host->next_data.cookie);
  225. data->host_cookie = 0;
  226. }
  227. /* Check if next job is already prepared */
  228. if (next || data->host_cookie != host->next_data.cookie) {
  229. sg_len = dma_map_sg(chan->device->dev,
  230. data->sg,
  231. data->sg_len,
  232. dir);
  233. } else {
  234. sg_len = next_data->sg_len;
  235. next_data->sg_len = 0;
  236. }
  237. if (sg_len <= 0) {
  238. dev_err(mmc_dev(host->mmc),
  239. "Failed to map scatterlist for DMA operation\n");
  240. return -EINVAL;
  241. }
  242. if (next) {
  243. next->sg_len = sg_len;
  244. data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
  245. } else
  246. host->sg_len = sg_len;
  247. return 0;
  248. }
  249. static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
  250. struct mmc_data *data)
  251. {
  252. int ret;
  253. struct dma_chan *chan;
  254. struct dma_async_tx_descriptor *desc;
  255. struct dma_slave_config conf = {
  256. .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  257. .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  258. .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
  259. .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
  260. };
  261. if (data->flags & MMC_DATA_WRITE) {
  262. conf.direction = DMA_MEM_TO_DEV;
  263. conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
  264. conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT;
  265. chan = host->dma_tx;
  266. } else {
  267. conf.direction = DMA_DEV_TO_MEM;
  268. conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
  269. conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE;
  270. chan = host->dma_rx;
  271. }
  272. ret = jz4740_mmc_prepare_dma_data(host, data, NULL, chan);
  273. if (ret)
  274. return ret;
  275. dmaengine_slave_config(chan, &conf);
  276. desc = dmaengine_prep_slave_sg(chan,
  277. data->sg,
  278. host->sg_len,
  279. conf.direction,
  280. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  281. if (!desc) {
  282. dev_err(mmc_dev(host->mmc),
  283. "Failed to allocate DMA %s descriptor",
  284. conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX");
  285. goto dma_unmap;
  286. }
  287. dmaengine_submit(desc);
  288. dma_async_issue_pending(chan);
  289. return 0;
  290. dma_unmap:
  291. jz4740_mmc_dma_unmap(host, data);
  292. return -ENOMEM;
  293. }
  294. static void jz4740_mmc_pre_request(struct mmc_host *mmc,
  295. struct mmc_request *mrq)
  296. {
  297. struct jz4740_mmc_host *host = mmc_priv(mmc);
  298. struct mmc_data *data = mrq->data;
  299. struct jz4740_mmc_host_next *next_data = &host->next_data;
  300. BUG_ON(data->host_cookie);
  301. if (host->use_dma) {
  302. struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
  303. if (jz4740_mmc_prepare_dma_data(host, data, next_data, chan))
  304. data->host_cookie = 0;
  305. }
  306. }
  307. static void jz4740_mmc_post_request(struct mmc_host *mmc,
  308. struct mmc_request *mrq,
  309. int err)
  310. {
  311. struct jz4740_mmc_host *host = mmc_priv(mmc);
  312. struct mmc_data *data = mrq->data;
  313. if (host->use_dma && data->host_cookie) {
  314. jz4740_mmc_dma_unmap(host, data);
  315. data->host_cookie = 0;
  316. }
  317. if (err) {
  318. struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
  319. dmaengine_terminate_all(chan);
  320. }
  321. }
  322. /*----------------------------------------------------------------------------*/
  323. static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
  324. unsigned int irq, bool enabled)
  325. {
  326. unsigned long flags;
  327. spin_lock_irqsave(&host->lock, flags);
  328. if (enabled)
  329. host->irq_mask &= ~irq;
  330. else
  331. host->irq_mask |= irq;
  332. jz4740_mmc_write_irq_mask(host, host->irq_mask);
  333. spin_unlock_irqrestore(&host->lock, flags);
  334. }
  335. static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
  336. bool start_transfer)
  337. {
  338. uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
  339. if (start_transfer)
  340. val |= JZ_MMC_STRPCL_START_OP;
  341. writew(val, host->base + JZ_REG_MMC_STRPCL);
  342. }
  343. static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
  344. {
  345. uint32_t status;
  346. unsigned int timeout = 1000;
  347. writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
  348. do {
  349. status = readl(host->base + JZ_REG_MMC_STATUS);
  350. } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
  351. }
  352. static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
  353. {
  354. uint32_t status;
  355. unsigned int timeout = 1000;
  356. writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
  357. udelay(10);
  358. do {
  359. status = readl(host->base + JZ_REG_MMC_STATUS);
  360. } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
  361. }
  362. static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
  363. {
  364. struct mmc_request *req;
  365. req = host->req;
  366. host->req = NULL;
  367. mmc_request_done(host->mmc, req);
  368. }
  369. static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
  370. unsigned int irq)
  371. {
  372. unsigned int timeout = 0x800;
  373. uint32_t status;
  374. do {
  375. status = jz4740_mmc_read_irq_reg(host);
  376. } while (!(status & irq) && --timeout);
  377. if (timeout == 0) {
  378. set_bit(0, &host->waiting);
  379. mod_timer(&host->timeout_timer, jiffies + 5*HZ);
  380. jz4740_mmc_set_irq_enabled(host, irq, true);
  381. return true;
  382. }
  383. return false;
  384. }
  385. static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
  386. struct mmc_data *data)
  387. {
  388. int status;
  389. status = readl(host->base + JZ_REG_MMC_STATUS);
  390. if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
  391. if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
  392. host->req->cmd->error = -ETIMEDOUT;
  393. data->error = -ETIMEDOUT;
  394. } else {
  395. host->req->cmd->error = -EIO;
  396. data->error = -EIO;
  397. }
  398. } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
  399. if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
  400. host->req->cmd->error = -ETIMEDOUT;
  401. data->error = -ETIMEDOUT;
  402. } else {
  403. host->req->cmd->error = -EIO;
  404. data->error = -EIO;
  405. }
  406. }
  407. }
  408. static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
  409. struct mmc_data *data)
  410. {
  411. struct sg_mapping_iter *miter = &host->miter;
  412. void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
  413. uint32_t *buf;
  414. bool timeout;
  415. size_t i, j;
  416. while (sg_miter_next(miter)) {
  417. buf = miter->addr;
  418. i = miter->length / 4;
  419. j = i / 8;
  420. i = i & 0x7;
  421. while (j) {
  422. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
  423. if (unlikely(timeout))
  424. goto poll_timeout;
  425. writel(buf[0], fifo_addr);
  426. writel(buf[1], fifo_addr);
  427. writel(buf[2], fifo_addr);
  428. writel(buf[3], fifo_addr);
  429. writel(buf[4], fifo_addr);
  430. writel(buf[5], fifo_addr);
  431. writel(buf[6], fifo_addr);
  432. writel(buf[7], fifo_addr);
  433. buf += 8;
  434. --j;
  435. }
  436. if (unlikely(i)) {
  437. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
  438. if (unlikely(timeout))
  439. goto poll_timeout;
  440. while (i) {
  441. writel(*buf, fifo_addr);
  442. ++buf;
  443. --i;
  444. }
  445. }
  446. data->bytes_xfered += miter->length;
  447. }
  448. sg_miter_stop(miter);
  449. return false;
  450. poll_timeout:
  451. miter->consumed = (void *)buf - miter->addr;
  452. data->bytes_xfered += miter->consumed;
  453. sg_miter_stop(miter);
  454. return true;
  455. }
  456. static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
  457. struct mmc_data *data)
  458. {
  459. struct sg_mapping_iter *miter = &host->miter;
  460. void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
  461. uint32_t *buf;
  462. uint32_t d;
  463. uint32_t status;
  464. size_t i, j;
  465. unsigned int timeout;
  466. while (sg_miter_next(miter)) {
  467. buf = miter->addr;
  468. i = miter->length;
  469. j = i / 32;
  470. i = i & 0x1f;
  471. while (j) {
  472. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
  473. if (unlikely(timeout))
  474. goto poll_timeout;
  475. buf[0] = readl(fifo_addr);
  476. buf[1] = readl(fifo_addr);
  477. buf[2] = readl(fifo_addr);
  478. buf[3] = readl(fifo_addr);
  479. buf[4] = readl(fifo_addr);
  480. buf[5] = readl(fifo_addr);
  481. buf[6] = readl(fifo_addr);
  482. buf[7] = readl(fifo_addr);
  483. buf += 8;
  484. --j;
  485. }
  486. if (unlikely(i)) {
  487. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
  488. if (unlikely(timeout))
  489. goto poll_timeout;
  490. while (i >= 4) {
  491. *buf++ = readl(fifo_addr);
  492. i -= 4;
  493. }
  494. if (unlikely(i > 0)) {
  495. d = readl(fifo_addr);
  496. memcpy(buf, &d, i);
  497. }
  498. }
  499. data->bytes_xfered += miter->length;
  500. /* This can go away once MIPS implements
  501. * flush_kernel_dcache_page */
  502. flush_dcache_page(miter->page);
  503. }
  504. sg_miter_stop(miter);
  505. /* For whatever reason there is sometime one word more in the fifo then
  506. * requested */
  507. timeout = 1000;
  508. status = readl(host->base + JZ_REG_MMC_STATUS);
  509. while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
  510. d = readl(fifo_addr);
  511. status = readl(host->base + JZ_REG_MMC_STATUS);
  512. }
  513. return false;
  514. poll_timeout:
  515. miter->consumed = (void *)buf - miter->addr;
  516. data->bytes_xfered += miter->consumed;
  517. sg_miter_stop(miter);
  518. return true;
  519. }
  520. static void jz4740_mmc_timeout(struct timer_list *t)
  521. {
  522. struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer);
  523. if (!test_and_clear_bit(0, &host->waiting))
  524. return;
  525. jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
  526. host->req->cmd->error = -ETIMEDOUT;
  527. jz4740_mmc_request_done(host);
  528. }
  529. static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
  530. struct mmc_command *cmd)
  531. {
  532. int i;
  533. uint16_t tmp;
  534. void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
  535. if (cmd->flags & MMC_RSP_136) {
  536. tmp = readw(fifo_addr);
  537. for (i = 0; i < 4; ++i) {
  538. cmd->resp[i] = tmp << 24;
  539. tmp = readw(fifo_addr);
  540. cmd->resp[i] |= tmp << 8;
  541. tmp = readw(fifo_addr);
  542. cmd->resp[i] |= tmp >> 8;
  543. }
  544. } else {
  545. cmd->resp[0] = readw(fifo_addr) << 24;
  546. cmd->resp[0] |= readw(fifo_addr) << 8;
  547. cmd->resp[0] |= readw(fifo_addr) & 0xff;
  548. }
  549. }
  550. static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
  551. struct mmc_command *cmd)
  552. {
  553. uint32_t cmdat = host->cmdat;
  554. host->cmdat &= ~JZ_MMC_CMDAT_INIT;
  555. jz4740_mmc_clock_disable(host);
  556. host->cmd = cmd;
  557. if (cmd->flags & MMC_RSP_BUSY)
  558. cmdat |= JZ_MMC_CMDAT_BUSY;
  559. switch (mmc_resp_type(cmd)) {
  560. case MMC_RSP_R1B:
  561. case MMC_RSP_R1:
  562. cmdat |= JZ_MMC_CMDAT_RSP_R1;
  563. break;
  564. case MMC_RSP_R2:
  565. cmdat |= JZ_MMC_CMDAT_RSP_R2;
  566. break;
  567. case MMC_RSP_R3:
  568. cmdat |= JZ_MMC_CMDAT_RSP_R3;
  569. break;
  570. default:
  571. break;
  572. }
  573. if (cmd->data) {
  574. cmdat |= JZ_MMC_CMDAT_DATA_EN;
  575. if (cmd->data->flags & MMC_DATA_WRITE)
  576. cmdat |= JZ_MMC_CMDAT_WRITE;
  577. if (host->use_dma) {
  578. /*
  579. * The 4780's MMC controller has integrated DMA ability
  580. * in addition to being able to use the external DMA
  581. * controller. It moves DMA control bits to a separate
  582. * register. The DMA_SEL bit chooses the external
  583. * controller over the integrated one. Earlier SoCs
  584. * can only use the external controller, and have a
  585. * single DMA enable bit in CMDAT.
  586. */
  587. if (host->version >= JZ_MMC_JZ4780) {
  588. writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL,
  589. host->base + JZ_REG_MMC_DMAC);
  590. } else {
  591. cmdat |= JZ_MMC_CMDAT_DMA_EN;
  592. }
  593. } else if (host->version >= JZ_MMC_JZ4780) {
  594. writel(0, host->base + JZ_REG_MMC_DMAC);
  595. }
  596. writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
  597. writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
  598. }
  599. writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
  600. writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
  601. writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
  602. jz4740_mmc_clock_enable(host, 1);
  603. }
  604. static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
  605. {
  606. struct mmc_command *cmd = host->req->cmd;
  607. struct mmc_data *data = cmd->data;
  608. int direction;
  609. if (data->flags & MMC_DATA_READ)
  610. direction = SG_MITER_TO_SG;
  611. else
  612. direction = SG_MITER_FROM_SG;
  613. sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
  614. }
  615. static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
  616. {
  617. struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
  618. struct mmc_command *cmd = host->req->cmd;
  619. struct mmc_request *req = host->req;
  620. struct mmc_data *data = cmd->data;
  621. bool timeout = false;
  622. if (cmd->error)
  623. host->state = JZ4740_MMC_STATE_DONE;
  624. switch (host->state) {
  625. case JZ4740_MMC_STATE_READ_RESPONSE:
  626. if (cmd->flags & MMC_RSP_PRESENT)
  627. jz4740_mmc_read_response(host, cmd);
  628. if (!data)
  629. break;
  630. jz_mmc_prepare_data_transfer(host);
  631. case JZ4740_MMC_STATE_TRANSFER_DATA:
  632. if (host->use_dma) {
  633. /* Use DMA if enabled.
  634. * Data transfer direction is defined later by
  635. * relying on data flags in
  636. * jz4740_mmc_prepare_dma_data() and
  637. * jz4740_mmc_start_dma_transfer().
  638. */
  639. timeout = jz4740_mmc_start_dma_transfer(host, data);
  640. data->bytes_xfered = data->blocks * data->blksz;
  641. } else if (data->flags & MMC_DATA_READ)
  642. /* Use PIO if DMA is not enabled.
  643. * Data transfer direction was defined before
  644. * by relying on data flags in
  645. * jz_mmc_prepare_data_transfer().
  646. */
  647. timeout = jz4740_mmc_read_data(host, data);
  648. else
  649. timeout = jz4740_mmc_write_data(host, data);
  650. if (unlikely(timeout)) {
  651. host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
  652. break;
  653. }
  654. jz4740_mmc_transfer_check_state(host, data);
  655. timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
  656. if (unlikely(timeout)) {
  657. host->state = JZ4740_MMC_STATE_SEND_STOP;
  658. break;
  659. }
  660. jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
  661. case JZ4740_MMC_STATE_SEND_STOP:
  662. if (!req->stop)
  663. break;
  664. jz4740_mmc_send_command(host, req->stop);
  665. if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) {
  666. timeout = jz4740_mmc_poll_irq(host,
  667. JZ_MMC_IRQ_PRG_DONE);
  668. if (timeout) {
  669. host->state = JZ4740_MMC_STATE_DONE;
  670. break;
  671. }
  672. }
  673. case JZ4740_MMC_STATE_DONE:
  674. break;
  675. }
  676. if (!timeout)
  677. jz4740_mmc_request_done(host);
  678. return IRQ_HANDLED;
  679. }
  680. static irqreturn_t jz_mmc_irq(int irq, void *devid)
  681. {
  682. struct jz4740_mmc_host *host = devid;
  683. struct mmc_command *cmd = host->cmd;
  684. uint32_t irq_reg, status, tmp;
  685. status = readl(host->base + JZ_REG_MMC_STATUS);
  686. irq_reg = jz4740_mmc_read_irq_reg(host);
  687. tmp = irq_reg;
  688. irq_reg &= ~host->irq_mask;
  689. tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
  690. JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
  691. if (tmp != irq_reg)
  692. jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg);
  693. if (irq_reg & JZ_MMC_IRQ_SDIO) {
  694. jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO);
  695. mmc_signal_sdio_irq(host->mmc);
  696. irq_reg &= ~JZ_MMC_IRQ_SDIO;
  697. }
  698. if (host->req && cmd && irq_reg) {
  699. if (test_and_clear_bit(0, &host->waiting)) {
  700. del_timer(&host->timeout_timer);
  701. if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
  702. cmd->error = -ETIMEDOUT;
  703. } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
  704. cmd->error = -EIO;
  705. } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
  706. JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
  707. if (cmd->data)
  708. cmd->data->error = -EIO;
  709. cmd->error = -EIO;
  710. }
  711. jz4740_mmc_set_irq_enabled(host, irq_reg, false);
  712. jz4740_mmc_write_irq_reg(host, irq_reg);
  713. return IRQ_WAKE_THREAD;
  714. }
  715. }
  716. return IRQ_HANDLED;
  717. }
  718. static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
  719. {
  720. int div = 0;
  721. int real_rate;
  722. jz4740_mmc_clock_disable(host);
  723. clk_set_rate(host->clk, host->mmc->f_max);
  724. real_rate = clk_get_rate(host->clk);
  725. while (real_rate > rate && div < 7) {
  726. ++div;
  727. real_rate >>= 1;
  728. }
  729. writew(div, host->base + JZ_REG_MMC_CLKRT);
  730. return real_rate;
  731. }
  732. static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
  733. {
  734. struct jz4740_mmc_host *host = mmc_priv(mmc);
  735. host->req = req;
  736. jz4740_mmc_write_irq_reg(host, ~0);
  737. jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
  738. host->state = JZ4740_MMC_STATE_READ_RESPONSE;
  739. set_bit(0, &host->waiting);
  740. mod_timer(&host->timeout_timer, jiffies + 5*HZ);
  741. jz4740_mmc_send_command(host, req->cmd);
  742. }
  743. static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  744. {
  745. struct jz4740_mmc_host *host = mmc_priv(mmc);
  746. if (ios->clock)
  747. jz4740_mmc_set_clock_rate(host, ios->clock);
  748. switch (ios->power_mode) {
  749. case MMC_POWER_UP:
  750. jz4740_mmc_reset(host);
  751. if (host->pdata && gpio_is_valid(host->pdata->gpio_power))
  752. gpio_set_value(host->pdata->gpio_power,
  753. !host->pdata->power_active_low);
  754. host->cmdat |= JZ_MMC_CMDAT_INIT;
  755. clk_prepare_enable(host->clk);
  756. break;
  757. case MMC_POWER_ON:
  758. break;
  759. default:
  760. if (host->pdata && gpio_is_valid(host->pdata->gpio_power))
  761. gpio_set_value(host->pdata->gpio_power,
  762. host->pdata->power_active_low);
  763. clk_disable_unprepare(host->clk);
  764. break;
  765. }
  766. switch (ios->bus_width) {
  767. case MMC_BUS_WIDTH_1:
  768. host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
  769. break;
  770. case MMC_BUS_WIDTH_4:
  771. host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
  772. break;
  773. default:
  774. break;
  775. }
  776. }
  777. static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  778. {
  779. struct jz4740_mmc_host *host = mmc_priv(mmc);
  780. jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
  781. }
  782. static const struct mmc_host_ops jz4740_mmc_ops = {
  783. .request = jz4740_mmc_request,
  784. .pre_req = jz4740_mmc_pre_request,
  785. .post_req = jz4740_mmc_post_request,
  786. .set_ios = jz4740_mmc_set_ios,
  787. .get_ro = mmc_gpio_get_ro,
  788. .get_cd = mmc_gpio_get_cd,
  789. .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
  790. };
  791. static int jz4740_mmc_request_gpio(struct device *dev, int gpio,
  792. const char *name, bool output, int value)
  793. {
  794. int ret;
  795. if (!gpio_is_valid(gpio))
  796. return 0;
  797. ret = gpio_request(gpio, name);
  798. if (ret) {
  799. dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
  800. return ret;
  801. }
  802. if (output)
  803. gpio_direction_output(gpio, value);
  804. else
  805. gpio_direction_input(gpio);
  806. return 0;
  807. }
  808. static int jz4740_mmc_request_gpios(struct mmc_host *mmc,
  809. struct platform_device *pdev)
  810. {
  811. struct jz4740_mmc_platform_data *pdata = dev_get_platdata(&pdev->dev);
  812. int ret = 0;
  813. if (!pdata)
  814. return 0;
  815. if (!pdata->card_detect_active_low)
  816. mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
  817. if (!pdata->read_only_active_low)
  818. mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
  819. /*
  820. * Get optional card detect and write protect GPIOs,
  821. * only back out on probe deferral.
  822. */
  823. ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
  824. if (ret == -EPROBE_DEFER)
  825. return ret;
  826. ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
  827. if (ret == -EPROBE_DEFER)
  828. return ret;
  829. return jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
  830. "MMC read only", true, pdata->power_active_low);
  831. }
  832. static void jz4740_mmc_free_gpios(struct platform_device *pdev)
  833. {
  834. struct jz4740_mmc_platform_data *pdata = dev_get_platdata(&pdev->dev);
  835. if (!pdata)
  836. return;
  837. if (gpio_is_valid(pdata->gpio_power))
  838. gpio_free(pdata->gpio_power);
  839. }
  840. static const struct of_device_id jz4740_mmc_of_match[] = {
  841. { .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 },
  842. { .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 },
  843. {},
  844. };
  845. MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match);
  846. static int jz4740_mmc_probe(struct platform_device* pdev)
  847. {
  848. int ret;
  849. struct mmc_host *mmc;
  850. struct jz4740_mmc_host *host;
  851. const struct of_device_id *match;
  852. struct jz4740_mmc_platform_data *pdata;
  853. pdata = dev_get_platdata(&pdev->dev);
  854. mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
  855. if (!mmc) {
  856. dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
  857. return -ENOMEM;
  858. }
  859. host = mmc_priv(mmc);
  860. host->pdata = pdata;
  861. match = of_match_device(jz4740_mmc_of_match, &pdev->dev);
  862. if (match) {
  863. host->version = (enum jz4740_mmc_version)match->data;
  864. ret = mmc_of_parse(mmc);
  865. if (ret) {
  866. if (ret != -EPROBE_DEFER)
  867. dev_err(&pdev->dev,
  868. "could not parse of data: %d\n", ret);
  869. goto err_free_host;
  870. }
  871. } else {
  872. /* JZ4740 should be the only one using legacy probe */
  873. host->version = JZ_MMC_JZ4740;
  874. mmc->caps |= MMC_CAP_SDIO_IRQ;
  875. if (!(pdata && pdata->data_1bit))
  876. mmc->caps |= MMC_CAP_4_BIT_DATA;
  877. ret = jz4740_mmc_request_gpios(mmc, pdev);
  878. if (ret)
  879. goto err_free_host;
  880. }
  881. host->irq = platform_get_irq(pdev, 0);
  882. if (host->irq < 0) {
  883. ret = host->irq;
  884. dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
  885. goto err_free_host;
  886. }
  887. host->clk = devm_clk_get(&pdev->dev, "mmc");
  888. if (IS_ERR(host->clk)) {
  889. ret = PTR_ERR(host->clk);
  890. dev_err(&pdev->dev, "Failed to get mmc clock\n");
  891. goto err_free_host;
  892. }
  893. host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  894. host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
  895. if (IS_ERR(host->base)) {
  896. ret = PTR_ERR(host->base);
  897. dev_err(&pdev->dev, "Failed to ioremap base memory\n");
  898. goto err_free_host;
  899. }
  900. mmc->ops = &jz4740_mmc_ops;
  901. if (!mmc->f_max)
  902. mmc->f_max = JZ_MMC_CLK_RATE;
  903. mmc->f_min = mmc->f_max / 128;
  904. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  905. mmc->max_blk_size = (1 << 10) - 1;
  906. mmc->max_blk_count = (1 << 15) - 1;
  907. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  908. mmc->max_segs = 128;
  909. mmc->max_seg_size = mmc->max_req_size;
  910. host->mmc = mmc;
  911. host->pdev = pdev;
  912. spin_lock_init(&host->lock);
  913. host->irq_mask = ~0;
  914. jz4740_mmc_reset(host);
  915. ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
  916. dev_name(&pdev->dev), host);
  917. if (ret) {
  918. dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
  919. goto err_free_gpios;
  920. }
  921. jz4740_mmc_clock_disable(host);
  922. timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0);
  923. ret = jz4740_mmc_acquire_dma_channels(host);
  924. if (ret == -EPROBE_DEFER)
  925. goto err_free_irq;
  926. host->use_dma = !ret;
  927. platform_set_drvdata(pdev, host);
  928. ret = mmc_add_host(mmc);
  929. if (ret) {
  930. dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
  931. goto err_release_dma;
  932. }
  933. dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
  934. dev_info(&pdev->dev, "Using %s, %d-bit mode\n",
  935. host->use_dma ? "DMA" : "PIO",
  936. (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
  937. return 0;
  938. err_release_dma:
  939. if (host->use_dma)
  940. jz4740_mmc_release_dma_channels(host);
  941. err_free_irq:
  942. free_irq(host->irq, host);
  943. err_free_gpios:
  944. jz4740_mmc_free_gpios(pdev);
  945. err_free_host:
  946. mmc_free_host(mmc);
  947. return ret;
  948. }
  949. static int jz4740_mmc_remove(struct platform_device *pdev)
  950. {
  951. struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
  952. del_timer_sync(&host->timeout_timer);
  953. jz4740_mmc_set_irq_enabled(host, 0xff, false);
  954. jz4740_mmc_reset(host);
  955. mmc_remove_host(host->mmc);
  956. free_irq(host->irq, host);
  957. jz4740_mmc_free_gpios(pdev);
  958. if (host->use_dma)
  959. jz4740_mmc_release_dma_channels(host);
  960. mmc_free_host(host->mmc);
  961. return 0;
  962. }
  963. #ifdef CONFIG_PM_SLEEP
  964. static int jz4740_mmc_suspend(struct device *dev)
  965. {
  966. return pinctrl_pm_select_sleep_state(dev);
  967. }
  968. static int jz4740_mmc_resume(struct device *dev)
  969. {
  970. return pinctrl_pm_select_default_state(dev);
  971. }
  972. static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
  973. jz4740_mmc_resume);
  974. #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
  975. #else
  976. #define JZ4740_MMC_PM_OPS NULL
  977. #endif
  978. static struct platform_driver jz4740_mmc_driver = {
  979. .probe = jz4740_mmc_probe,
  980. .remove = jz4740_mmc_remove,
  981. .driver = {
  982. .name = "jz4740-mmc",
  983. .of_match_table = of_match_ptr(jz4740_mmc_of_match),
  984. .pm = JZ4740_MMC_PM_OPS,
  985. },
  986. };
  987. module_platform_driver(jz4740_mmc_driver);
  988. MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
  989. MODULE_LICENSE("GPL");
  990. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");