mmci.h 11 KB

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  1. /*
  2. * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
  3. *
  4. * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #define MMCIPOWER 0x000
  11. #define MCI_PWR_OFF 0x00
  12. #define MCI_PWR_UP 0x02
  13. #define MCI_PWR_ON 0x03
  14. #define MCI_OD (1 << 6)
  15. #define MCI_ROD (1 << 7)
  16. /*
  17. * The ST Micro version does not have ROD and reuse the voltage registers for
  18. * direction settings.
  19. */
  20. #define MCI_ST_DATA2DIREN (1 << 2)
  21. #define MCI_ST_CMDDIREN (1 << 3)
  22. #define MCI_ST_DATA0DIREN (1 << 4)
  23. #define MCI_ST_DATA31DIREN (1 << 5)
  24. #define MCI_ST_FBCLKEN (1 << 7)
  25. #define MCI_ST_DATA74DIREN (1 << 8)
  26. #define MMCICLOCK 0x004
  27. #define MCI_CLK_ENABLE (1 << 8)
  28. #define MCI_CLK_PWRSAVE (1 << 9)
  29. #define MCI_CLK_BYPASS (1 << 10)
  30. #define MCI_4BIT_BUS (1 << 11)
  31. /*
  32. * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
  33. * supported in ST Micro U300 and Ux500 versions
  34. */
  35. #define MCI_ST_8BIT_BUS (1 << 12)
  36. #define MCI_ST_U300_HWFCEN (1 << 13)
  37. #define MCI_ST_UX500_NEG_EDGE (1 << 13)
  38. #define MCI_ST_UX500_HWFCEN (1 << 14)
  39. #define MCI_ST_UX500_CLK_INV (1 << 15)
  40. /* Modified PL180 on Versatile Express platform */
  41. #define MCI_ARM_HWFCEN (1 << 12)
  42. /* Modified on Qualcomm Integrations */
  43. #define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11))
  44. #define MCI_QCOM_CLK_FLOWENA BIT(12)
  45. #define MCI_QCOM_CLK_INVERTOUT BIT(13)
  46. /* select in latch data and command in */
  47. #define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15)
  48. #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
  49. #define MMCIARGUMENT 0x008
  50. /* The command register controls the Command Path State Machine (CPSM) */
  51. #define MMCICOMMAND 0x00c
  52. #define MCI_CPSM_RESPONSE BIT(6)
  53. #define MCI_CPSM_LONGRSP BIT(7)
  54. #define MCI_CPSM_INTERRUPT BIT(8)
  55. #define MCI_CPSM_PENDING BIT(9)
  56. #define MCI_CPSM_ENABLE BIT(10)
  57. /* Command register flag extenstions in the ST Micro versions */
  58. #define MCI_CPSM_ST_SDIO_SUSP BIT(11)
  59. #define MCI_CPSM_ST_ENCMD_COMPL BIT(12)
  60. #define MCI_CPSM_ST_NIEN BIT(13)
  61. #define MCI_CPSM_ST_CE_ATACMD BIT(14)
  62. /* Command register flag extensions in the Qualcomm versions */
  63. #define MCI_CPSM_QCOM_PROGENA BIT(11)
  64. #define MCI_CPSM_QCOM_DATCMD BIT(12)
  65. #define MCI_CPSM_QCOM_MCIABORT BIT(13)
  66. #define MCI_CPSM_QCOM_CCSENABLE BIT(14)
  67. #define MCI_CPSM_QCOM_CCSDISABLE BIT(15)
  68. #define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16)
  69. #define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21)
  70. #define MMCIRESPCMD 0x010
  71. #define MMCIRESPONSE0 0x014
  72. #define MMCIRESPONSE1 0x018
  73. #define MMCIRESPONSE2 0x01c
  74. #define MMCIRESPONSE3 0x020
  75. #define MMCIDATATIMER 0x024
  76. #define MMCIDATALENGTH 0x028
  77. /* The data control register controls the Data Path State Machine (DPSM) */
  78. #define MMCIDATACTRL 0x02c
  79. #define MCI_DPSM_ENABLE BIT(0)
  80. #define MCI_DPSM_DIRECTION BIT(1)
  81. #define MCI_DPSM_MODE BIT(2)
  82. #define MCI_DPSM_DMAENABLE BIT(3)
  83. #define MCI_DPSM_BLOCKSIZE BIT(4)
  84. /* Control register extensions in the ST Micro U300 and Ux500 versions */
  85. #define MCI_DPSM_ST_RWSTART BIT(8)
  86. #define MCI_DPSM_ST_RWSTOP BIT(9)
  87. #define MCI_DPSM_ST_RWMOD BIT(10)
  88. #define MCI_DPSM_ST_SDIOEN BIT(11)
  89. /* Control register extensions in the ST Micro Ux500 versions */
  90. #define MCI_DPSM_ST_DMAREQCTL BIT(12)
  91. #define MCI_DPSM_ST_DBOOTMODEEN BIT(13)
  92. #define MCI_DPSM_ST_BUSYMODE BIT(14)
  93. #define MCI_DPSM_ST_DDRMODE BIT(15)
  94. /* Control register extensions in the Qualcomm versions */
  95. #define MCI_DPSM_QCOM_DATA_PEND BIT(17)
  96. #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
  97. #define MMCIDATACNT 0x030
  98. #define MMCISTATUS 0x034
  99. #define MCI_CMDCRCFAIL (1 << 0)
  100. #define MCI_DATACRCFAIL (1 << 1)
  101. #define MCI_CMDTIMEOUT (1 << 2)
  102. #define MCI_DATATIMEOUT (1 << 3)
  103. #define MCI_TXUNDERRUN (1 << 4)
  104. #define MCI_RXOVERRUN (1 << 5)
  105. #define MCI_CMDRESPEND (1 << 6)
  106. #define MCI_CMDSENT (1 << 7)
  107. #define MCI_DATAEND (1 << 8)
  108. #define MCI_STARTBITERR (1 << 9)
  109. #define MCI_DATABLOCKEND (1 << 10)
  110. #define MCI_CMDACTIVE (1 << 11)
  111. #define MCI_TXACTIVE (1 << 12)
  112. #define MCI_RXACTIVE (1 << 13)
  113. #define MCI_TXFIFOHALFEMPTY (1 << 14)
  114. #define MCI_RXFIFOHALFFULL (1 << 15)
  115. #define MCI_TXFIFOFULL (1 << 16)
  116. #define MCI_RXFIFOFULL (1 << 17)
  117. #define MCI_TXFIFOEMPTY (1 << 18)
  118. #define MCI_RXFIFOEMPTY (1 << 19)
  119. #define MCI_TXDATAAVLBL (1 << 20)
  120. #define MCI_RXDATAAVLBL (1 << 21)
  121. /* Extended status bits for the ST Micro variants */
  122. #define MCI_ST_SDIOIT (1 << 22)
  123. #define MCI_ST_CEATAEND (1 << 23)
  124. #define MCI_ST_CARDBUSY (1 << 24)
  125. #define MMCICLEAR 0x038
  126. #define MCI_CMDCRCFAILCLR (1 << 0)
  127. #define MCI_DATACRCFAILCLR (1 << 1)
  128. #define MCI_CMDTIMEOUTCLR (1 << 2)
  129. #define MCI_DATATIMEOUTCLR (1 << 3)
  130. #define MCI_TXUNDERRUNCLR (1 << 4)
  131. #define MCI_RXOVERRUNCLR (1 << 5)
  132. #define MCI_CMDRESPENDCLR (1 << 6)
  133. #define MCI_CMDSENTCLR (1 << 7)
  134. #define MCI_DATAENDCLR (1 << 8)
  135. #define MCI_STARTBITERRCLR (1 << 9)
  136. #define MCI_DATABLOCKENDCLR (1 << 10)
  137. /* Extended status bits for the ST Micro variants */
  138. #define MCI_ST_SDIOITC (1 << 22)
  139. #define MCI_ST_CEATAENDC (1 << 23)
  140. #define MCI_ST_BUSYENDC (1 << 24)
  141. #define MMCIMASK0 0x03c
  142. #define MCI_CMDCRCFAILMASK (1 << 0)
  143. #define MCI_DATACRCFAILMASK (1 << 1)
  144. #define MCI_CMDTIMEOUTMASK (1 << 2)
  145. #define MCI_DATATIMEOUTMASK (1 << 3)
  146. #define MCI_TXUNDERRUNMASK (1 << 4)
  147. #define MCI_RXOVERRUNMASK (1 << 5)
  148. #define MCI_CMDRESPENDMASK (1 << 6)
  149. #define MCI_CMDSENTMASK (1 << 7)
  150. #define MCI_DATAENDMASK (1 << 8)
  151. #define MCI_STARTBITERRMASK (1 << 9)
  152. #define MCI_DATABLOCKENDMASK (1 << 10)
  153. #define MCI_CMDACTIVEMASK (1 << 11)
  154. #define MCI_TXACTIVEMASK (1 << 12)
  155. #define MCI_RXACTIVEMASK (1 << 13)
  156. #define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
  157. #define MCI_RXFIFOHALFFULLMASK (1 << 15)
  158. #define MCI_TXFIFOFULLMASK (1 << 16)
  159. #define MCI_RXFIFOFULLMASK (1 << 17)
  160. #define MCI_TXFIFOEMPTYMASK (1 << 18)
  161. #define MCI_RXFIFOEMPTYMASK (1 << 19)
  162. #define MCI_TXDATAAVLBLMASK (1 << 20)
  163. #define MCI_RXDATAAVLBLMASK (1 << 21)
  164. /* Extended status bits for the ST Micro variants */
  165. #define MCI_ST_SDIOITMASK (1 << 22)
  166. #define MCI_ST_CEATAENDMASK (1 << 23)
  167. #define MCI_ST_BUSYENDMASK (1 << 24)
  168. #define MMCIMASK1 0x040
  169. #define MMCIFIFOCNT 0x048
  170. #define MMCIFIFO 0x080 /* to 0x0bc */
  171. #define MCI_IRQENABLE \
  172. (MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
  173. MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \
  174. MCI_CMDRESPENDMASK | MCI_CMDSENTMASK)
  175. /* These interrupts are directed to IRQ1 when two IRQ lines are available */
  176. #define MCI_IRQ1MASK \
  177. (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
  178. MCI_TXFIFOHALFEMPTYMASK)
  179. #define NR_SG 128
  180. #define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
  181. struct clk;
  182. struct dma_chan;
  183. struct mmci_host;
  184. /**
  185. * struct variant_data - MMCI variant-specific quirks
  186. * @clkreg: default value for MCICLOCK register
  187. * @clkreg_enable: enable value for MMCICLOCK register
  188. * @clkreg_8bit_bus_enable: enable value for 8 bit bus
  189. * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
  190. * @datalength_bits: number of bits in the MMCIDATALENGTH register
  191. * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
  192. * is asserted (likewise for RX)
  193. * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
  194. * is asserted (likewise for RX)
  195. * @data_cmd_enable: enable value for data commands.
  196. * @st_sdio: enable ST specific SDIO logic
  197. * @st_clkdiv: true if using a ST-specific clock divider algorithm
  198. * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
  199. * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
  200. * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
  201. * register
  202. * @datactrl_mask_sdio: SDIO enable mask in datactrl register
  203. * @pwrreg_powerup: power up value for MMCIPOWER register
  204. * @f_max: maximum clk frequency supported by the controller.
  205. * @signal_direction: input/out direction of bus signals can be indicated
  206. * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
  207. * @busy_detect: true if the variant supports busy detection on DAT0.
  208. * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
  209. * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
  210. * indicating that the card is busy
  211. * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
  212. * getting busy end detection interrupts
  213. * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
  214. * @explicit_mclk_control: enable explicit mclk control in driver.
  215. * @qcom_fifo: enables qcom specific fifo pio read logic.
  216. * @qcom_dml: enables qcom specific dma glue for dma transfers.
  217. * @reversed_irq_handling: handle data irq before cmd irq.
  218. * @mmcimask1: true if variant have a MMCIMASK1 register.
  219. * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
  220. * register.
  221. * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
  222. */
  223. struct variant_data {
  224. unsigned int clkreg;
  225. unsigned int clkreg_enable;
  226. unsigned int clkreg_8bit_bus_enable;
  227. unsigned int clkreg_neg_edge_enable;
  228. unsigned int datalength_bits;
  229. unsigned int fifosize;
  230. unsigned int fifohalfsize;
  231. unsigned int data_cmd_enable;
  232. unsigned int datactrl_mask_ddrmode;
  233. unsigned int datactrl_mask_sdio;
  234. bool st_sdio;
  235. bool st_clkdiv;
  236. bool blksz_datactrl16;
  237. bool blksz_datactrl4;
  238. u32 pwrreg_powerup;
  239. u32 f_max;
  240. bool signal_direction;
  241. bool pwrreg_clkgate;
  242. bool busy_detect;
  243. u32 busy_dpsm_flag;
  244. u32 busy_detect_flag;
  245. u32 busy_detect_mask;
  246. bool pwrreg_nopower;
  247. bool explicit_mclk_control;
  248. bool qcom_fifo;
  249. bool qcom_dml;
  250. bool reversed_irq_handling;
  251. bool mmcimask1;
  252. u32 start_err;
  253. u32 opendrain;
  254. void (*init)(struct mmci_host *host);
  255. };
  256. /* mmci variant callbacks */
  257. struct mmci_host_ops {
  258. void (*dma_setup)(struct mmci_host *host);
  259. };
  260. struct mmci_host_next {
  261. struct dma_async_tx_descriptor *dma_desc;
  262. struct dma_chan *dma_chan;
  263. s32 cookie;
  264. };
  265. struct mmci_host {
  266. phys_addr_t phybase;
  267. void __iomem *base;
  268. struct mmc_request *mrq;
  269. struct mmc_command *cmd;
  270. struct mmc_data *data;
  271. struct mmc_host *mmc;
  272. struct clk *clk;
  273. bool singleirq;
  274. spinlock_t lock;
  275. unsigned int mclk;
  276. /* cached value of requested clk in set_ios */
  277. unsigned int clock_cache;
  278. unsigned int cclk;
  279. u32 pwr_reg;
  280. u32 pwr_reg_add;
  281. u32 clk_reg;
  282. u32 datactrl_reg;
  283. u32 busy_status;
  284. u32 mask1_reg;
  285. bool vqmmc_enabled;
  286. struct mmci_platform_data *plat;
  287. struct mmci_host_ops *ops;
  288. struct variant_data *variant;
  289. struct pinctrl *pinctrl;
  290. struct pinctrl_state *pins_default;
  291. struct pinctrl_state *pins_opendrain;
  292. u8 hw_designer;
  293. u8 hw_revision:4;
  294. struct timer_list timer;
  295. unsigned int oldstat;
  296. /* pio stuff */
  297. struct sg_mapping_iter sg_miter;
  298. unsigned int size;
  299. int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);
  300. #ifdef CONFIG_DMA_ENGINE
  301. /* DMA stuff */
  302. struct dma_chan *dma_current;
  303. struct dma_chan *dma_rx_channel;
  304. struct dma_chan *dma_tx_channel;
  305. struct dma_async_tx_descriptor *dma_desc_current;
  306. struct mmci_host_next next_data;
  307. bool dma_in_progress;
  308. #define dma_inprogress(host) ((host)->dma_in_progress)
  309. #else
  310. #define dma_inprogress(host) (0)
  311. #endif
  312. };