moxart-mmc.c 17 KB

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  1. /*
  2. * MOXA ART MMC host driver.
  3. *
  4. * Copyright (C) 2014 Jonas Jensen
  5. *
  6. * Jonas Jensen <jonas.jensen@gmail.com>
  7. *
  8. * Based on code from
  9. * Moxa Technologies Co., Ltd. <www.moxa.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/blkdev.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/mmc/host.h>
  25. #include <linux/mmc/sd.h>
  26. #include <linux/sched.h>
  27. #include <linux/io.h>
  28. #include <linux/of_address.h>
  29. #include <linux/of_irq.h>
  30. #include <linux/clk.h>
  31. #include <linux/bitops.h>
  32. #include <linux/of_dma.h>
  33. #include <linux/spinlock.h>
  34. #define REG_COMMAND 0
  35. #define REG_ARGUMENT 4
  36. #define REG_RESPONSE0 8
  37. #define REG_RESPONSE1 12
  38. #define REG_RESPONSE2 16
  39. #define REG_RESPONSE3 20
  40. #define REG_RESPONSE_COMMAND 24
  41. #define REG_DATA_CONTROL 28
  42. #define REG_DATA_TIMER 32
  43. #define REG_DATA_LENGTH 36
  44. #define REG_STATUS 40
  45. #define REG_CLEAR 44
  46. #define REG_INTERRUPT_MASK 48
  47. #define REG_POWER_CONTROL 52
  48. #define REG_CLOCK_CONTROL 56
  49. #define REG_BUS_WIDTH 60
  50. #define REG_DATA_WINDOW 64
  51. #define REG_FEATURE 68
  52. #define REG_REVISION 72
  53. /* REG_COMMAND */
  54. #define CMD_SDC_RESET BIT(10)
  55. #define CMD_EN BIT(9)
  56. #define CMD_APP_CMD BIT(8)
  57. #define CMD_LONG_RSP BIT(7)
  58. #define CMD_NEED_RSP BIT(6)
  59. #define CMD_IDX_MASK 0x3f
  60. /* REG_RESPONSE_COMMAND */
  61. #define RSP_CMD_APP BIT(6)
  62. #define RSP_CMD_IDX_MASK 0x3f
  63. /* REG_DATA_CONTROL */
  64. #define DCR_DATA_FIFO_RESET BIT(8)
  65. #define DCR_DATA_THRES BIT(7)
  66. #define DCR_DATA_EN BIT(6)
  67. #define DCR_DMA_EN BIT(5)
  68. #define DCR_DATA_WRITE BIT(4)
  69. #define DCR_BLK_SIZE 0x0f
  70. /* REG_DATA_LENGTH */
  71. #define DATA_LEN_MASK 0xffffff
  72. /* REG_STATUS */
  73. #define WRITE_PROT BIT(12)
  74. #define CARD_DETECT BIT(11)
  75. /* 1-10 below can be sent to either registers, interrupt or clear. */
  76. #define CARD_CHANGE BIT(10)
  77. #define FIFO_ORUN BIT(9)
  78. #define FIFO_URUN BIT(8)
  79. #define DATA_END BIT(7)
  80. #define CMD_SENT BIT(6)
  81. #define DATA_CRC_OK BIT(5)
  82. #define RSP_CRC_OK BIT(4)
  83. #define DATA_TIMEOUT BIT(3)
  84. #define RSP_TIMEOUT BIT(2)
  85. #define DATA_CRC_FAIL BIT(1)
  86. #define RSP_CRC_FAIL BIT(0)
  87. #define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \
  88. RSP_CRC_OK | CARD_DETECT | CMD_SENT)
  89. #define MASK_DATA (DATA_CRC_OK | DATA_END | \
  90. DATA_CRC_FAIL | DATA_TIMEOUT)
  91. #define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE)
  92. /* REG_POWER_CONTROL */
  93. #define SD_POWER_ON BIT(4)
  94. #define SD_POWER_MASK 0x0f
  95. /* REG_CLOCK_CONTROL */
  96. #define CLK_HISPD BIT(9)
  97. #define CLK_OFF BIT(8)
  98. #define CLK_SD BIT(7)
  99. #define CLK_DIV_MASK 0x7f
  100. /* REG_BUS_WIDTH */
  101. #define BUS_WIDTH_8 BIT(2)
  102. #define BUS_WIDTH_4 BIT(1)
  103. #define BUS_WIDTH_1 BIT(0)
  104. #define MMC_VDD_360 23
  105. #define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK)
  106. #define MAX_RETRIES 500000
  107. struct moxart_host {
  108. spinlock_t lock;
  109. void __iomem *base;
  110. phys_addr_t reg_phys;
  111. struct dma_chan *dma_chan_tx;
  112. struct dma_chan *dma_chan_rx;
  113. struct dma_async_tx_descriptor *tx_desc;
  114. struct mmc_host *mmc;
  115. struct mmc_request *mrq;
  116. struct scatterlist *cur_sg;
  117. struct completion dma_complete;
  118. struct completion pio_complete;
  119. u32 num_sg;
  120. u32 data_remain;
  121. u32 data_len;
  122. u32 fifo_width;
  123. u32 timeout;
  124. u32 rate;
  125. long sysclk;
  126. bool have_dma;
  127. bool is_removed;
  128. };
  129. static inline void moxart_init_sg(struct moxart_host *host,
  130. struct mmc_data *data)
  131. {
  132. host->cur_sg = data->sg;
  133. host->num_sg = data->sg_len;
  134. host->data_remain = host->cur_sg->length;
  135. if (host->data_remain > host->data_len)
  136. host->data_remain = host->data_len;
  137. }
  138. static inline int moxart_next_sg(struct moxart_host *host)
  139. {
  140. int remain;
  141. struct mmc_data *data = host->mrq->cmd->data;
  142. host->cur_sg++;
  143. host->num_sg--;
  144. if (host->num_sg > 0) {
  145. host->data_remain = host->cur_sg->length;
  146. remain = host->data_len - data->bytes_xfered;
  147. if (remain > 0 && remain < host->data_remain)
  148. host->data_remain = remain;
  149. }
  150. return host->num_sg;
  151. }
  152. static int moxart_wait_for_status(struct moxart_host *host,
  153. u32 mask, u32 *status)
  154. {
  155. int ret = -ETIMEDOUT;
  156. u32 i;
  157. for (i = 0; i < MAX_RETRIES; i++) {
  158. *status = readl(host->base + REG_STATUS);
  159. if (!(*status & mask)) {
  160. udelay(5);
  161. continue;
  162. }
  163. writel(*status & mask, host->base + REG_CLEAR);
  164. ret = 0;
  165. break;
  166. }
  167. if (ret)
  168. dev_err(mmc_dev(host->mmc), "timed out waiting for status\n");
  169. return ret;
  170. }
  171. static void moxart_send_command(struct moxart_host *host,
  172. struct mmc_command *cmd)
  173. {
  174. u32 status, cmdctrl;
  175. writel(RSP_TIMEOUT | RSP_CRC_OK |
  176. RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR);
  177. writel(cmd->arg, host->base + REG_ARGUMENT);
  178. cmdctrl = cmd->opcode & CMD_IDX_MASK;
  179. if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND ||
  180. cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS ||
  181. cmdctrl == SD_APP_SEND_NUM_WR_BLKS)
  182. cmdctrl |= CMD_APP_CMD;
  183. if (cmd->flags & MMC_RSP_PRESENT)
  184. cmdctrl |= CMD_NEED_RSP;
  185. if (cmd->flags & MMC_RSP_136)
  186. cmdctrl |= CMD_LONG_RSP;
  187. writel(cmdctrl | CMD_EN, host->base + REG_COMMAND);
  188. if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT)
  189. cmd->error = -ETIMEDOUT;
  190. if (status & RSP_TIMEOUT) {
  191. cmd->error = -ETIMEDOUT;
  192. return;
  193. }
  194. if (status & RSP_CRC_FAIL) {
  195. cmd->error = -EIO;
  196. return;
  197. }
  198. if (status & RSP_CRC_OK) {
  199. if (cmd->flags & MMC_RSP_136) {
  200. cmd->resp[3] = readl(host->base + REG_RESPONSE0);
  201. cmd->resp[2] = readl(host->base + REG_RESPONSE1);
  202. cmd->resp[1] = readl(host->base + REG_RESPONSE2);
  203. cmd->resp[0] = readl(host->base + REG_RESPONSE3);
  204. } else {
  205. cmd->resp[0] = readl(host->base + REG_RESPONSE0);
  206. }
  207. }
  208. }
  209. static void moxart_dma_complete(void *param)
  210. {
  211. struct moxart_host *host = param;
  212. complete(&host->dma_complete);
  213. }
  214. static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host)
  215. {
  216. u32 len, dir_slave;
  217. long dma_time;
  218. struct dma_async_tx_descriptor *desc = NULL;
  219. struct dma_chan *dma_chan;
  220. if (host->data_len == data->bytes_xfered)
  221. return;
  222. if (data->flags & MMC_DATA_WRITE) {
  223. dma_chan = host->dma_chan_tx;
  224. dir_slave = DMA_MEM_TO_DEV;
  225. } else {
  226. dma_chan = host->dma_chan_rx;
  227. dir_slave = DMA_DEV_TO_MEM;
  228. }
  229. len = dma_map_sg(dma_chan->device->dev, data->sg,
  230. data->sg_len, mmc_get_dma_dir(data));
  231. if (len > 0) {
  232. desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
  233. len, dir_slave,
  234. DMA_PREP_INTERRUPT |
  235. DMA_CTRL_ACK);
  236. } else {
  237. dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
  238. }
  239. if (desc) {
  240. host->tx_desc = desc;
  241. desc->callback = moxart_dma_complete;
  242. desc->callback_param = host;
  243. dmaengine_submit(desc);
  244. dma_async_issue_pending(dma_chan);
  245. }
  246. data->bytes_xfered += host->data_remain;
  247. dma_time = wait_for_completion_interruptible_timeout(
  248. &host->dma_complete, host->timeout);
  249. dma_unmap_sg(dma_chan->device->dev,
  250. data->sg, data->sg_len,
  251. mmc_get_dma_dir(data));
  252. }
  253. static void moxart_transfer_pio(struct moxart_host *host)
  254. {
  255. struct mmc_data *data = host->mrq->cmd->data;
  256. u32 *sgp, len = 0, remain, status;
  257. if (host->data_len == data->bytes_xfered)
  258. return;
  259. sgp = sg_virt(host->cur_sg);
  260. remain = host->data_remain;
  261. if (data->flags & MMC_DATA_WRITE) {
  262. while (remain > 0) {
  263. if (moxart_wait_for_status(host, FIFO_URUN, &status)
  264. == -ETIMEDOUT) {
  265. data->error = -ETIMEDOUT;
  266. complete(&host->pio_complete);
  267. return;
  268. }
  269. for (len = 0; len < remain && len < host->fifo_width;) {
  270. iowrite32(*sgp, host->base + REG_DATA_WINDOW);
  271. sgp++;
  272. len += 4;
  273. }
  274. remain -= len;
  275. }
  276. } else {
  277. while (remain > 0) {
  278. if (moxart_wait_for_status(host, FIFO_ORUN, &status)
  279. == -ETIMEDOUT) {
  280. data->error = -ETIMEDOUT;
  281. complete(&host->pio_complete);
  282. return;
  283. }
  284. for (len = 0; len < remain && len < host->fifo_width;) {
  285. /* SCR data must be read in big endian. */
  286. if (data->mrq->cmd->opcode == SD_APP_SEND_SCR)
  287. *sgp = ioread32be(host->base +
  288. REG_DATA_WINDOW);
  289. else
  290. *sgp = ioread32(host->base +
  291. REG_DATA_WINDOW);
  292. sgp++;
  293. len += 4;
  294. }
  295. remain -= len;
  296. }
  297. }
  298. data->bytes_xfered += host->data_remain - remain;
  299. host->data_remain = remain;
  300. if (host->data_len != data->bytes_xfered)
  301. moxart_next_sg(host);
  302. else
  303. complete(&host->pio_complete);
  304. }
  305. static void moxart_prepare_data(struct moxart_host *host)
  306. {
  307. struct mmc_data *data = host->mrq->cmd->data;
  308. u32 datactrl;
  309. int blksz_bits;
  310. if (!data)
  311. return;
  312. host->data_len = data->blocks * data->blksz;
  313. blksz_bits = ffs(data->blksz) - 1;
  314. BUG_ON(1 << blksz_bits != data->blksz);
  315. moxart_init_sg(host, data);
  316. datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE);
  317. if (data->flags & MMC_DATA_WRITE)
  318. datactrl |= DCR_DATA_WRITE;
  319. if ((host->data_len > host->fifo_width) && host->have_dma)
  320. datactrl |= DCR_DMA_EN;
  321. writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL);
  322. writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR);
  323. writel(host->rate, host->base + REG_DATA_TIMER);
  324. writel(host->data_len, host->base + REG_DATA_LENGTH);
  325. writel(datactrl, host->base + REG_DATA_CONTROL);
  326. }
  327. static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq)
  328. {
  329. struct moxart_host *host = mmc_priv(mmc);
  330. long pio_time;
  331. unsigned long flags;
  332. u32 status;
  333. spin_lock_irqsave(&host->lock, flags);
  334. init_completion(&host->dma_complete);
  335. init_completion(&host->pio_complete);
  336. host->mrq = mrq;
  337. if (readl(host->base + REG_STATUS) & CARD_DETECT) {
  338. mrq->cmd->error = -ETIMEDOUT;
  339. goto request_done;
  340. }
  341. moxart_prepare_data(host);
  342. moxart_send_command(host, host->mrq->cmd);
  343. if (mrq->cmd->data) {
  344. if ((host->data_len > host->fifo_width) && host->have_dma) {
  345. writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
  346. spin_unlock_irqrestore(&host->lock, flags);
  347. moxart_transfer_dma(mrq->cmd->data, host);
  348. spin_lock_irqsave(&host->lock, flags);
  349. } else {
  350. writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK);
  351. spin_unlock_irqrestore(&host->lock, flags);
  352. /* PIO transfers start from interrupt. */
  353. pio_time = wait_for_completion_interruptible_timeout(
  354. &host->pio_complete, host->timeout);
  355. spin_lock_irqsave(&host->lock, flags);
  356. }
  357. if (host->is_removed) {
  358. dev_err(mmc_dev(host->mmc), "card removed\n");
  359. mrq->cmd->error = -ETIMEDOUT;
  360. goto request_done;
  361. }
  362. if (moxart_wait_for_status(host, MASK_DATA, &status)
  363. == -ETIMEDOUT) {
  364. mrq->cmd->data->error = -ETIMEDOUT;
  365. goto request_done;
  366. }
  367. if (status & DATA_CRC_FAIL)
  368. mrq->cmd->data->error = -ETIMEDOUT;
  369. if (mrq->cmd->data->stop)
  370. moxart_send_command(host, mrq->cmd->data->stop);
  371. }
  372. request_done:
  373. spin_unlock_irqrestore(&host->lock, flags);
  374. mmc_request_done(host->mmc, mrq);
  375. }
  376. static irqreturn_t moxart_irq(int irq, void *devid)
  377. {
  378. struct moxart_host *host = (struct moxart_host *)devid;
  379. u32 status;
  380. unsigned long flags;
  381. spin_lock_irqsave(&host->lock, flags);
  382. status = readl(host->base + REG_STATUS);
  383. if (status & CARD_CHANGE) {
  384. host->is_removed = status & CARD_DETECT;
  385. if (host->is_removed && host->have_dma) {
  386. dmaengine_terminate_all(host->dma_chan_tx);
  387. dmaengine_terminate_all(host->dma_chan_rx);
  388. }
  389. host->mrq = NULL;
  390. writel(MASK_INTR_PIO, host->base + REG_CLEAR);
  391. writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
  392. mmc_detect_change(host->mmc, 0);
  393. }
  394. if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq)
  395. moxart_transfer_pio(host);
  396. spin_unlock_irqrestore(&host->lock, flags);
  397. return IRQ_HANDLED;
  398. }
  399. static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  400. {
  401. struct moxart_host *host = mmc_priv(mmc);
  402. unsigned long flags;
  403. u8 power, div;
  404. u32 ctrl;
  405. spin_lock_irqsave(&host->lock, flags);
  406. if (ios->clock) {
  407. for (div = 0; div < CLK_DIV_MASK; ++div) {
  408. if (ios->clock >= host->sysclk / (2 * (div + 1)))
  409. break;
  410. }
  411. ctrl = CLK_SD | div;
  412. host->rate = host->sysclk / (2 * (div + 1));
  413. if (host->rate > host->sysclk)
  414. ctrl |= CLK_HISPD;
  415. writel(ctrl, host->base + REG_CLOCK_CONTROL);
  416. }
  417. if (ios->power_mode == MMC_POWER_OFF) {
  418. writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON,
  419. host->base + REG_POWER_CONTROL);
  420. } else {
  421. if (ios->vdd < MIN_POWER)
  422. power = 0;
  423. else
  424. power = ios->vdd - MIN_POWER;
  425. writel(SD_POWER_ON | (u32) power,
  426. host->base + REG_POWER_CONTROL);
  427. }
  428. switch (ios->bus_width) {
  429. case MMC_BUS_WIDTH_4:
  430. writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);
  431. break;
  432. case MMC_BUS_WIDTH_8:
  433. writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH);
  434. break;
  435. default:
  436. writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);
  437. break;
  438. }
  439. spin_unlock_irqrestore(&host->lock, flags);
  440. }
  441. static int moxart_get_ro(struct mmc_host *mmc)
  442. {
  443. struct moxart_host *host = mmc_priv(mmc);
  444. return !!(readl(host->base + REG_STATUS) & WRITE_PROT);
  445. }
  446. static const struct mmc_host_ops moxart_ops = {
  447. .request = moxart_request,
  448. .set_ios = moxart_set_ios,
  449. .get_ro = moxart_get_ro,
  450. };
  451. static int moxart_probe(struct platform_device *pdev)
  452. {
  453. struct device *dev = &pdev->dev;
  454. struct device_node *node = dev->of_node;
  455. struct resource res_mmc;
  456. struct mmc_host *mmc;
  457. struct moxart_host *host = NULL;
  458. struct dma_slave_config cfg;
  459. struct clk *clk;
  460. void __iomem *reg_mmc;
  461. int irq, ret;
  462. u32 i;
  463. mmc = mmc_alloc_host(sizeof(struct moxart_host), dev);
  464. if (!mmc) {
  465. dev_err(dev, "mmc_alloc_host failed\n");
  466. ret = -ENOMEM;
  467. goto out;
  468. }
  469. ret = of_address_to_resource(node, 0, &res_mmc);
  470. if (ret) {
  471. dev_err(dev, "of_address_to_resource failed\n");
  472. goto out;
  473. }
  474. irq = irq_of_parse_and_map(node, 0);
  475. if (irq <= 0) {
  476. dev_err(dev, "irq_of_parse_and_map failed\n");
  477. ret = -EINVAL;
  478. goto out;
  479. }
  480. clk = devm_clk_get(dev, NULL);
  481. if (IS_ERR(clk)) {
  482. ret = PTR_ERR(clk);
  483. goto out;
  484. }
  485. reg_mmc = devm_ioremap_resource(dev, &res_mmc);
  486. if (IS_ERR(reg_mmc)) {
  487. ret = PTR_ERR(reg_mmc);
  488. goto out;
  489. }
  490. ret = mmc_of_parse(mmc);
  491. if (ret)
  492. goto out;
  493. host = mmc_priv(mmc);
  494. host->mmc = mmc;
  495. host->base = reg_mmc;
  496. host->reg_phys = res_mmc.start;
  497. host->timeout = msecs_to_jiffies(1000);
  498. host->sysclk = clk_get_rate(clk);
  499. host->fifo_width = readl(host->base + REG_FEATURE) << 2;
  500. host->dma_chan_tx = dma_request_slave_channel_reason(dev, "tx");
  501. host->dma_chan_rx = dma_request_slave_channel_reason(dev, "rx");
  502. spin_lock_init(&host->lock);
  503. mmc->ops = &moxart_ops;
  504. mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2);
  505. mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2);
  506. mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */
  507. if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) {
  508. if (PTR_ERR(host->dma_chan_tx) == -EPROBE_DEFER ||
  509. PTR_ERR(host->dma_chan_rx) == -EPROBE_DEFER) {
  510. ret = -EPROBE_DEFER;
  511. goto out;
  512. }
  513. dev_dbg(dev, "PIO mode transfer enabled\n");
  514. host->have_dma = false;
  515. } else {
  516. dev_dbg(dev, "DMA channels found (%p,%p)\n",
  517. host->dma_chan_tx, host->dma_chan_rx);
  518. host->have_dma = true;
  519. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  520. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  521. cfg.direction = DMA_MEM_TO_DEV;
  522. cfg.src_addr = 0;
  523. cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW;
  524. dmaengine_slave_config(host->dma_chan_tx, &cfg);
  525. cfg.direction = DMA_DEV_TO_MEM;
  526. cfg.src_addr = host->reg_phys + REG_DATA_WINDOW;
  527. cfg.dst_addr = 0;
  528. dmaengine_slave_config(host->dma_chan_rx, &cfg);
  529. }
  530. switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) {
  531. case 1:
  532. mmc->caps |= MMC_CAP_4_BIT_DATA;
  533. break;
  534. case 2:
  535. mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
  536. break;
  537. default:
  538. break;
  539. }
  540. writel(0, host->base + REG_INTERRUPT_MASK);
  541. writel(CMD_SDC_RESET, host->base + REG_COMMAND);
  542. for (i = 0; i < MAX_RETRIES; i++) {
  543. if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET))
  544. break;
  545. udelay(5);
  546. }
  547. ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host);
  548. if (ret)
  549. goto out;
  550. dev_set_drvdata(dev, mmc);
  551. mmc_add_host(mmc);
  552. dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width);
  553. return 0;
  554. out:
  555. if (mmc)
  556. mmc_free_host(mmc);
  557. return ret;
  558. }
  559. static int moxart_remove(struct platform_device *pdev)
  560. {
  561. struct mmc_host *mmc = dev_get_drvdata(&pdev->dev);
  562. struct moxart_host *host = mmc_priv(mmc);
  563. dev_set_drvdata(&pdev->dev, NULL);
  564. if (mmc) {
  565. if (!IS_ERR(host->dma_chan_tx))
  566. dma_release_channel(host->dma_chan_tx);
  567. if (!IS_ERR(host->dma_chan_rx))
  568. dma_release_channel(host->dma_chan_rx);
  569. mmc_remove_host(mmc);
  570. mmc_free_host(mmc);
  571. writel(0, host->base + REG_INTERRUPT_MASK);
  572. writel(0, host->base + REG_POWER_CONTROL);
  573. writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF,
  574. host->base + REG_CLOCK_CONTROL);
  575. }
  576. return 0;
  577. }
  578. static const struct of_device_id moxart_mmc_match[] = {
  579. { .compatible = "moxa,moxart-mmc" },
  580. { .compatible = "faraday,ftsdc010" },
  581. { }
  582. };
  583. MODULE_DEVICE_TABLE(of, moxart_mmc_match);
  584. static struct platform_driver moxart_mmc_driver = {
  585. .probe = moxart_probe,
  586. .remove = moxart_remove,
  587. .driver = {
  588. .name = "mmc-moxart",
  589. .of_match_table = moxart_mmc_match,
  590. },
  591. };
  592. module_platform_driver(moxart_mmc_driver);
  593. MODULE_ALIAS("platform:mmc-moxart");
  594. MODULE_DESCRIPTION("MOXA ART MMC driver");
  595. MODULE_LICENSE("GPL v2");
  596. MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");