mxs-mmc.c 19 KB

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  1. /*
  2. * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
  3. * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
  4. *
  5. * Copyright 2008 Embedded Alley Solutions, Inc.
  6. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along
  19. * with this program; if not, write to the Free Software Foundation, Inc.,
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/init.h>
  24. #include <linux/ioport.h>
  25. #include <linux/of.h>
  26. #include <linux/of_device.h>
  27. #include <linux/of_gpio.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/delay.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/dmaengine.h>
  33. #include <linux/highmem.h>
  34. #include <linux/clk.h>
  35. #include <linux/err.h>
  36. #include <linux/completion.h>
  37. #include <linux/mmc/host.h>
  38. #include <linux/mmc/mmc.h>
  39. #include <linux/mmc/sdio.h>
  40. #include <linux/mmc/slot-gpio.h>
  41. #include <linux/gpio.h>
  42. #include <linux/regulator/consumer.h>
  43. #include <linux/module.h>
  44. #include <linux/stmp_device.h>
  45. #include <linux/spi/mxs-spi.h>
  46. #define DRIVER_NAME "mxs-mmc"
  47. #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
  48. BM_SSP_CTRL1_RESP_ERR_IRQ | \
  49. BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
  50. BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
  51. BM_SSP_CTRL1_DATA_CRC_IRQ | \
  52. BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
  53. BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
  54. BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
  55. /* card detect polling timeout */
  56. #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
  57. struct mxs_mmc_host {
  58. struct mxs_ssp ssp;
  59. struct mmc_host *mmc;
  60. struct mmc_request *mrq;
  61. struct mmc_command *cmd;
  62. struct mmc_data *data;
  63. unsigned char bus_width;
  64. spinlock_t lock;
  65. int sdio_irq_en;
  66. bool broken_cd;
  67. };
  68. static int mxs_mmc_get_cd(struct mmc_host *mmc)
  69. {
  70. struct mxs_mmc_host *host = mmc_priv(mmc);
  71. struct mxs_ssp *ssp = &host->ssp;
  72. int present, ret;
  73. if (host->broken_cd)
  74. return -ENOSYS;
  75. ret = mmc_gpio_get_cd(mmc);
  76. if (ret >= 0)
  77. return ret;
  78. present = mmc->caps & MMC_CAP_NEEDS_POLL ||
  79. !(readl(ssp->base + HW_SSP_STATUS(ssp)) &
  80. BM_SSP_STATUS_CARD_DETECT);
  81. if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
  82. present = !present;
  83. return present;
  84. }
  85. static int mxs_mmc_reset(struct mxs_mmc_host *host)
  86. {
  87. struct mxs_ssp *ssp = &host->ssp;
  88. u32 ctrl0, ctrl1;
  89. int ret;
  90. ret = stmp_reset_block(ssp->base);
  91. if (ret)
  92. return ret;
  93. ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
  94. ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
  95. BF_SSP(0x7, CTRL1_WORD_LENGTH) |
  96. BM_SSP_CTRL1_DMA_ENABLE |
  97. BM_SSP_CTRL1_POLARITY |
  98. BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  99. BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
  100. BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  101. BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  102. BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
  103. writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
  104. BF_SSP(2, TIMING_CLOCK_DIVIDE) |
  105. BF_SSP(0, TIMING_CLOCK_RATE),
  106. ssp->base + HW_SSP_TIMING(ssp));
  107. if (host->sdio_irq_en) {
  108. ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
  109. ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
  110. }
  111. writel(ctrl0, ssp->base + HW_SSP_CTRL0);
  112. writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp));
  113. return 0;
  114. }
  115. static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
  116. struct mmc_command *cmd);
  117. static void mxs_mmc_request_done(struct mxs_mmc_host *host)
  118. {
  119. struct mmc_command *cmd = host->cmd;
  120. struct mmc_data *data = host->data;
  121. struct mmc_request *mrq = host->mrq;
  122. struct mxs_ssp *ssp = &host->ssp;
  123. if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
  124. if (mmc_resp_type(cmd) & MMC_RSP_136) {
  125. cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
  126. cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp));
  127. cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp));
  128. cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp));
  129. } else {
  130. cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
  131. }
  132. }
  133. if (cmd == mrq->sbc) {
  134. /* Finished CMD23, now send actual command. */
  135. mxs_mmc_start_cmd(host, mrq->cmd);
  136. return;
  137. } else if (data) {
  138. dma_unmap_sg(mmc_dev(host->mmc), data->sg,
  139. data->sg_len, ssp->dma_dir);
  140. /*
  141. * If there was an error on any block, we mark all
  142. * data blocks as being in error.
  143. */
  144. if (!data->error)
  145. data->bytes_xfered = data->blocks * data->blksz;
  146. else
  147. data->bytes_xfered = 0;
  148. host->data = NULL;
  149. if (data->stop && (data->error || !mrq->sbc)) {
  150. mxs_mmc_start_cmd(host, mrq->stop);
  151. return;
  152. }
  153. }
  154. host->mrq = NULL;
  155. mmc_request_done(host->mmc, mrq);
  156. }
  157. static void mxs_mmc_dma_irq_callback(void *param)
  158. {
  159. struct mxs_mmc_host *host = param;
  160. mxs_mmc_request_done(host);
  161. }
  162. static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
  163. {
  164. struct mxs_mmc_host *host = dev_id;
  165. struct mmc_command *cmd = host->cmd;
  166. struct mmc_data *data = host->data;
  167. struct mxs_ssp *ssp = &host->ssp;
  168. u32 stat;
  169. spin_lock(&host->lock);
  170. stat = readl(ssp->base + HW_SSP_CTRL1(ssp));
  171. writel(stat & MXS_MMC_IRQ_BITS,
  172. ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
  173. spin_unlock(&host->lock);
  174. if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
  175. mmc_signal_sdio_irq(host->mmc);
  176. if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
  177. cmd->error = -ETIMEDOUT;
  178. else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
  179. cmd->error = -EIO;
  180. if (data) {
  181. if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
  182. BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
  183. data->error = -ETIMEDOUT;
  184. else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
  185. data->error = -EILSEQ;
  186. else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
  187. BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
  188. data->error = -EIO;
  189. }
  190. return IRQ_HANDLED;
  191. }
  192. static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
  193. struct mxs_mmc_host *host, unsigned long flags)
  194. {
  195. struct mxs_ssp *ssp = &host->ssp;
  196. struct dma_async_tx_descriptor *desc;
  197. struct mmc_data *data = host->data;
  198. struct scatterlist * sgl;
  199. unsigned int sg_len;
  200. if (data) {
  201. /* data */
  202. dma_map_sg(mmc_dev(host->mmc), data->sg,
  203. data->sg_len, ssp->dma_dir);
  204. sgl = data->sg;
  205. sg_len = data->sg_len;
  206. } else {
  207. /* pio */
  208. sgl = (struct scatterlist *) ssp->ssp_pio_words;
  209. sg_len = SSP_PIO_NUM;
  210. }
  211. desc = dmaengine_prep_slave_sg(ssp->dmach,
  212. sgl, sg_len, ssp->slave_dirn, flags);
  213. if (desc) {
  214. desc->callback = mxs_mmc_dma_irq_callback;
  215. desc->callback_param = host;
  216. } else {
  217. if (data)
  218. dma_unmap_sg(mmc_dev(host->mmc), data->sg,
  219. data->sg_len, ssp->dma_dir);
  220. }
  221. return desc;
  222. }
  223. static void mxs_mmc_bc(struct mxs_mmc_host *host)
  224. {
  225. struct mxs_ssp *ssp = &host->ssp;
  226. struct mmc_command *cmd = host->cmd;
  227. struct dma_async_tx_descriptor *desc;
  228. u32 ctrl0, cmd0, cmd1;
  229. ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
  230. cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
  231. cmd1 = cmd->arg;
  232. if (host->sdio_irq_en) {
  233. ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
  234. cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
  235. }
  236. ssp->ssp_pio_words[0] = ctrl0;
  237. ssp->ssp_pio_words[1] = cmd0;
  238. ssp->ssp_pio_words[2] = cmd1;
  239. ssp->dma_dir = DMA_NONE;
  240. ssp->slave_dirn = DMA_TRANS_NONE;
  241. desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
  242. if (!desc)
  243. goto out;
  244. dmaengine_submit(desc);
  245. dma_async_issue_pending(ssp->dmach);
  246. return;
  247. out:
  248. dev_warn(mmc_dev(host->mmc),
  249. "%s: failed to prep dma\n", __func__);
  250. }
  251. static void mxs_mmc_ac(struct mxs_mmc_host *host)
  252. {
  253. struct mxs_ssp *ssp = &host->ssp;
  254. struct mmc_command *cmd = host->cmd;
  255. struct dma_async_tx_descriptor *desc;
  256. u32 ignore_crc, get_resp, long_resp;
  257. u32 ctrl0, cmd0, cmd1;
  258. ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
  259. 0 : BM_SSP_CTRL0_IGNORE_CRC;
  260. get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
  261. BM_SSP_CTRL0_GET_RESP : 0;
  262. long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
  263. BM_SSP_CTRL0_LONG_RESP : 0;
  264. ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
  265. cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
  266. cmd1 = cmd->arg;
  267. if (cmd->opcode == MMC_STOP_TRANSMISSION)
  268. cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
  269. if (host->sdio_irq_en) {
  270. ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
  271. cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
  272. }
  273. ssp->ssp_pio_words[0] = ctrl0;
  274. ssp->ssp_pio_words[1] = cmd0;
  275. ssp->ssp_pio_words[2] = cmd1;
  276. ssp->dma_dir = DMA_NONE;
  277. ssp->slave_dirn = DMA_TRANS_NONE;
  278. desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
  279. if (!desc)
  280. goto out;
  281. dmaengine_submit(desc);
  282. dma_async_issue_pending(ssp->dmach);
  283. return;
  284. out:
  285. dev_warn(mmc_dev(host->mmc),
  286. "%s: failed to prep dma\n", __func__);
  287. }
  288. static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
  289. {
  290. const unsigned int ssp_timeout_mul = 4096;
  291. /*
  292. * Calculate ticks in ms since ns are large numbers
  293. * and might overflow
  294. */
  295. const unsigned int clock_per_ms = clock_rate / 1000;
  296. const unsigned int ms = ns / 1000;
  297. const unsigned int ticks = ms * clock_per_ms;
  298. const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
  299. WARN_ON(ssp_ticks == 0);
  300. return ssp_ticks;
  301. }
  302. static void mxs_mmc_adtc(struct mxs_mmc_host *host)
  303. {
  304. struct mmc_command *cmd = host->cmd;
  305. struct mmc_data *data = cmd->data;
  306. struct dma_async_tx_descriptor *desc;
  307. struct scatterlist *sgl = data->sg, *sg;
  308. unsigned int sg_len = data->sg_len;
  309. unsigned int i;
  310. unsigned short dma_data_dir, timeout;
  311. enum dma_transfer_direction slave_dirn;
  312. unsigned int data_size = 0, log2_blksz;
  313. unsigned int blocks = data->blocks;
  314. struct mxs_ssp *ssp = &host->ssp;
  315. u32 ignore_crc, get_resp, long_resp, read;
  316. u32 ctrl0, cmd0, cmd1, val;
  317. ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
  318. 0 : BM_SSP_CTRL0_IGNORE_CRC;
  319. get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
  320. BM_SSP_CTRL0_GET_RESP : 0;
  321. long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
  322. BM_SSP_CTRL0_LONG_RESP : 0;
  323. if (data->flags & MMC_DATA_WRITE) {
  324. dma_data_dir = DMA_TO_DEVICE;
  325. slave_dirn = DMA_MEM_TO_DEV;
  326. read = 0;
  327. } else {
  328. dma_data_dir = DMA_FROM_DEVICE;
  329. slave_dirn = DMA_DEV_TO_MEM;
  330. read = BM_SSP_CTRL0_READ;
  331. }
  332. ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
  333. ignore_crc | get_resp | long_resp |
  334. BM_SSP_CTRL0_DATA_XFER | read |
  335. BM_SSP_CTRL0_WAIT_FOR_IRQ |
  336. BM_SSP_CTRL0_ENABLE;
  337. cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
  338. /* get logarithm to base 2 of block size for setting register */
  339. log2_blksz = ilog2(data->blksz);
  340. /*
  341. * take special care of the case that data size from data->sg
  342. * is not equal to blocks x blksz
  343. */
  344. for_each_sg(sgl, sg, sg_len, i)
  345. data_size += sg->length;
  346. if (data_size != data->blocks * data->blksz)
  347. blocks = 1;
  348. /* xfer count, block size and count need to be set differently */
  349. if (ssp_is_old(ssp)) {
  350. ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
  351. cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
  352. BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
  353. } else {
  354. writel(data_size, ssp->base + HW_SSP_XFER_SIZE);
  355. writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
  356. BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
  357. ssp->base + HW_SSP_BLOCK_SIZE);
  358. }
  359. if (cmd->opcode == SD_IO_RW_EXTENDED)
  360. cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
  361. cmd1 = cmd->arg;
  362. if (host->sdio_irq_en) {
  363. ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
  364. cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
  365. }
  366. /* set the timeout count */
  367. timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns);
  368. val = readl(ssp->base + HW_SSP_TIMING(ssp));
  369. val &= ~(BM_SSP_TIMING_TIMEOUT);
  370. val |= BF_SSP(timeout, TIMING_TIMEOUT);
  371. writel(val, ssp->base + HW_SSP_TIMING(ssp));
  372. /* pio */
  373. ssp->ssp_pio_words[0] = ctrl0;
  374. ssp->ssp_pio_words[1] = cmd0;
  375. ssp->ssp_pio_words[2] = cmd1;
  376. ssp->dma_dir = DMA_NONE;
  377. ssp->slave_dirn = DMA_TRANS_NONE;
  378. desc = mxs_mmc_prep_dma(host, 0);
  379. if (!desc)
  380. goto out;
  381. /* append data sg */
  382. WARN_ON(host->data != NULL);
  383. host->data = data;
  384. ssp->dma_dir = dma_data_dir;
  385. ssp->slave_dirn = slave_dirn;
  386. desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  387. if (!desc)
  388. goto out;
  389. dmaengine_submit(desc);
  390. dma_async_issue_pending(ssp->dmach);
  391. return;
  392. out:
  393. dev_warn(mmc_dev(host->mmc),
  394. "%s: failed to prep dma\n", __func__);
  395. }
  396. static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
  397. struct mmc_command *cmd)
  398. {
  399. host->cmd = cmd;
  400. switch (mmc_cmd_type(cmd)) {
  401. case MMC_CMD_BC:
  402. mxs_mmc_bc(host);
  403. break;
  404. case MMC_CMD_BCR:
  405. mxs_mmc_ac(host);
  406. break;
  407. case MMC_CMD_AC:
  408. mxs_mmc_ac(host);
  409. break;
  410. case MMC_CMD_ADTC:
  411. mxs_mmc_adtc(host);
  412. break;
  413. default:
  414. dev_warn(mmc_dev(host->mmc),
  415. "%s: unknown MMC command\n", __func__);
  416. break;
  417. }
  418. }
  419. static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  420. {
  421. struct mxs_mmc_host *host = mmc_priv(mmc);
  422. WARN_ON(host->mrq != NULL);
  423. host->mrq = mrq;
  424. if (mrq->sbc)
  425. mxs_mmc_start_cmd(host, mrq->sbc);
  426. else
  427. mxs_mmc_start_cmd(host, mrq->cmd);
  428. }
  429. static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  430. {
  431. struct mxs_mmc_host *host = mmc_priv(mmc);
  432. if (ios->bus_width == MMC_BUS_WIDTH_8)
  433. host->bus_width = 2;
  434. else if (ios->bus_width == MMC_BUS_WIDTH_4)
  435. host->bus_width = 1;
  436. else
  437. host->bus_width = 0;
  438. if (ios->clock)
  439. mxs_ssp_set_clk_rate(&host->ssp, ios->clock);
  440. }
  441. static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  442. {
  443. struct mxs_mmc_host *host = mmc_priv(mmc);
  444. struct mxs_ssp *ssp = &host->ssp;
  445. unsigned long flags;
  446. spin_lock_irqsave(&host->lock, flags);
  447. host->sdio_irq_en = enable;
  448. if (enable) {
  449. writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
  450. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  451. writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
  452. ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET);
  453. } else {
  454. writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
  455. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  456. writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
  457. ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
  458. }
  459. spin_unlock_irqrestore(&host->lock, flags);
  460. if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) &
  461. BM_SSP_STATUS_SDIO_IRQ)
  462. mmc_signal_sdio_irq(host->mmc);
  463. }
  464. static const struct mmc_host_ops mxs_mmc_ops = {
  465. .request = mxs_mmc_request,
  466. .get_ro = mmc_gpio_get_ro,
  467. .get_cd = mxs_mmc_get_cd,
  468. .set_ios = mxs_mmc_set_ios,
  469. .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
  470. };
  471. static const struct platform_device_id mxs_ssp_ids[] = {
  472. {
  473. .name = "imx23-mmc",
  474. .driver_data = IMX23_SSP,
  475. }, {
  476. .name = "imx28-mmc",
  477. .driver_data = IMX28_SSP,
  478. }, {
  479. /* sentinel */
  480. }
  481. };
  482. MODULE_DEVICE_TABLE(platform, mxs_ssp_ids);
  483. static const struct of_device_id mxs_mmc_dt_ids[] = {
  484. { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, },
  485. { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, },
  486. { /* sentinel */ }
  487. };
  488. MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
  489. static int mxs_mmc_probe(struct platform_device *pdev)
  490. {
  491. const struct of_device_id *of_id =
  492. of_match_device(mxs_mmc_dt_ids, &pdev->dev);
  493. struct device_node *np = pdev->dev.of_node;
  494. struct mxs_mmc_host *host;
  495. struct mmc_host *mmc;
  496. struct resource *iores;
  497. int ret = 0, irq_err;
  498. struct regulator *reg_vmmc;
  499. struct mxs_ssp *ssp;
  500. irq_err = platform_get_irq(pdev, 0);
  501. if (irq_err < 0)
  502. return irq_err;
  503. mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
  504. if (!mmc)
  505. return -ENOMEM;
  506. host = mmc_priv(mmc);
  507. ssp = &host->ssp;
  508. ssp->dev = &pdev->dev;
  509. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  510. ssp->base = devm_ioremap_resource(&pdev->dev, iores);
  511. if (IS_ERR(ssp->base)) {
  512. ret = PTR_ERR(ssp->base);
  513. goto out_mmc_free;
  514. }
  515. ssp->devid = (enum mxs_ssp_id) of_id->data;
  516. host->mmc = mmc;
  517. host->sdio_irq_en = 0;
  518. reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc");
  519. if (!IS_ERR(reg_vmmc)) {
  520. ret = regulator_enable(reg_vmmc);
  521. if (ret) {
  522. dev_err(&pdev->dev,
  523. "Failed to enable vmmc regulator: %d\n", ret);
  524. goto out_mmc_free;
  525. }
  526. }
  527. ssp->clk = devm_clk_get(&pdev->dev, NULL);
  528. if (IS_ERR(ssp->clk)) {
  529. ret = PTR_ERR(ssp->clk);
  530. goto out_mmc_free;
  531. }
  532. ret = clk_prepare_enable(ssp->clk);
  533. if (ret)
  534. goto out_mmc_free;
  535. ret = mxs_mmc_reset(host);
  536. if (ret) {
  537. dev_err(&pdev->dev, "Failed to reset mmc: %d\n", ret);
  538. goto out_clk_disable;
  539. }
  540. ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
  541. if (!ssp->dmach) {
  542. dev_err(mmc_dev(host->mmc),
  543. "%s: failed to request dma\n", __func__);
  544. ret = -ENODEV;
  545. goto out_clk_disable;
  546. }
  547. /* set mmc core parameters */
  548. mmc->ops = &mxs_mmc_ops;
  549. mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
  550. MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL | MMC_CAP_CMD23;
  551. host->broken_cd = of_property_read_bool(np, "broken-cd");
  552. mmc->f_min = 400000;
  553. mmc->f_max = 288000000;
  554. ret = mmc_of_parse(mmc);
  555. if (ret)
  556. goto out_free_dma;
  557. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  558. mmc->max_segs = 52;
  559. mmc->max_blk_size = 1 << 0xf;
  560. mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff;
  561. mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff;
  562. mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev);
  563. platform_set_drvdata(pdev, mmc);
  564. spin_lock_init(&host->lock);
  565. ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
  566. dev_name(&pdev->dev), host);
  567. if (ret)
  568. goto out_free_dma;
  569. ret = mmc_add_host(mmc);
  570. if (ret)
  571. goto out_free_dma;
  572. dev_info(mmc_dev(host->mmc), "initialized\n");
  573. return 0;
  574. out_free_dma:
  575. dma_release_channel(ssp->dmach);
  576. out_clk_disable:
  577. clk_disable_unprepare(ssp->clk);
  578. out_mmc_free:
  579. mmc_free_host(mmc);
  580. return ret;
  581. }
  582. static int mxs_mmc_remove(struct platform_device *pdev)
  583. {
  584. struct mmc_host *mmc = platform_get_drvdata(pdev);
  585. struct mxs_mmc_host *host = mmc_priv(mmc);
  586. struct mxs_ssp *ssp = &host->ssp;
  587. mmc_remove_host(mmc);
  588. if (ssp->dmach)
  589. dma_release_channel(ssp->dmach);
  590. clk_disable_unprepare(ssp->clk);
  591. mmc_free_host(mmc);
  592. return 0;
  593. }
  594. #ifdef CONFIG_PM_SLEEP
  595. static int mxs_mmc_suspend(struct device *dev)
  596. {
  597. struct mmc_host *mmc = dev_get_drvdata(dev);
  598. struct mxs_mmc_host *host = mmc_priv(mmc);
  599. struct mxs_ssp *ssp = &host->ssp;
  600. clk_disable_unprepare(ssp->clk);
  601. return 0;
  602. }
  603. static int mxs_mmc_resume(struct device *dev)
  604. {
  605. struct mmc_host *mmc = dev_get_drvdata(dev);
  606. struct mxs_mmc_host *host = mmc_priv(mmc);
  607. struct mxs_ssp *ssp = &host->ssp;
  608. return clk_prepare_enable(ssp->clk);
  609. }
  610. #endif
  611. static SIMPLE_DEV_PM_OPS(mxs_mmc_pm_ops, mxs_mmc_suspend, mxs_mmc_resume);
  612. static struct platform_driver mxs_mmc_driver = {
  613. .probe = mxs_mmc_probe,
  614. .remove = mxs_mmc_remove,
  615. .id_table = mxs_ssp_ids,
  616. .driver = {
  617. .name = DRIVER_NAME,
  618. .pm = &mxs_mmc_pm_ops,
  619. .of_match_table = mxs_mmc_dt_ids,
  620. },
  621. };
  622. module_platform_driver(mxs_mmc_driver);
  623. MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
  624. MODULE_AUTHOR("Freescale Semiconductor");
  625. MODULE_LICENSE("GPL");
  626. MODULE_ALIAS("platform:" DRIVER_NAME);